WO2002017362A2 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices - Google Patents

Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices Download PDF

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Publication number
WO2002017362A2
WO2002017362A2 PCT/US2001/026298 US0126298W WO0217362A2 WO 2002017362 A2 WO2002017362 A2 WO 2002017362A2 US 0126298 W US0126298 W US 0126298W WO 0217362 A2 WO0217362 A2 WO 0217362A2
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WO
WIPO (PCT)
Prior art keywords
semiconductor
nanometers
doped
ofthe
elongated
Prior art date
Application number
PCT/US2001/026298
Other languages
French (fr)
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WO2002017362A8 (en
Inventor
Charles M. Lieber
Ying Cui
Xiangfeng Duan
Yung-Sheng Huang
Original Assignee
President And Fellows Of Harvard College
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by President And Fellows Of Harvard College filed Critical President And Fellows Of Harvard College
Priority to JP2002521336A priority Critical patent/JP5013650B2/en
Priority to KR1020037002636A priority patent/KR100791732B1/en
Priority to MXPA03001605A priority patent/MXPA03001605A/en
Priority to EP01966109A priority patent/EP1314189B1/en
Priority to KR1020087015375A priority patent/KR100984585B1/en
Priority to AU8664901A priority patent/AU8664901A/en
Priority to AU2001286649A priority patent/AU2001286649B2/en
Priority to CA2417992A priority patent/CA2417992C/en
Publication of WO2002017362A2 publication Critical patent/WO2002017362A2/en
Publication of WO2002017362A8 publication Critical patent/WO2002017362A8/en
Priority to AU2007202897A priority patent/AU2007202897B2/en

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Abstract

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longtiudinal section of such a semiconductor, a ratio of the length of the section to a longest width which is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

Description


  DOPED ELONGATED SEMICONDUCTORS, GROWING SUCH
SEMICONDUCTORS, DEVICES INCLUDING SUCH SEMICONDUCTORS
AND FABRICATING SUCH DEVICES RELATED APPLICATIONS
This application claims priority under 35 U.S.C. [section]119(e) to commonly-owned, copending U.S. Provisional Patent Application Serial No. 60/226,835, entitled, "Semiconductor Nanowires", filed August 22, 2000; Serial No. 60/292,121, entitled, "Semiconductor Nanowires", filed May 18, 2001 ; Serial No. 60/254,745, entitled,
"Nanowire and Nanotube Nanosensors," filed December 11, 2000; Serial No. 60/292,035, entitled "Nanowire and Nanotube Nanosensors," filed May 18, 2001;

   Serial No. 60/292,045, entitled "Nanowire Electronic Devices Including Memory and Switching Devices," filed May IS, 2001; and Serial No. 60/291,896, entitled "Nanowire Devices Including Emissive Elements and Sensors," filed May 18, 2001 , each of which is hereby inco[phi]orated by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates generally to sub-microelectronic semiconductor devices, and more particularly to nanometer-scale semiconductor articles, for example, nanowires, doped to provide n-type and p-type conductivity, the growth of such articles, and the arrangement of such articles to fabricate devices.
BACKGROUND Small-scale electronic technology relies to a large extent on doping of various materials.

   Doping of semiconductor materials to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, and the like are well known.
Typical state-of-the-art semiconductor fabrication facilities involve relatively high cost, and require a clean room and the use of toxic chemicals such as hydrogen fluoride. While semiconductor and niicrofabrication technology is well-developed, there is a continuing need for improvements, preferably including smaller-scale, envhonmentallyfriendly fabrication, at lower cost.

   SUMMARY
In an embodiment, provided is a free-standing bulk-doped semiconductor comprising at least one portion having a smallest width of less than 5 0 nanometers.
In another aspect of this embodiment, the semiconductor comprises: an interior 5 core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor.
In another aspect of this embodiment, the semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or l o greater than 10 : 1 , or greater than 100 : 1 , or even greater than 1000:1
In various aspects of this embodiment, at least one portion of the semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 15 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, 20 GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe,
HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeS[iota]N2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate 25 combination of two ore more such semiconductors.
In various aspects of this embodiment, the semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table;

   a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As 30 and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te. In another aspect of this embodiment, the semiconductor is part of a device. In another aspect of this embodiment, the semiconductor is n-doped. In various optional features of this aspect, the semiconductor is either lightly n-doped or heavily n-doped.
In yet another aspect of this embodiment, the semiconductor is p-doped.

   In various optional features embodiments of this aspect, the semiconductor is either lightly p-doped or heavily p-doped.
In another aspect of this embodiment, the semiconductor is a single crystal.
In additional various aspects of this embodiment, the semiconductor is magnetic; the semiconductor comprises a dopant making the semiconductor magnetic the semiconductor is ferromagnetic; the semiconductor comprises a dopant that makes the semiconductor ferromagnetic; and or the semiconductor comprises manganese.
In another embodiment, provided is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers.

   In an aspect of this embodiment, the semiconductor is free-standing.
In another aspect of this embodiment, the semiconductor comprises: an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor.
In various aspects of this embodiment, at any point along the longitudinal axis of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater than 1000:

  1
In various aspects of this embodiment, at least one longitudinal section of the semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, at least one longitudinal section of the semiconductor has a largest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment,

   the semiconductor comprises a semiconductor from a group consisting of: Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN InP[Lambda]nAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, S13N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two or more such semiconductors.
In various aspects of this embodiment, the semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table;

   an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type dopant is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
In another aspect of this embodiment, the semiconductor is part of a device.
In another aspect of this embodiment, the semiconductor is n-doped. In various optional features of this aspect, the semiconductor is either lightly n-doped or heavily ndoped.
In yet another aspect of this embodiment, the semiconductor is p-doped.

   In various optional features embodiments of this aspect, the semiconductor is either lightly p-doped or heavily p-doped.
In another aspect of this embodiment, the semiconductor is a single crystal. In another embodiment, provided is a doped semiconductor comprising a single crystal.
In an aspect of this embodiment, the semiconductor is bulk-doped.
In an aspect of this embodiment, the semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4: 1 , or greater than 10:1, or greater than 100:1, or even greater than 1000:1
In various aspects of this embodiment, at least one portion of the semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP[Lambda]nAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two or more such semiconductors.
In various aspects of this embodiment, the semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of:

   B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type dopant is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te.
In yet another embodiment, provided is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, where a phenomena produced by a section of the bulk-doped semiconductor exhibits a quantum confinement caused by a dimension of the section.
In another aspect of this embodiment, the longitudinal section is capable of emitting light in response to excitation, wherein a wavelength of the emitted light is related to the width.

   In optional features of this aspect: the wavelength of the emitted light is a function of the width; the longitudinal section is capable of transporting electrical carriers without scattering; the longitudinal section is capable of transporting electrical carriers such that the electrical carriers pass through the longitudinal section ballistically; the longitudinal section is capable of transporting electrical carriers such that the electrical carriers pass through the longitudinal section coherently; the longitudinal section is capable of transporting electrical carriers such that the electrical carriers are spinpolarized;

   and/or the longitudinal section is capable of transporting electrical carriers such that the spin-polarized electrical carriers pass through the longitudinal section without losing spin information.
In another embodiment, provided is a solution comprising one or more doped semiconductors, wherein at least one of the semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
In an aspect of this embodiment, the at least one semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater 1000:1.
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb,
GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb,
GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe,
HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO,
PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se,
Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.

   In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te.
In another embodiment, provided is a device comprising one or more doped semiconductors, wherein at least one of the semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.

   In an aspect of this embodiment, the device comprises at least two doped semiconductors, wherein both of the at least two doped semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein a first of the at least two doped semiconductors exhibits quantum confinement and a second of the at least two doped semiconductor manipulates the quantum confinement of the first.
In another aspect of this embodiment, the device comprises at least two doped semiconductor, wherein both of the at least two doped semiconductors is at least one of the following:

   a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. In various optional features of this embodiment: the at least two bulk-doped semiconductors are in physical contact with each other; a first of the at least two bulk-doped semiconductors is of a first conductivity type, and a second of the at least two bulk-doped semiconductors is of a second conductivity type; the first conductivity type is n-type, and the second type of conductivity type is ptype; and/or the at least two bulk-doped semiconductors form a p-n junction.

   In various aspects of this embodiment, the device comprises one or more of the following:, a switch; a diode; a Light-Emitting Diode; a tunnel diode; a Schottky diode; a Bipolar Junction Transistor; a Field Effect Transistor; an inverter; a complimentary inverter; an optical sensor; a sensor for an analyte (e.g., DNA); a memory device; a dynamic memory device; a static memory device; a laser; a logic gate; an AND gate; a NAND gate; an EXCLUSIVE-AND gate; an OR gate; a NOR gate; an EXCLUS1NE-OR gate; a latch; a register; clock circuitry; a logic array; a state machine; a programmable circuit; an amplifier; a transformer; a signal processor; a digital circuit; an analog circuit; a light emission source; a photolurninescent device; an elecfroluminescent device; a rectifier; a photodiode; a p-n solar cell.; a phototransistor; a single-electron transistor; a single-photon emitter;

   a single-photon detector; a spintronic device; an ultra-sha[phi] tip for atomic force microscope; a scanning tunneling microscope; a field-emission device; a photoluminescence tag; a photovoltaic device; a photonic band gap materials; a scanning near field optical microscope tips; and a circuit that has digital and analog components. In various aspects of this embodiment, for a device that includes one or more of the device components listed in the previous paragraph, one of the device components may include the at least one semiconductor.

   In an optional feature of this aspect, a plurality of the components of the device may include at least one semiconductor, where, for each device component, the at least one semiconductor is at least one of the following: a single crystal, an elongated and bulk-doped semicond[mu]ctor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
In an aspect of this embodiment, the at least one semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater than 1000:1
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2,< CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.

   In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group TV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
In another aspect of this embodiment, the device comprises another semiconductor that is electrically coupled to the at least one bulk-doped semiconductor.

   In another aspect of this embodiment, the device comprises another semiconductor that is optically coupled to the at least one bulk-doped semiconductor. In yet another aspect of this embodiment, the device comprises another semiconductor that is magnetically coupled to the at least one bulk-doped semiconductor.
In another aspect of this embodiment, the device comprises another semiconductor that physically contacts the at least one bulk-doped semiconductor.
In various aspects of this embodiment, the at least one semiconductor is coupled to one or more of: an electrical contact; an optical contact; or a magnetic contact. In another aspect of this embodiment, a conductivity of the at least one semiconductor is controllable in response to a signal.

   In various optional features of this aspect: the conductivity of the at least one semiconductor is controllable to have any value within a range of values; the at least one semiconductor is switchable between two or more states; the at least one semiconductor is switchable between a conducting state and an insulating state by the signal; two or more states of the at least one semiconductor are maintainable without an applied signal; the conductivity of the at least one semiconductor is controllable in response to an electrical signal; the conductivity of the at least one semiconductor is controllable in response to an optical signal; the conductivity of the at least one semiconductor is controllable in response to a magnetic signal;

   and/or the conductivity of the at least one semiconductor is controllable in response to a signal of a gate terminal.
In another aspect of this embodiment, at least two of the semiconductors are arranged in an array, and at least one of the semiconductors arranged in the array is a bulkdoped semiconductor comprising at least one portion having a smallest width of less than 500 nanometers. In an optional feature of this aspect, the array is an ordered array.

   In another optional feature of this embodiment, the array is not an ordered array.
In yet another aspect of this embodiment, the device comprises two or more separate and interconnected circuits, at least one of the circuits not comprising a bulkdoped semiconductor that comprises at least one portion having a smallest width of less than 500 nanometers.
In another aspect of this embodiment, the device is embodied on a chip having one or more pinouts.

   In an optional feature of this embodiment, the chip comprises separate and interconnected circuits, at least one of the circuits not comprising a bulk-doped semiconductor that comprises at least one portion having a smallest width of less than 500 nanometers.
In another embodiment, provided is a collection of reagents for growing a bulkdoped semiconductor that comprises at least one portion having a smallest width of less than 500 nanometers, the collection comprising a semiconductor reagent and a dopant reagent. In an aspect of this embodiment, the at least one semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater than 1000:1
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.

   In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of: Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe,
HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.
In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of:

   a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te.
In another embodiment, a semiconductor is doped during growth of the semiconductor.
In various aspects of this embodiment: the semiconductor is free-standing; the semiconductor has a smallest width of no more than 100 nanometers; an extent of the doping is controlled; the doped semiconductor is grown by applying energy to a collection of molecules, the collection of molecules comprising molecules of the semiconductor and molecules of a dopant; an extent of the doping is controlled; a ratio of an amount of the semiconductor molecules to an amount of the dopant molecules is controlled, the molecules are vaporized using a laser to form vaporized molecules; the semiconductor is grown from the vaporized molecules; the vaporized molecules are condensed into a liquid cluster; the semiconductor is grown from the liquid cluster;

   growing the semiconductor is performed using laser-assisted catalytic growth; the collection of molecules comprises a cluster of molecules of a catalyst material; a width of the semiconductor is controlled; and/or the width of the semiconductor is controlled by controlling a width of the catalyst cluster.

   In additional aspects of this embodiment: the act of doping includes performing chemical vapor deposition on at least the molecules; the grown semiconductor has at least one portion having a smallest width of less than 20 nanometers; the grown semiconductor has at least one portion having a smallest width of less than 10 nanometers; and/or the grown semiconductor has at least one portion having a smallest width of less than 5 nanometers.
In yet other additional aspects of this embodiment: the grown semiconductor is magnetic; the semiconductor is doped with a material that makes the grown semiconductor magnetic; the grown semiconductor is ferromagnetic; the semiconductor is doped with a material that makes the grown semiconductor ferromagnetic; the semiconductor is doped with manganese.
In another aspect of this embodiment, the at least one semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4: 1, or greater than 10:1, or greater than 100:1 or even greater than 1000:1.
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe,
HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.
In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table;

   a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
In another embodiment; a device is fabricated.

   One or more semiconductors are contacted to a surface, where at least one of the semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.

   In various aspects of this embodiment: the surface is a substrate; prior to contacting the surface, at least one of the semiconductors is grown by applying energy to molecules of a semiconductor and molecules of a dopant; a solution is contacted comprising the one or more semiconductors to the surface; one or more of the semiconductors are aligned on the surface using an electric field; an electric field is generated between at least two electrodes and one or more of the semiconductors are positioned between the electrodes; another solution comprising one or more other semiconductors is contacted to the surface, where at least one of the other semiconductor is a bulk-doped semiconductor comprising at least one portion having a smallest width of less than 500 nanometers; the surface is conditioned to attach the one or more contacted semiconductors to the surface;

   forming channels on the surface; patterns are formed on the surface; one or more of the semiconductors are aligned on the surface using an electric field; the at least one semiconductor is elongated.
In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater than 1000:

  1
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B P(BP6), B-Si, Si-C, Si¯Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2,
ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, , Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.
In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table;

   a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te.
In another embodiment, generating light is generated by applying energy to one or more semiconductors causing the one or more semiconductors to emit light, wherein at least one of the semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
In an aspect of this embodiment, the at least one semiconductor is elongated.

   In various optional features of this aspect, at any point along a longitudinal section of the semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1 or even greater than 1000:1
In various aspects of this embodiment, at least one portion of the at least one semiconductor has a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers.
In various aspects of this embodiment, the at least one semiconductor comprises a semiconductor from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, BP(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO, and an appropriate combination of two ore more such semiconductors.

   In various aspects of this embodiment, the at least one semiconductor comprises a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an-type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te.
In various aspects of this embodiment: the at least one semiconductor is a bulkdoped; the semiconductor comprises a direct-band-gap semiconductor; a voltage is applied across a junction of two crossed semiconductors, each semiconductor having a smallest width of less than 500 nanometers; each semiconductor has a smallest width of less than 100 nanometers; a wavelength of the emitted light is controlled by controlling a dimension of the at least one semiconductor having a smallest width of less than 100 nanometers; the semiconductor is elongated, and a width of the elongated semiconductor is controlled;

   the semiconductor has a property that a mass of the semiconductor emits light at a first wavelength if the mass has a minimum shortest dimension, and the controlled dimension of the semiconductor is less than the minimum shortest dimension.
In another embodiment, a device having at least a doped semiconductor component and one or more other components is fabricated.

   A semiconductor is doped during its growth to produce the doped semiconductor component, and the doped semiconductor component is attached to at least one of the one or more other components.
In an aspect of this embodiment, the doped semiconductor is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers
In various aspects of this embodiment: the semiconductor component is at least part of a nanowire; the semiconductor is doped during growth of the semiconductor.

   In another embodiment provided is a process for controllably assembling a semiconductor device having elongated elements with a characteristic dimension in a transverse direction of the element on a nanometer scale, the process comprising: producing at least one first elements of a first doping type, orienting said first element in a first dhection, and connecting said first element to at least one first contact to allow an electrical current to flow through the first element.
In various aspects of this embodiment:

   the process further comprises producing at least one second elements of a second doping type, orienting said second element in a second direction different from the first direction, enabling an electrical contact between the first element and the second element, and connecting said second element to at least one second contact to allow an electrical current to flow between the first and second element; the process further comprises connecting said first element to spaced-apart contacts and arranging a gate electrode proximate to the first element between the spacedapart contacts, thereby forming an FET; the first doping type is one of n-type or p-type; the second doping type is n-type if the first doping type is p-type, and p-type if the first doping type is n-type; the first element is oriented by applying at least one of an electric field or a fluid flow;

   the first element is suspended in the fluid flow; the first element is oriented by applying a mechanical tool; the second element is oriented by applying at least one of an electric field or a fluid flow; the second element is suspended in the fluid flow; the second element is oriented by applying a mechanical tool
In yet another embodiment, provided is a semiconductor device, comprising: a silicon substrate having an array of metal contacts;

   a crossbar switch element formed h electrical communication with the array and having a first bar formed of a p-type semiconductor nanowire, and a second bar formed of an n-type semiconductor nanowire and being spaced away from the first bar and being disposed transversely thereto.
In an aspect of this embodiment, the second bar is spaces between 1-10 nm from the first bar In another embodiment, provided is a method for manufacturing a nanowire semiconductor device comprising positioning a first nanowire between two contact points by applying a potential between the contact points; positioning a second nanowire between two other contact points.

   In another embodiment, provided is a method for manufacturing a nanowire semiconductor device comprising forming a surface with one or more regions that selectively attract nanowires.
In another embodiment, provided is a method for manufacturing a light-emitting diode from nanowires, the diode having an emission wavelength determined by a dimension of a p-n junction between two doped nanowires .
In yet another embodiment, provided is a method for manufacturing a semiconductor junction by crossing a p-type nanowire and an n-type nanowire.
En another embodiment, provided is a method of assembling one or more elongated structures on a surface, where the method comprising acts of: flowing a fluid that comprises the one or more elongated structures onto the surface;

   and aligning the one or more elongated structures on the surface to form an array of the elongated structures.
In various embodiments of this method: flowing comprises flowing the fluid in a first direction and aligning comprises aligning the one or more elongated structures as the fluid flows in the first direction to form a first layer of arrayed structures, and the method further comprises changing a direction of the flow from the first dhection to a second direction, and repeating the acts of flowing and aligning; at least a first elongated structure from the first layer contacts at least a second elongated structure from the second array; one of the first and second elongated structures is doped semiconductor of a first conductivity type and another of first and second elongated structures is doped semiconductor of a second conductivity type;

   the first conductivity type is p-type and the second conductivity type is n-type, and wherein the first and second elongated structures form a p-n junction; the surface is a surface of a substrate; the method further comprises transferring the array of elongated structures from the surface of the substrate to a surface of another substrate; transferring comprises stamping; the one or more elongated structured are aligned onto the surface while still comprised in the fluid; conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface, and the act of aligning comprises attracting the one or more elongated structures to the particular positions using the one or more functionalities; the act of conditioning comprises conditioning the surface with one or more molecules;

   the act of conditioning comprises conditioning the surface with one or more charges; the act of conditioning comprises conditioning the surface with one or more magnetos; the act of conditioning comprises conditioning the surface with one or more light intensities; conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using chemical force; the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using optical force; the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using electrostatic force;

   the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using magnetic force; the method further comprises patterning the surface to receive the one or more elongated structures at particular positions on the surface; the act of patterning comprise creating physical patterns on the surface; the physical patterns are trenches; the physical patterns are steps; the surface is a surface of a substrate, and creating physical patterns on the surface comprises using crystal lattice steps of the substrate; the surface is a surface of a substrate, and creating physical patterns on the surface comprises using self-assembled di-block polymer strips; creating physical patterns on the surface comprises using patterns;

   creating physical patterns on the surface comprises using imprinted patterns; and/or the act of flowing comprises controlling the flow of the fluid using a channel.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers;

   at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb<'>, GaN/GaP/GaAs/GaSb, IriN/Irtf /InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, disclosed is method of assembling one or more elongated structures on a surface, wherein one or more of the elongated structures are at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface,

   and aligning the one or more elongated structures by attracting the one or more elongated structures to the particular positions using the one or more functionalities.
In various aspects of this embodiment: the act of conditioning comprises conditioning the surface with one or more molecules; the act of conditioning comprises conditioning the surface with one or more charges; the act of conditioning comprises conditioning the surface with one or more magnetos; the act of conditioning comprises conditioning the surface with one or more light intensities; conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using chemical force;

   the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using optical force; the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using electrostatic force; and/or the act of conditioning comprises conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using magnetic force.

   In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following:

   a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, disclosed is a method of assembling a plurality of elongated structures on a surface, wherein one or more of the elongated structures are at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of: depositing the plurality of elongated structures onto the surface; and electrically charging the surface to produce electrostatic forces between two or more of the plurality of the elongated structures.

   In various embodiments of this embodiment: the electrostatic forces cause the two or more elongated structures to align themselves; the electrostatic forces cause the two or more elongated structures to align themselves into one or more patterns; and/or the one or more patterns comprise a parallel array.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers;

   at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of: Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.

   In yet another embodiment, provided is a method of assembling a plurality of elongated structures on a surface, wherein one or more of the elongated structures are at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of: dispersing the one or more elongated structures on a surface of a liquid phase to form a Langmuir-Blodgett film; compressing the Langmuir-Blodgett film; and transferring the compressed Langmuir-Blodgett film onto a surface.
In an aspect of this embodiment: the surface id the surface of a substrate.

   In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following:

   a single crystal, an elongated and bulk doped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, provided is a method of assembling a plurality of one or more elongated structures on a surface, wherein at least one of the elongated structures are at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of: dispersing the one or more elongated structures in a flexible matrix;

   stretching the flexible matrix in a dhection to produce a shear force on the one or more elongated structures that causes the at least one elongated structure to align in the direction; removing the flexible matrix; and transferring the at least one aligned elongated structure to a surface.
In various aspects of this embodiment: the direction is parallel to a plane of the surface the act of stretching comprises stretching the flexible matrix with an electrically induced force; the act of stretching comprises stretching the flexible matrix with an optically-induced force; the act of stretching comprises stretching the flexible matrix with a mechanically-induced force; the act of stretching comprises stretching the flexible matrix with a magnetically-induced force; the surface is a surface of a substrate; the flexible matrix is a polymer.
In additional aspects of this embodiment:

   at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following:

   a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, provided is a system for growing a doped semiconductor, the system comprising: means for providing a molecules of the semiconductor and molecules of a dopant; and means for doping the molecules of the semiconductor with the molecules of the dopant during growth of the semiconductor to produce the doped semiconductor.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor;

   at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an n type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, provided is a system for assembling one or more elongated structures on a surface, the system comprising: means for flowing a fluid that comprises the one or more elongated structures onto the surface; and means for aligning the one or more elongated structures on the surface to form an array of the elongated structures.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor;

   at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an n type is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In yet another embodiment, provided is a system for assembling one or more elongated structures on a surface, wherein one or more of the elongated structures are at least one of the following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises:

   means for conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface, and means for aUgning the one or more elongated structures by attracting the one or more elongated structures to the particular positions using the one or more functionalities.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers;

   at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP InAs InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe,
BeS BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of: Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.

   In another embodiment, provided is a system for assembling a plurality of elongated structures on a surface, wherein one or more of the elongated sfructures are at least one of the following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises means for depositing the plurality of elongated structures onto the surface; and means for electrically charging the surface to produce electrostatic forces between two or more of the plurality of the elongated structures.

   In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following:

   a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Gen, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consistmg of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, provided is a system for assembling a plurality of elongated structures on a surface, wherein one or more of the elongated structures are at least one of the following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises: means for dispersing the one or more elongated structures on a surface of a liquid phase to form a Langmuir-Blodgett film; means for compressing the Langmuir-Blodgett film;

   and means for transferring the compressed Langmuir-Blodgett film onto a surface.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers; at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following:

   a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of:

   Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
In another embodiment, provided is a system for assembling a plurality of one or more elongated structures on a surface, wherein at least one of the elongated structures are at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises: means for dispersing the one or more elongated structures in a flexible matrix;

   means for stretching the flexible matrix in a direction to produce a shear force on the one or more elongated structures that causes the at least one elongated structure to align in the dhection; means for removing the flexible matrix; and means for transferring the at least one aligned elongated structure to a surface.
In additional aspects of this embodiment: at least one of the elongated structures are semiconductors; at least one of the elongated structures are doped semiconductors; at least one of the elongated structures are bulk-doped semiconductors; at least one of the structures is a doped single-crystal semiconductor; at least one of the structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dhnension less than 500 nanometers;

   at least one of the structures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; at least one of the structures is a doped semiconductor that is at least one of the following: a single crystal, an elongated and bulkdoped semiconductor that, at any point along its longitudinal axis, has a largest crosssectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers; the doped semiconductor comprises a semiconductor selected from a group consisting of:

   Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO; the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of:

   P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an ntype is selected from a group consisting of: Si, Ge, Sn, S, Se and Te; the doped semiconductor is doped during growth of the semiconductor.
The features and advantages of the embodiments described above and other features and advantages of these embodiments will be more readily understood and appreciated from the detailed description below, which should be read together with the accompanying drawing Figs.

   BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:
Fig. 1 is a perspective view of an example of a semiconductor article, or nanowhe, in accordance with an embodiment of the invention;
Fig. 2 is a simplified schematic diagram of an example of a laser assisted catalytic growth process for fabrication of semiconductor nanowires;
Fig. 3 is a schematic diagram that illustrates nanowire growth;
Fig. 4 is a schematic diagram that illusfrates an example of a method for controlling nanowire diameter;
Fig. 5 is a schematic diagram that illustrates nanowire fabrication by deposition on the edge of surface steps;
Fig. 6 is a schematic diagram that illustrates nanowire growth by vapor deposition in or on an elongated template;

   Figs. 7A-7E illustrate orthogonal assembly of semiconductor nanowires to form devices;
Figs. 8A-8C show silicon nanowire current as a function of bias voltage for different doping levels and gate voltages;
Figs. 9 A and 9B show silicon nanowire current as a function of bias voltage for different phosphorous doping levels and gate voltages;
Figs. 10A and 10B show energy band diagrams for p-type and n-type silicon nanowire devices, respectively;
Figs. 11A and 11B show temperature dependent current-voltage curves recorded on a heavily boron doped silicon nanowire; Fig. 12 is a schematic diagram that depicts the use of monodispersed gold colloids as catalysts for the growth of well-defined GaP semiconductor nanowires;
Fig. 13 A shows a FE-SEM image of nanowires synthesized from 28.2 nanometer colloids;
Fig. 13B shows a TEM image of another wire in the sample;

   Figs. 14A-14C show histograms of measured diameters for wires grown from different diameter colloids; Fig. 14D shows a histogram of diameters for wires grown using the previous method without colloids, in which the laser is used to both generate the gold nanoclusters and the GaP reactants;
Fig. 15 shows a pseudobinary phase diagram for gold and gallium arsenide; Figs. 16A-16C show FE-SEM images of different nanowires prepared by laser assisted catalytic growth;
Fig. 17A shows a diffraction contrast TEM image of an approximately 20 nanometer diameter gallium arsenide nanowire;
Figs. 17B-17D show high resolution TEM images of different diameter nanowires;

   Fig. 18 A shows a FE-SEM image of CdSe nanowires prepared by laser assisted catalytic growth;
Fig. 18B shows a diffraction contrast TEM image of an 18 nanometer diameter CdSe nanowire;
Fig. 18C shows a high resolution TEM image of an approximately 13 nanometer diameter CdSe nanowhe;
Fig. 19 is a schematic diagram showing GaN nanowire growth by laser assisted catalytic growth;
Fig. 20 A shows a FE-SEM image of bulk GaN nanowhe synthesized by laser assisted catalytic growth; Fig. 20B shows a PXRD pattern recorded on bulk GaN nanowires;
Fig. 21 A shows a diffraction contrast TEM image of a GaN nanowhe that terminates in a faceted nanoparticle of higher contrast;
Fig. 21 B shows an HRTEM image of another GaN nanowire with a diameter of approximately 10 nanometers;

   Figs. 22A-22C illustrate doping and electrical transport of InP nanowires;
Figs. 23 A-23D illustrate crossed nanowhe junctions and electrical properties;
Figs. 24A-24D illustrate optoelectrical characterization of nanowire P-N junctions;
Fig. 25A shows an EL image taken from a p-type Si and n-type GaN nanojunction;
Fig. 25B shows current as a function of voltage for various gate voltages; Fig. 25C shows an EL spectrum for the nanojunction of Figs. 25A;
Figs. 26A-26D illustrate parallel and orthogonal assembly of nanowires with electric fields;
Figs. 27A-27F illustrate crossed silicon nanowire junctions; Figs. 28A-28D illustrate n<+>pn crossed silicon nanowire bipolar transistors; Figs. 29A-29D illustrate complementary inverters and tunnel diodes; Figs. 30A and 30B are schematics of fluidic channel structures for flow assembly;

   Figs. 31A-31D illustrate parallel assembly of nanowhe arrays; Figs. 32A-32D illustrate assembly of periodic nanowire arrays; and
Figs. 33A-33E illustrate layer-by-layer assembly and transport measurements of crossed nanowire arrays.
DETAILED DESCRIPTION The present invention provides, in one aspect, techniques for controlled doping of materials such as semiconductors at a very small spatial scale, and arrangement of doped materials in position relative to each other to create useful devices. One set of embodiments involves doping of a semiconductor, with a dopant (e.g., boron, aluminum, phosphorous, arsenic, etc.) selected according to whether an n-type or p-type semiconductor is desired.
In various embodiments, this invention involves controlled doping of semiconductors selected from among indium phosphide, gallium arsenide, gallium nitride, cadmium selenide, and zinc selenide.

   Dopants including, but not limited to, zinc, cadmium, or magnesium can be used to form p-type semiconductors in this set of embodiments, and dopants including, but not limited to, tellurium, sulfur, selenium, or germanium can be used as dopants to form n-type semiconductors from these materials. These materials define direct band gap semiconductor materials and these and doped silicon are well known to those of ordinary skill in the art. The present invention contemplates use of any doped silicon or direct band gap semiconductor materials for a variety of uses.
As used herein, a "width" of an article is a distance of a straight line from a point on a perimeter of the article through the center of the article to another point on the perimeter of the article.

   As used herein, a "width" or "cross-sectional dimension" at a point along the longitudinal axis of an elongated article is a distance along a straight line that passes through the center of the cross-section at the point and that connects two points on the perimeter of the cross section. As used herein, an "elongated" article (e.g., semiconductor or section thereof) is an article for which, at any point along the longitudinal axis of the article, a ratio of the length of the article to the largest width at the point is greater than 2:

   1.
As used herein, the "longitudinal axis" of an elongated article is an axis along a largest dimension of the article.
As used herein, the "length" of an elongated article is a distance along the longitudinal axis from end to end of the article.
As used herein, a "longitudinal section" of an elongated article is a portion of the elongated article along the longitudinal axis of the elongated article than can have any length greater than zero and less than or equal to the length of the article.
As used herein, a "cross-section" at a point along the longitudinal axis of an elongated article is a plane at the point across the elongated article that is orthogonal to the longitudinal axis of the article.
As used herein, a "cylindrical" article is an article having an exterior shaped like a cylinder, but does not define or reflect any properties regarding the interior of the article.

   In other words, a cylindrical article may have a solid interior or may have ahollowed-out interior.
As used herein, a "nanowhe" or "NW" is an elongated semiconductor, i.e., a nanoscale semiconductor, that at any point along its length has at least one cross-sectional dimension and, in some embodiments, two orthogonal cross-sectional dimensions less than 500 nanometers, preferably less than 200 nanometers, more preferably less than 150 nanometers, still more preferably less than 100 nanometers, even more preferably less than 70, still more preferably less than 50 nanometers, even more preferably less than 20 nanometers, still more preferably less than 10 nanometers, and even less than 5 nanometers. The cross-section of the elongated semiconductor may have any arbitrary shape, including, but not limited to, circular, square, rectangular, elliptical.

   Regular and irregular shapes are included.
As used herein, a "nanotube" or "NT" is a nanowire that has a hollowed-out core. As used herein, a "bulk-doped" article (e.g. semiconductor or section thereof) is an article for which a dopant is incorporated substantially throughout the crystalline lattice of the article, as opposed to an article in which a dopant is only incorporated in particular regions. For example, some articles such as carbon NTs typically are doped after the base material is grown, and thus the dopant only extends a finite distance from the surface or exterior of the carbon NT into the interior of the crystal line lattice. Further, carbon NTs are often combined as nested tubes forming alternating layers of base material and doped base material such that the dopant is not hicorporated throughout the crystal line lattice of the base material.

   As used herein to describe a "nanowire" or "NW", "doped" means bulk-doped.
Accordingly, as used herein, a "doped nanowire" or "doped NW" is a bulk-doped nanowhe
As used herein, an "array" of articles (e.g., nanowires) comprises a plurality of the articles. As used herein, a "crossed array" is an array where at least one of the articles contacts either another of the articles or a signal node (e.g., an electrode).
As used herein, a first article (e.g., a nanowire or larger-sized structure) "coupled" to a second article is disposed such that the first article either physically contacts the second article or is proximate enough to the second article to influence a property (e.g., electrical property, optical property, magnetic property) of the second article.

   Thus, the present invention contemplates, in one aspect, an elongated semiconductor that has a smallest width of less than 500 nanometers that is doped in any way (n-type or p-type). In other embodiments, the semiconductor may have a smallest width less than about 200 nanometers, less than about 150 nanometers, or less than about 100 nanometers. Preferably, the semiconductor has a smallest width of less than about 80 nanometers, more preferably less than about 70 nanometers, preferably less than about 50 nanometers. Smaller widths, such as those with at least one dimension of less than about 20 nanometers, less than about 10 nanometers, or less than about 5 nanometers also are included. In some embodiments, two orthogonal cross-sectional dimensions of the elongated semiconductor may be less than the values given above.

   The aspect ratio, i.e., the ratio of semiconductor length to largest width, is greater than 2:1. In other embodiments, the aspect ratio may be greater than 4:1, greater than 10:1, greater than 100:1 or even greater than 1000:1. Semiconductors such as these, at very small dimensions, find a variety of uses as described below.
Fig. 1 is a perspective diagram illustrating an example of a cylindrical semiconductor LI , for example, a wire-like semiconductor such as a nanowire. The cylindrical semiconductor LI has a length L2 and a longitudinal axis L3. At a point L5 along the longitudinal axis L3, the cylindrical semiconductor LI has a plurality of widths L4 across cross-section L6, where one of the widths L4 is a smallest width at the point L5. Such semiconductors may be free-standing.

   As used herein, a "free-standing" article is an article that at some point in its life is not attached to another article or that is in solution.
Further, such a semiconductor may be a bulk-doped semiconductor. As used herein, a "bulk-doped semiconductor" article (e.g. article or section of an article) is a semiconductor for which a dopant is incorporated substantially throughout the crystalline lattice of the semiconductor, as opposed to a semiconductor in which a dopant is only incorporated in particular regions. For example, some semiconductors such as NTs typically are doped after the semiconductor is grown, and thus the dopant only extends a finite distance from the surface or exterior of the nanotube into the interior of the crystalline lattice.

   Further, NTs are often combined as nested tubes (i.e. cylinders) forming alternating layers of semiconductor and doped semiconductor such that the dopant is not incorporated throughout the crystalline lattice of the semiconductor. It should be understood that "bulk-doped" does not define or reflect a concentration or amount of doping in a semiconductor, nor does it indicate that the doping is necessarily uniform.
For a doped semiconductor, the semiconductor may be doped during growth of the semiconductor. Doping the semiconductor during growth may result in the property that the doped semiconductor is bulk-doped.

   Further, such doped semiconductors may be controllably doped, such that a concentration of a dopant within the doped semiconductor can be controlled and therefore reproduced consistently, making possible the commercial production of such semiconductors.
A variety of devices may be fabricated using semiconductors such as those described above. Such devices include electrical devices, optical devices, mechanical devices or any combination thereof, including opto-electronic devices and electromechanical devices.
In an embodiment a field effect transistor (FET) is produced using a doped semiconductor having a smallest width of less than 500 nanometers or other width described above. The doped semiconductor can be either a p-type or n-type semiconductor, as is known by those of ordinary skill in the art in FET fabrication.

   While FETs are known using nanotubes, to the inventors' knowledge, prior arrangements select nanotubes at random, without control over whether the nanotube is metallic or semiconducting. In such a case a very low percentage of devices are functional, perhaps less than one in twenty, or one in fifty, or perhaps approximately one i one hundred. The present invention contemplates controlled doping of nanowires such that a fabrication process can involve fabricating functional FETs according to a technique in which much greater than one in fifty devices is functional. For example, the technique can involve doping a nanowire, then fabricating an FET therefrom.

   The invention also provides lightly-doped complementary inverters
(complementary metal oxide semiconductors) arranged simply by contact of an n-type semiconductor with a p-type semiconductor, for example by arrangement of crossed ntype and p-type semiconducting nanowires as shown below.
Also provided in accordance with the invention are tunnel diodes with heavilydoped semiconducting components.

   A tunnel diode can be arranged similarly or exactly the same as a complementary inverter, with the semiconductors being heavily doped rather than lightly doped. "Heavily doped" and "lightly doped" are terms the meaning of which is clearly understood by those of ordinary skill in the art.
One important aspect of the present invention is the ability to fabricate essentially any electronic device that can benefit from adjacent n-type and p-type semiconducting components, where the components are pre-fabricated (doped, in individual and separate processes with components separate from each other when doped) and then brought into contact after doping.

   This is in contrast to typical prior art arrangements in which a single semiconductor is n-doped in one region and p-doped in an adjacent region, but the n-type semiconductor region and p-type semiconducting regions are initially adjacent prior to doping and do not move relative to each other prior to or after doping. That is, n-type and p-type semiconductors, initially in non-contacting arrangement, are brought into contact with each other to form a useful electronic device. Essentially any device can be made in accordance with this aspect of the invention that one of ordinary skill in the art would desirably make using n-type and p-type semiconductors in combination.

   Examples of such devices include, but are not limited to, field effect transistors (FETs), bipolar junction transistors (BJTs), tunnel diodes, complementary inverters, light emitting devices, light sensing devices, gates, inverters, AND, NAND, OR, and NOR gates, latches, flip-flops, registers, switches, clock circuitry, static or dynamic memory devices and arrays, state machines, gate arrays, and any other dynamic or sequential logic or other digital devices including programmable circuits. Also included are analog devices and chcuitry, including but not limited to, amplifiers, switches and other analog chcuitry using active transistor devices, as well as mixed signal devices and signal processing circuitry. Electronic devices incorporating semiconductor nanowires can be controlled, for example, by electrical, optical or magnetic signals.

   The control may involve switching between two or more discrete states or may involve continuous control of nanowire current, i.e., analog control. In addition to electrical signals, optical signals and magnetic signals, the devices may be controlled as follows:
(1) The device is switchable in response to biological and chemical species, for example, DNA, protein, metal ions. In more general sense, these species are charged or have dipole.
(2) The device is switchable in response to the mechanical stretching, vibration and bending.
(3) The device is switchable in response to the temperature.
(4) The device is switchable in response to the environmental pressure.
(5) The device is switchable in response to the movement of environmental gas or liquid.

   Many devices of the invention make particular use of crossed p/n junctions which can be junctions of crossed n-type and p-type nanowires. Crossed p/n junctions are defined by at least one n-type semiconductor and at least one p-type semiconductor, at least one portion of each material contacting at least one portion of the other material, and each semiconductor including portions that do not contact the other component. They can be arranged by pre-doping the nanowires, then bringing them into proximity with each other using techniques described below.
Light-emission sources are provided in accordance with the invention as well, in which electrons and holes combine, emitting light. One type of light-emission source of the invention includes at least one crossed p/n junction, in particular, crossed p-type and ntype nanowhes.

   In this and other arrangements of the invention using crossed nanowires, the wires need not be perpendicular, but can be. When forward biased (positive charge applied to the p-type wire and a negative charge applied to the n-type wire) electrons flow toward the junction in the n-type wire and holes flow toward the junction in the p-type wire. At the junction, holes and electrons combine, emitting light. Other techniques may be used to cause one or more nanowires, or other semiconductors to emit light, as described below in more detail.
At the size scale of the invention (nanoscale) the wavelength of light emission can be controlled by controlling the size of at least one, and preferably both components that are crossed to form the light-emitting junction.

   For example, where nanowires are used, a nanowire with larger smallest dimension (broader wire) will provide emission at a lower frequency. For example, in the case of indium phosphide, at size scales associated with typical fabrication processes, the material emits at 920 nanometers. At the size scales of the present invention the wavelength of emission can be controlled to be at wavelengths shorter than 920 nanometers, for example between 920 and 580 nanometers.

   Wavelengths can be selected within this range, such as 900, 850, 800, 750, 700 nanometers, etc., depending upon wire size.
Thus, one aspect of the invention involves a semiconductor light-emission source that emits at a higher frequency than the semiconductor causing emission emits in its bulk state such increase of the frequency of emission of light is often referred to herein as quantum confinement. "Bulk state", in this context, means a state in which it is present as a component, or a portion of a component having a smallest dimension of greater than 500 nanometers. "Bulk state" also can be defined as that state causing a material's inherent wavelength or frequency of emission.

   The present invention provides for such control over emission frequency of essentially any semiconducting or doped semiconducting material.
Assembly, or controlled placement of nanowires on surfaces can be carried out by aligning nanowires using an electrical field. An electrical field is generated between electrodes, nanowires are positioned between the electrodes (optionally flowed into a region between the electrodes in a suspending fluid), and will align in the electrical field and thereby can be made to span the distance between and contact each of the electrodes. In another arrangement individual contact points are arranged in opposing relation to each other, the individual contact points being tapered to form a point directed towards each other.

   An electric field generated between such points will attract a shigle nanowire spanning the distance between, and contacting each of, the electrodes. In this way individual nanowires can readily be assembled between individual pahs of electrical contacts. Crossed-wire arrangements, including multiple crossings (multiple parallel wires in a first direction crossed by multiple parallel wires in a perpendicular or approximately perpendicular second dhection) can readily be formed by first positioning contact points (electrodes) at locations where opposite ends of the crossed wires desirably will lie. Electrodes, or contact points, can be fabricated via typical microfabrication techniques.

   These assembly techniques can be substituted by, or complemented with, a positioning arrangement involving positioning a fluid flow directing apparatus to direct fluid containing suspended nanowhes toward and in the dhection of alignment with locations at which nanowires are desirably positioned. A nanowire solution can be prepared as follows. After nanowires are synthesized, they are transferred into a solvent (e.g., ethanol), and then are sonicated for several seconds to several minutes to obtain a stable suspension.
Another arrangement involves forming surfaces including regions that selectively attract nanowires surrounded by regions that do not selectively attract them. For example, -NH2can be presented in a particular pattern at a surface, and that pattern will attract nanowires or nanotubes having surface functionality attractive to amines.

   Surfaces can be patterned using known techniques such as electron-beam patterning, "soft-lithography" such as that described in International Patent Publication No. WO 96/29629, published July 26, 1996, or U.S. Patent No. 5, 512,131, issued April 30, 1996, each of which is incorporated herein by reference. Additional techniques are described in U.S. Patent
Application Serial No. 60/142,216, filed July 2, 1999, by Lieber, et al., incorporated herein by reference. Fluid flow channels can be created at a size scale advantageous for placement of nanowhes on surfaces using a variety of techniques such as those described in International Patent Publication No. WO 97/33737, published September 18, 1997, and incorporated herein by reference. Other techniques include those described in U.S.

   Patent Application Serial No. 09/578,589, filed May 25, 2000, and incorporated herein by reference.
Figs. 7A-7E show one such technique for creating a fluid flow channel using a polydimethyl siloxane (PDMS) mold. Channels can be created and applied to a surface, and a mold can be removed and re-applied in a different orientation to provide a cross flow arrangement or different arrangement.
The flow channel arrangement can include channels having a smallest width of less than 1 millimeter, preferably less than 0.5 millimeter, 200 microns or less. Such channels are easily made by fabricating a master by using photolithography and casting PDMS on the master, as described in the above-referenced patent applications and international publications. Larger-scale assembly is possible as well.

   The area that can be patterned with nanowire arrays is defined only by the feature of the channel which can be as large as desired. Semiconductor nanowires have a crystalline core sheathed with 1-10 nm thick of amorphous oxide. This allows surface modification to terminate the surface with various functional groups. For example, we can use molecules, one end of which is alkyloxysilane group (e.g. -Si(OCH3)) reacting with nanowire surface, the other end of which comprise (1) -CH3, -COOH,- NH2, -SH, -OH, hydrazide, and aldehyde groups. (2) light activatable moieties: aryl azide, fluorinated aryl azide, benzophenone etc. . The substrate and electrodes are also modified with certain functional groups to allow nanowhes to specifically bind or not bind onto the substrate/electrodes surface based on the their interaction.

   Surface-functionalized nanowires can also be coupled to the substrate surface with functional cross-linkers, e.g. (1) Homobifunctional cross-linkers, comprising homobifunctional NHS esters, homobifunctional imidoesters, homobifunctional sulfhydryl-reactive linkers, difluorobenzene derivatives, homobifunctional photoactive linkers, homobifunctional aldehyde, bis-epoxides, homobifunctional hydarzide etc. (2) Heterobifuntional cross-linkers (3)Trifuntional cross-linkers
The assembly of nanowires onto substrate and electrodes can also be assisted using bimolecular recognition. For example, we can immobilize one biological binding partner onto the nanowire surface and the other one onto substrate or electrodes using physical adsorption or covalently linking.

   Some good bio-recognitions are: DNA hybridization, antibody-antigen binding, biotin-avidin (or streptavidin) binding.
There are many techniques that may be used to grow bulk-doped semiconductors, such as nanowhes, and for doping such nanowhes during growth.
For example, SiNWs (elongated nanoscale semiconductors) may be synthesized using laser assisted catalytic growth (LCG). As shown in Figs. 2 and 3, laser vaporization of a composite target that is composed of a desired material (e.g. InP) and a catalytic material (e.g. Au) creates a hot, dense vapor which quickly condenses into liquid nanoclusters through collision with the buffer gas. Growth begins when the liquid nanoclusters become supersaturated with the desired phase and continues as long as the reactant is available.

   Growth terminates when the nanowires pass out of the hot reaction zone or when the temperature is turned down. Au is generally used as catalyst for growing a wide range of elongated nanoscale semiconductors. However, The catalyst is not limited to Au only. A wide rage of materials such as (Ag, Cu, Zn, Cd, Fe, Ni, Co...) can be used as the catalyst. Generally, any metal that can form an alloy with the desired semiconductor material, but doesn't form more stable compound than with the elements of the desired semiconductor can be used as the catalyst. The buffer gas can be Ar, N2, and others inert gases. Sometimes, a mixture of H2 and buffer gas is used to avoid un-desired oxidation by residue oxygen.

   Reactive gas can also be introduced when desired (e.g. ammonia for GaN).The key point of this process is laser ablation generates liquid nanoclusters that subsequently define the size and direct the growth direction of the crystalline nanowires. The diameters of the resulting nanowires are determined by the size of the catalyst cluster, which in turn can be varied by controlling the growth conditions (e.g. background pressure, temperature, flow rate...). For example, lower pressure generally produces nanowhes with smaller diameters.

   Further diameter control can be done by using uniform diameter catalytic clusters.
With same basic principle as LCG, if uniform diameter nanoclusters (less than 1020% variation depending on how uniform the nanoclusters are) are used as the catalytic cluster, nanowires with uniform size (diameter) distribution can be produced, where the diameter of the nanowires is determined by the size of the catalytic clusters, as illustrated in Fig. 4. By controlling the growth time, nanowires with different lengths can be grown.
With LCG, nanowhes can be flexibly doped by introducing one or more dopants into the composite target (e.g. (Ge for n-type doping of InP).

   The doping concentration can be controlled by controlling the relative amount of doping element, typically 0-20%, introduced in the composite target.
Laser ablation may be used as the way to generate the catalytic clusters and vapor phase reactant for growth of nanowhes and other related elongated nanoscale structures, but fabrication is not limited to laser ablation, many ways can be used to generate vapor phase and catalytic clusters for nanowhe growth (e.g. thermal evaporation). Another technique that may be used to grow nanowires is catalytic chemical vapor deposition (C-CVD).

   C-CVD utilizes the same basic principles as LCG, except that in the C-CVD method, the reactant molecules (e.g., silane and the dopant) are from vapor phase molecules (as opposed to vapor source from laser vaporization.
In C-CVD, nanowhes can be doped by introducing the doping element into the vapor phase reactant (e.g. diborane and phosphane for p-type and n-type doped nanowire). The doping concentration can be controlled by controlling the relative amount of the doping element introduced in the composite target. It is not necessary to obtain elongated nanoscale semiconductors with the same doping ratio as that in the gas reactant. However, by controlling the growth conditions (e.g. temperature, pressure....), nanowires with same doping concentration can be reproduced.

   And the doping concentration can be varied over a large range by simply varying the ratio of gas reactant (e.g. lppm-10%).
There are several other techniques that may be used to grow elongated nanoscale semiconductors such as nanowhes. For example, nanowhes of any of a variety of materials can be grown directly from vapor phase through a vapor-solid process. Also, nanowires can also be produced by deposition on the edge of surface steps, or other types of patterned surfaces, as shown in Fig. 5. Further, nanowhes can be grown by vapor deposition in/on any general elongated template, for example, as shown in Fig. 6. The porous membrane can be porous silicon, anodic alumina or diblock copolymer and any other similar structure. The natural fiber can be DNA molecules, protein molecules carbon nanotubes, any other elongated structures.

   For all the above described techniques, the source materials can be came from a solution phase rather than a vapor phase. While in solution phase, the template can also be column micelles formed by surfactant molecules in addition to the templates described above.
Using one or more of the above techniques, elongated nanoscale semiconductors, including semiconductor nanowhes and doped semiconductor nanowires, can be grown. Such bulk-doped semiconductors may include various combinations of materials, including semiconductors and dopants. The following are non-comprehensive lists of such materials. Other materials may be used.

   Such materials include, but are not limited to: Elemental semiconductors:
Si, Ge, Sn, Se, Te, B, Diamond, P Solid solution of Elemental semiconductors: B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn
IV-IV group semiconductors:
SiC III- V semiconductors:
BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, Alloys oflll-V Group: any combination of two or more of the above compound (e.g.: AlGaN, GaPAs, InPAs, GalnN, AlGalnN, GalnAsP...) II- VI semiconductors: ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe MgS/MgSe
Alloys ofll-VI Group: any combination of two or more of the above compound (e.g.: (ZnCd)Se, Zn(SSe)...) Alloy ofll-VI and III- V semiconductors: combination of any one II-VI and one III-V compounds, eg.(GaAs)x(ZnS)1-xIV-VI semiconductors:
GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe J- VII semiconductors:

   CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl
Other semiconductor compounds
I[Iota]-rV-V2: BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2 ... I-IV2-V3: CuGeP3, CuSi2P3.. I-[pi]i-VI2: Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te)2 IV3-V4: Si3N4, Ge3N4 ...
III2-Vl3: A12O3, (Al, Ga, In)2(S, Se, Te)3... III2-IV-VI: A12CO ...
For Group IV semiconductor materials, a p-type dopant may be selected from Group ni, and an n-type dopant may be selected from Group V. For silicon semiconductor materials, a p-type dopant may be selected from the group consisting of B, Al and In, and an n-type dopant may be selected from the group consisting of P, As and Sb. For Group III-V semiconductor materials, a p-type dopant may be selected from Group II, including Mg, Zn, Cd and Hg, or Group IV, including C and Si. An n-type dopant may be selected from the group consisting of Si, Ge, Sn, S, Se and Te.

   It will be understood that the invention is not limited to these dopants. Examples Doping and Electrical Transport in Nanowires
Single crystal n-type and p-type silicon nanowires (SiNWs) have been prepared and characterized by electrical transport measurements. As used herein, a "shigle crystal" item is an item that has covalent bonding, ionic bonding, or a combination thereof throughout the item. Such a single crystal item may include defects in the crystal, but is distinguished from an item that includes one or more crystals, not ionically or covalently bonded, but merely in close proximity to one another. Laser catalytic growth was used to introduce controllably either boron or phosphorous dopants during the vapor phase growth of SiNWs.

   Two terminal, gate-dependent measurements made on individual boron-doped and phosphorous-doped SiNWs show that these materials behave as p-type and n-type materials, respectively. Estimates of the carrier mobility made from gate-dependent transport measurements are consistent with diffusive transport. In addition, these studies show it is possible to heavily dope SiNWs and approach a metallic regime. Temperaturedependent measurements made on heavily doped SiNWs show no evidence for coulomb blockade at temperature down to 4.2 K, and thus testify to the structural and electronic uniformity of the SiNWs. Potential applications of the doped SiNWs are discussed.

   Currently, there is intense interest in one dimensional (ID) nanostructures, such as. nanowires and nanotubes, due to their potential to test fundamental concepts about how dimensionality and size affect physical properties, and to serve as critical building blocks for emerging nanotechnologies. Of particular importance to ID nanostructures is the electrical transport through these "wires", since predictable and controllable conductance will be critical to many nanoscale electronics applications. To date, most efforts have focused on electrical transport in carbon nanotubes. These studies have shown interesting fundamental features, including the existence of coherent states extending over hundreds of nanometers, ballistic conduction at room temperature, and Luttinger liquid behavior, and have demonstrated the potential for devices such as field effect transistors.

   However, there are important limitations of nanotubes. First, the specific growth of metallic or semiconducting tubes, which depends sensitively on diameter and helicity, is not possible. Studies dependent on the specific conducting behavior must thus rely on chance observation. Second, controlled doping of semiconducting nanotubes is not possible, although it is potentially critical for devices applications. Semiconductor nanowires, however, can overcome these limitations of carbon nanotubes. These nanowires will remain semiconducting independent of diameter, and moreover, it should be possible to take advantage of the vast knowledge from the semiconductor industry to dope the nanowires.
To this end, we here report the first demonstration of controlled doping of SiNWs and the characterization of the electrical properties of these doped nanowires using transport measurements.

   Gate-dependent, two terminal measurements demonstrate that boron-doped (B-doped) and phosphorous-doped (P-doped) SiNWs behave as p-type and n-type materials, respectively, and estimates of the carrier mobilities suggest diffusive transport in these nanowires. In addition, temperature dependent measurements made on heavily doped SiNWs show no evidence for coulomb blockade at temperatures down to 4.2 K.
SiNWs were synthesized using the laser-assisted catalytic growth (LCG) we have described previously. Briefly, aNd-YAG laser (532 nm; 8 ns pulse width, 300 mJ/pulse, 10 Hz) may be used to ablate a gold target, which produces gold nanocluster catalyst particles within a reactor. The SiNWs may be grown in a flow of S1H4as the reactant.

   Such SiNWs may be doped with boron by incorporating B2H in the reactant flow, and may be doped with phosphorous using a Au-P target (99.5:0.5 wt%, Alfa Aesar) and additional red phosphorous (99%, Alfa Aesar) at the reactant gas inlet. Transmission electron microscopy (TEM) measurements demonstrate that doped SiNWs grown using this technique have a single crystal silicon core that is covered by a dense SiOxsheath as described previously.
Electrical contact to individual SiNWs were made using standard electron beam lithography methods using a JEOL 6400 writer. The nanowhes were supported on oxidized Si substrate (1-10 [Omega]cm resistivity, 600 nm SiO2, Silicon Sense, Inc.) with the underlying conducting Si used as a back gate. The contacts to the SiNWs were made using thermally evaporated Al (50 nm) and Au (150 nm).

   Electrical transport measurements were made using a homebuilt system with less than or equal to 1 pA noise under computer control. The temperature-dependent measurements were made in a Quantum Design magnetic property measurement system.
TEM studies show that the boron and phosphorous-doped SiNWs are single crystals, although these measurements do not have sufficient sensitivity to quantify the boron or phosphorous doping level in individual wires. We can, however, demonstrate unambiguously the presence of p-type (boron) or n-type (phosphorous) dopants and the relative doping levels using electrical transport spectroscopy. In these measurements, a gate electrode is used to vary the electrostatic potential of the SiNW while measuring current versus voltage of the nanowhe.

   The change in conductance of SiNWs as function of gate voltage can be used to distinguish whether a given nanowire is p-type or n-type since the conductance will vary oppositely for increasing positive (negative) gate voltages. Typical gate-dependent current versus bias voltage (I-V) curves recorded on intrinsic and B-doped SiNWs are shown in Figs. 8A-8C. The two B-doped wires shown in Figs. 8B and 8C were synthesized using S1H4 : B2H6ratios of 1000 : 1 and 2 : 1, respectively. In general, the two terminal I-V curves are linear and thus suggest that the metal electrodes make ohmic contacts to the SiNWs. The small nonlinearity observed in the intrinsic nanowire indicates that this contact is slightly nonohmic.

   Analysis of I-V data, recorded at zero gate voltage (Vg= 0), which accounts for contributions from the contact resistance and oxide coating on the SiNW, yield a resistivity of 3.9 x 10<2>[Omega]cm. Significantly, when Vgis made increasingly negative (positive), the conductance increases (decreases). This gate dependence shows that the SiNW is a p-doped semiconductor (discussion below). Similar I-V versus Vgcurves were recorded for the lightly B-doped SiNW, and show that it is also p-type. Moreover, the Vg= 0 resistivity of this B-doped SiNW (1 [Omega]-cm) is more than two orders of magnitude smaller than the intrinsic SiNW, and demonstrates clearly our ability to control conductivity chemically. This latter point is further supported by I-V measurements on the heavily B-doped SiNWs show in Fig. 8C.

   This wire has a very low resistivity of 6.9 xlO<"3>[Omega]-cm and shows no dependence on Vg; that is, J.-V data recorded with Vgof 0 and 20 V are overlapping. These results are consistent with a high carrier concentration that is near the metallic limit.
We have also measured Vg-dependent transport in lightly and heavily P-doped SiNWs. The I-V recorded on the lightly doped nanowire (Fig. 9A) is somewhat nonlinear, which indicates nonideal contact between the electrodes and nanowire, and the Vgdependence is opposite of that observed for the B-doped SiNWs. Significantly, this observed gate dependence is consistent with n-type material as expected for P-doping. The estimated resistivity of this wire at Vg= 0 is 2.6 xlO<2>[Omega]-cm. This relatively high resistivity is suggestive of a low doping level and/or low mobility.

   In addition, heavily Pdoped SiNWs have also been made and studied. The I-V data recorded on a typical heavily P-doped wire are linear, have a resistivity of 2.3 xlO<">[Omega]-cm, and shows no dependence on Vg. The low resistivity (four orders of magnitude smaller than the lightly P-doped sample) and Vgindependence demonstrate that high carrier concentrations can also be created via P-doping of the SiNWs.
The above results demonstrate that boron and phosphorous can be used to change the conductivity of SiNWs over many orders of magnitude and that the conductivity of the doped SiNWs respond oppositely to positive (negative) Vgfor boron and phosphorous dopants. Indeed, the Vg-dependence provides strong proof for p-type (holes) doping with boron and n-type (electrons) doping with phosphorous in the SiNWs.

   The observed gate dependencies can be understood by referring to the schematics shown in Figs. 10A and 10B, which show the effect of the electrostatic potential on the SiNW bands. In these diagrams, a p-type nanowire (a) and n-type nanowire (b) are contacted at both ends to metal electrodes. As for a conventional metal-semiconductor interface, the SiNW bands bend (up for p-type; down for n-type) to bring the nanowire Fermi level in line with that of the metal contacts. When Vg> 0, the bands are lowered, which depletes the holes in Bdoped SiNWs and suppress conductivity, but leads to an accumulation of electrons in Pdoped SiNWs and enhance the conductivity. Conversely, Vg< 0 will raise the bands and increase the conductivity of B-doped (p-type) SiNWs and decrease the conductivity of the P-doped (n-type) nanowires.

   In addition, it is possible to estimate the mobility of carriers from the transconductance, dI/dVg= [mu]C/L<2>) V, where [mu] is the carrier mobility, C is the capacitance, and L is the length of the SiNW. The SiNW capacitance is given by C¯2[pi][epsilon][epsilon]0L/ln(2h/r), where [epsilon] is the dielectric constant, h is the thickness of the silicon oxide layer, and r is the SiNW radius. Plots of dI/dV[epsilon]versus V were found to be linear for the intrinsic (Fig. 8 A) and lightly B-doped (Fig. 8B) SiNWs, as expected for this model. The slopes of dI/dVgfor the intrinsic (2.13 x 10<1>) and B-doped (9.54 xlO<"9>) SiNW yield mobilities of 5.9xl0<3>cm<2>/V-s and 3.17 cm<2>/V-s, respectively. The mobility for the B-doped nanowire is comparable to that expected in bulk Si at a doping concentration of 10<20>cm<"3>.

   We also note that the mobility is expected to increase with decreasing dopant concentration, although in our intrinsic (low dopant concentration) SiNW the mobility is extremely low. It is possible that the reduced mobility is due to enhanced scattering in the smaller diameter (intrinsic) SiNW. We believe that future studies of the mobility as a function of diameter (for constant dopant concentration) should illuminate this important point.
Lastly, we have carried out preliminary temperature-dependent studies of heavily B-doped SiNWs. Temperature dependent I-V curves show that the conductance decreases with decreasing temperature, as expected for a doped semiconductor (Figs. 11 A and 1 IB).

   More importantly, we see no evidence for a coulomb blockade down to our lowest accessible temperature (Fig. 1 IB), he small nonlinearity near V = 0 is attributed to a contact effect since high resolution I-V versus Vgmeasurements show no signature for coulomb blockade. Coulomb charging effect in this homogenous wire between the electrodes (a 150 nm thick 2.3 [mu]m long wire) would require a temperature below about 26 mK estimated from kT - e<2>/2C. This indicates strongly that variations in SiNW diameter and defects are sufficiently small that they do not effectively "break up" the SiNW into small islands, which would exhibit coulomb blockade at these temperatures.

   These results contrast studies of lithographically pattered SiNWs, which show coulomb blockade, and testify to the high quality of our free standing nanowires.
Shigle crystal n-type and p-type silicon nanowires (SiNWs) have been prepared and characterized by electrical transport measurements. Laser catalytic growth was used to introduce controllably either boron or phosphorous dopants during the vapor phase growth of SiNWs. Two-terminal, gate-dependent measurements made on individual boron-doped and phosphorous-doped SiNWs show that these materials behave as p-type and n-type materials, respectively. Estimates of the carrier mobility made from gatedependent transport measurements are consistent with diffusive transport, and show an indication for reduced mobility in smaller diameter wires.

   In addition, these studies show it is possible to incorporate high dopant concentrations in the SiNWs and approach the metallic regime. Temperature-dependent measurements made on heavily doped SiNWs show no evidence for single electron charging at temperatures down to 4.2 K, and thus suggest that the SiNWs possess a high degree of structural and doping uniformity. We believe that our successful doping of SiNWs to create n-type and p-type materials will open up exciting opportunities in nanoscale science and technology. Doped SiNWs will be candidates for investigating fundamental issues of transport in ID nanostructures. The structures studies in this paper are also field effect transistors (FETs), and it will be possible using self-assembly techniques to integrate many SiNW FETs into structures perhaps for nanoelectronics applications.

   It should also be possible to combine p-type and n-type SiNWs, for example in crossed arrays, to create p-n junctions that could also be considered for devices and sensors in the future.
Crossed SiNW p-n junctions have been formed by directed assembly of p-type (ntype) SiNWs over n-type (p-type) SiNWs. Transport measurements exhibit rectification in reverse bias and a sharp current onset in forward bias. Simultaneous measurements made on the p-type and n-type SiNWs making up the junction demonstrate that the contacts to these nanowires are ohmic (nonrectifying), and thus that the rectifying behavior is due to the p-n junction between the two SiNWs. Fig. 8A shows current (I) vs bias voltage (V) curves recorded on a 70 nm diameter intrinsic SiNW at different gate voltages (Vg). Curves 1, 2, 3, 4, 5, 6, and 7 correspond to Vg= -30, -20, -10, 0V, 10, 20, and 30 V, respectively.

   The inset is atypical scanning electron micrograph of the SiNW with metal contacts (scale bar = lOum). Fig. 8B shows I-V data recorded on a 150 nm diameter B-doped SiNW; curves 1-8 correspond to Vg= 20, -10, -5, 0, 5, 10, 15 and 20 V, respectively. Fig. 8C shows I-V curves recorded on a 150 nm diameter heavily B-doped SiNW; Vg= 20 V (solid line) and 0 V (heavy dashed line). Fig. 9 A shows I-V data recorded on a 60 nm diameter P-doped SiNW. Curves 1, 2,
3, 4, 5, and 6 correspond to Vg= 20, 5, 1, 0, -20, and -30 V, respectively. Fig. 9B shows I-V curves recorded on a 90 nm diameter heavily P-doped SiNW; Vg= 0 V (solid line) and -20 V (heavy dash line).
Fig. 10A shows energy band diagrams for p-type SiNW devices. Fig. 10B shows energy band diagrams for n-type SiNW devices.

   The diagrams show schematically the effect of Vgon the electrostatic potential for both types of nanowhes.
Figs. 11 A and 1 IB show temperature dependent I-V curves recorded on a heavily B-doped SiNW. In Fig. 11 A, curves 1, 2, 3, 4, 5, and 6 correspond to temperatures of 295, 250, 200, 150, 100, and 50 K, respectively. Fig. 1 IB shows I-V data recorded on the nanowire at 4.2 K.
Diameter Selective Synthesis of Semiconductor Nanowires
Nearly monodisperse samples of single crystalline GaP nanowires have been synthesized with diameters of 10, 20, and 30 nm and lengths greater than 10 [mu]m by exploiting well-defined gold colloids as catalysts in our laser catalytic growth (LCG) process. In this method, the Ga and P reactants generated by laser ablation of solid GaP are subsequently directed into a nanowire structure by gold nanocluster catalysts.

   Transmission electron microscopy (TEM) studies of nanowires prepared in this way demonstrate that the distributions of nanowire diameters are defined by those of the nanocluster catalysts. High-resolution TEM shows that the wires are single crystal zinc blend with a [111] growth direction, and energy dispersive X-ray analysis confirms that the nanowhe composition is stoichiometric GaP.

   The use of monodisperse nanocluster catalysts combined with the LCG method will enable the growth of a wide range of semiconductor nanowires with well-defined and controlled diameters, and thus opens up opportunities from fundamental properties of one-dimensional (ID) systems to the assembly of functional nanodevices.
Nearly monodisperse samples of single crystalline GaP nanowires have been synthesized with diameters of 10, 20, and 30 nm and lengths greater than 10 [mu]m by exploiting well-defined gold colloids as catalysts in our laser catalytic growth (LCG) synthetic methodology. Transmission electron microscopy (TEM) studies of nanowires prepared in this way demonstrate that the distributions of nanowhe diameters are defined by those of the nanocluster catalysts.

   High-resolution TEM shows that the wires are single crystal zinc blende with a [111] growth direction, and energy dispersive X-ray analysis (ED AX) confirms that the nanowire composition is stoichiornetric GaP.
Recent interest in low-dimensional semiconductor materials has been motivated by the push for miniaturization of electronic and optoelectronic devices and a need to understand the fundamentals of nanoscale chemistry and physics. In particular, onedhnensional (ID) systems are exciting from both fundamental and applied viewpoints. Fascinating physical phenomena, such as Luttinger liquid behavior, and numerous applications from interconnects to scanning probe microscopies, require high-quality, well-defined ID nanostructures.

   Experimental progress in the field of ID nanostructures has often been limited by the ability to create new materials in this size regime with controlled size, structure, and composition.
Early approaches to ID nanostructure synthesis employed thin film growth and lithographic techniques. In particular, "T-wfres" have been fabricated by growing semiconductor quantum wells via molecular beam epitaxy, followed by cleavage and overgrowth on the cleaved surface, while "V-groove" nanowires have been prepared by etching trenches on a surface and then depositing a small amount of material into the resulting grooves. One of the significant limitations of these approaches is that the nanowires are embedded in a substrate, which precludes the assembly of complex 2D and 3D nanostructures. Template approaches have also been used for growing a wide-range of nanowires.

   These methods can provide good control over the length and diameter of nanowhes, although they are limited in that polycrystallme structures are often produced. Our laboratory has made significant progress toward the development of a general synthetic approach to free-standing single-crystal semiconductor nanowhes via the LCG method. In LCG, laser ablation of a solid target is used to simultaneously generate nanoscale metal catalyst clusters and reactive semiconductor atoms that produce nanowhes via a vapor-liquid-solid growth mechanism. This method has been used to produce a wide range of group IV, III-V, and II-VI nanowires. We have suggested that the size of the catalyst nanocluster determines the size of the wire during growth, and thus one can envision creating wires with a narrow size distribution by exploiting monodisperse catalyst nanoclusters (Fig. 12).

   Here we utilize nanometer diameter gold colloids to explore this approach.
GaP nanowires were grown by LCG using 8.4, 18.5, and 28.2 nm diameter gold colloids. In these experiments the catalyst nanoclusters are supported on a SiO2substrate and laser ablation is used to generate the Ga and P reactants from a solid target of GaP.
Field emission scanning electron microscopy (FESEM) demonstrates that nanowhes with lengths exceeding 10 [mu]m (Fig. 13 A) were obtained using all three sizes of catalyst.
Examination of the nanowhe ends also shows the presence of the nanocluster catalyst
(Fig. 13 A, inset). Control experiments carried out without the Au colloids did not produce nanowires.

   The FESEM images show that the nanowhe diameter distributions are narrower than obtained in experiments without the colloid catalysts, although FESEM is not a good method for quantifying these distributions since small variations in the focal plane can produce significant changes in the observed diameter.
The growth apparatus used in these experiments is similar to that reported. Substrates were made by placing a silicon wafer with 600 nm of thermal oxide (Silicon
Sense) into a solution of 95:5 EtOH:H2[theta] with 0.4% N-[3-(Trimethoxysilyl)pro[rho]yI]ethylenediamine for 5 minutes, followed by curing at 100-110[deg.]C for 10 minutes. Solutions of Au colloids (Ted Pella) were diluted to concentrations of 10<9>-10<[pi]>particles/mL to minimize aggregation and were deposited on the substrates.

   Substrates were placed in a quartz tube at the downstream end of the furnace with a solid target of GaP placed 3-4 cm outside of the furnace at the upstream end. The chamber was evacuated to less than 100 mTorr, and then maintained at 250 Torr with an Airflow of 100 seem. The furnace was heated to 700[deg.]C and the target was ablated for 10 minutes with an ArF excimer laser ([lambda] = 193 nm, 100 mJ/pulse, 10 Hz). After cooling, the substrates were examined by FESEM (LEO 982). For TEM (JEOL 200CX and 2010) and ED AX analysis, nanowires were deposited onto copper grids after removal from the substrates by sonication in ethanol.
To obtain a quantitative measure of the nanowhe diameter distributions produced using the gold colloids, and to better characterize their structure and composition, we used TEM.

   High resolution TEM shows that the wires are single crystal (Fig. 13B), growing in the [111] direction, and ED AX confirms the composition to be stoichiornetric GaP (Ga:P 1.00:0.94), within the limits of this technique. Significantly, extensive TEM analysis of nanowhe diameters demonstrates the extremely good correlation with the colloid catalyst diameters and dispersion (Figs. 14A and 14B); that is, for wires grown from 28.2 +- 2.6, 18.5 +- 0.9, and 8.4 +- 0.9 nm colloids we observe mean diameters of 30.2 +- 2.3, 20.0 +- 1.0, and 11.4 +- 1.9 nm, respectively. The mean nanowire diameter is generally 1-2 nm larger than that of the colloids. We believe that this increase is due to alloying of the Ga and P reactants with the colloids before nucleation of the nanowire occurs.

   For the 30 mn and 20 nm wires (Figs. 14A and 14B) it is clear that the width of the nanowire distributions mirrors those of the colloid, suggesting that the monodispersity of the wires is limited only by the dispersity of the colloids. For the 10 nm diameter wires (Fig. 14C), a small broadening (1 nm) of the wire distribution can be attributed to aggregation of the colloids. The mean diameter and distribution width increased as more concentrated solutions of the colloid were dispersed onto the substrate. The fact that the distribution has peaks separated by 2.5 nm suggests that some of the wires grow from aggregates of two colloids, although additional work is required to substantiate this point.

   In all cases, the distribution of wire diameters is more than an order of magnitude narrower than those grown without the use of colloid catalyst (Fig. 14D): 43 +- 24 nm.
We believe that this work demonstrates clearly for the first time an ability to exert systematic control over the diameter of semiconductor nanowhes for a variety of colloids. Previous attempts to grow nanowires on surfaces with poorly defined catalysts resulted in nanowhes with non-uniform diameters greater than 50 nm. Other attempts to control the diameter of nanowires by varying the background carrier gas merely shifted the mean diameter of the wires slightly and yielded much broader distributions of wires than we have achieved with colloid-mediated growth.
In summary, we have demonstrated the controlled synthesis of semiconductor wires with monodisperse diameter distributions.

   These high-quality, single crystalline wires represent good candidates for both further studies of low-dimensional physics as well as for applications in various fields of nanoscale science and technology. In particular, we believe that the synthesis of controlled diameter samples will greatly facilitate the assembly of these nanoscale building blocks into complex and functional 2D and 3D nanosystems. Fig. 12 is a schematic depicting the use of monodisperse gold colloids as catalysts for the growth of well-defined GaP semiconductor nanowires.
Fig. 13 A shows a FESEM image of nanowires synthesized from 28.2 nm colloids (scale bar is 5 [mu]m). The inset is a TEM image of the end of one of these wires (scale bar is 50 nm). The high contrast feature corresponds to the colloid catalyst at the end of the wire.

   Fig. 13B shows a TEM image of another wire in this sample (scale bar is 10 nm). The [111] lattice planes are resolved, showing that wire growth occurs along this axis, in agreement with earlier work. Measurement of the inter-plane spacing gives a lattice constant of 0.54 nm (+-0.05 nm) for the wire, in agreement with the bulk value for GaP, 0.5451 nm.
Figs. 14A-14C show histograms of measured diameters for wires grown from 28.2 nm (Fig. 14A), 18.5 nm (Fig. 14B), and 8.4 nm (Fig. 14C) colloids. The solid line shows the distribution of wire. Fig. 14D shows a histogram of diameters for wires grown using the previous method without colloids, in which the laser is used to both generate the Au nanoclusters and the GaP reactants. The distribution is very broad (stan. dev. 23.9 nm) and the mean diameter (42.7 nm) greater than those synthesized using the predefined colloid catalyst.

   In all cases, the reported nanowire diameters correspond to the crystalline cores. The amorphous oxide layers on the surface of all nanowires are relatively uniform from wire to wire within the same experiment, but vary from 2-6 nm in thickness between syntheses.
General Synthesis of Compound Semiconductor Nanowires
The predictable synthesis of abroad range of ulticomponent semiconductor nanowires has been accomplished using laser-assisted catalytic growth. Nanowires of binary group III-V materials (GaAs, GaP, InAs and InP), ternary III-V materials (GaAs/P, InAs/P), binary II-VI compounds (ZnS, ZnSe, CdS, and CdSe) and binary SiGe alloys have been prepared in bulk quantities as high purity (>90%) single crystals. The nanowires have diameters varying from three to tens of nanometers, and lengths extending to tens of micrometers.

   The synthesis of this wide range of technologically important semiconductor nanowires can be extended to many other materials and opens up significant opportunities in nanoscale science and technology.
The synthesis of nanoscale materials is critical to work directed towards understanding fundamental properties of small structures, creating nanostructured materials and developing nanotechnologies. Nanowires and nanotubes have been the focus of considerable attention, because they have the potential to answer fundamental questions about one-dimensional systems and are expected to play a central role in applications ranging from molecular electronics to novel scanning microscopy probes. To explore such diverse and exciting opportunities requires nanowire materials for which the chemical composition and diameter can be varied.

   Over the past several years considerable effort has been placed on the bulk synthesis of nanowires, and while advances have been made using template, laser ablation, solution, and other methods, in no case has it been demonstrated that one approach could be exploited in a predictive manner to synthesize a wide range of nanowire materials. Here we describe the predictable synthesis of a broad range of binary and ternary III-V, II- VI and IV -IV group semiconductor nanowires using a laser-assisted catalytic growth (LCG) method.
Recently, we reported the growth of elemental Si and Ge nanowires using the LCG method, which exploits laser ablation to generate nanometer diameter catalytic clusters that define the size and direct the growth of the crystalline nanowires by a vapor-liquidsolid (VLS) mechanism.

   A key feature of the VLS growth process and our LCG method is that equilibrium phase diagrams can be used to predict catalysts and growth conditions, and thereby enable rational synthesis of new nanowire materials. Significantly, we show here that semiconductor nanowires of the III-V materials GaAs, GaP, GaAsP, InAs, InP and InAsP, the II-VI materials ZnS, ZnSe, CdS and CdSe, and [Iota]V-IV alloys of SiGe can be synthesized in high yield and purity using this approach. Compound semiconductors, such as GaAs and CdSe, are especially intriguing targets since their direct band gaps give rise to attractive optical and electrooptical properties. The nanowires have been prepared as single crystals with diameters as small as 3 nm, which places them in a regime of strong radial quantum confinement, and lengths exceeding 10 [mu]m.

   These studies demonstrate that LCG represents a very general and predictive approach for nanowire synthesis, and moreover, we believe that the broad-range of III-V, II-VI and FV-IV nanowires prepared will open up many new opportunities in nanoscale research and technology. The prediction of growth conditions for binary and more complex nanowires using the LCG method is, in principle, significantly more difficult than previous studies of elemental Si and Ge nanowires due to the complexity of ternary and higher order phase diagrams. However, this complexity can be greatly reduced by considering pseudobinary phase diagrams for the catalyst and compound semiconductor of interest. For example, the pseudobinary phase diagram of Au-GaAs shows that Au-Ga-As liquid and GaAs solid are the principle phases above 630 [deg.]C in the GaAs rich region (Fig 15).

   This implies that Au can serve as a catalyst to grow GaAs nanowires by the LCG method, if the target composition and growth temperature are set to this region of the phase diagram. Indeed, we find that LCG using (GaAs)o.9sAuo.o5targets produces samples consisting primarily of nanowires. A typical field-emission scanning electron microscopy (FE-SEM) image of material prepared at 890 [deg.]C (Fig. 16 A) shows that the product is wire-like with lengths extending to 10 [mu]m or more. Analyses of these high-resolution SEM images shows that at least 90% of the product produced by the LCG method is nanowire with only a small amount of particle material. X-ray diffraction data from bulk samples can be indexed to the zinc-blende (ZB) structure with a lattice constant consistent with bulk GaAs, and also show that the material is pure GaAs to the 1% level.

   Lastly, we note that high yields of GaAs nanowires were also obtained using Ag and Cu catalysts. These data are consistent with the fact that these metals (M = Ag, Cu) exhibit M-Ga-As liquid and GaAs solid phase in the GaAs rich regions of the psuedobinary phase diagrams, and furthermore, demonstrate the predictability of the LCG approach to nanowire growth.
The structure and composition of the GaAs nanowires have been characterized in detail using transmission electron microscopy (TEM), convergent beam electron diffraction (ED) and energy dispersive X-ray fluorescence (EDX). TEM studies show that the nanowires have diameters ranging from 3 nm to ca 30 nm. A typical diffraction contrast image of a single 20 nm diameter wire (Fig. 17 A) indicates that the wire is single crystal (uniform contrast) and uniform in diameter.

   The Ga:As composition of this wire determined by EDX, 51.4:48.6, is the same, within limits of instrument sensitivity, as the composition obtained from analysis of a GaAs crystal standard. Moreover, the ED pattern recorded perpendicular to the long axis of this nanowire (inset, Fig. 17 A) can be indexed for the <112> zone axis of the ZB GaAs structure, and thus shows that growth occurs along the [111] dhection. Extensive measurements of individual GaAs nanowires show that growth occurs along the <111> directions in all cases. This direction and the single crystal structure are further confirmed by lattice resolved TEM images (e.g., Fig. 17B) that show clearly the (111) lattice planes (spacing 0.32 +/- 0.01 nm; bulk GaAs, 0.326 nm) perpendicular to the wire axis. Lastly, the TEM studies reveal that most nanowhes terminate at one end with a nanoparticle (inset, Fig. 16A).

   EDX analysis indicates that the nanoparticles are composed mainly of Au. The presence of Au nanoparticles at the ends of the nanowires is consistent with the pseudobinary phase diagram, and represents strong evidence for a VLS growth mechanism proposed for LCG.
The successful synthesis of binary GaAs nanowires by LCG is not an isolated case but general to a broad range of binary and more complex nanowhe materials (Table-1). Toextend our synthetic approach to the broadest range of nanowires, we recognize that catalysts for LCG can be chosen in the absence of detailed phase diagrams by identifying metals in which the nanowire component elements are soluble in the liquid phase but that do not form solid compounds more stable than the desired nanowhe phase; that is, the ideal metal catalyst should be physically active but chemically stable.

   From this perspective the noble metal Au should represent a good starting point for many materials. This noble metal also has been used in the past for the VLS growth of surface supported nanowires by metal-organic chemical vapor deposition (MOCVD). The nanowires produced by MOCVD method are distinct from the materials reported in this communication in several regards, including (1) the MOCVD nanowires are produced on surfaces and not in the bulk quantities requhed for assembly, (2) the MOCVD nanowires taper significantly from the base to their ends (that is, they do not have uniform diameters), and (3) the smallest nanowire diameters, 10-15 nm, are significantly larger than the 3-5 nm diameters achieved in our work.

   Lastly, as described below, it is important to recognize that our LCG method is readily extended to many different materials (e.g., Table- 1) simply by producing solid targets of the material of interest and catalyst.
First, we have extended significantly our work on GaAs to include GaP and ternary alloys GaAs xPx. FE-SEM images of the product obtained by LCG from (GaP)o.95Au0.o5targets exhibit high purity nanowhes with lengths exceeding 10 [mu]m (Fig. 16B). Extensive TEM characterization shows that these nanowires (i) are single crystal GaP, (ii) grow along the <111> directions, and (hi) terminate in Au nanoparticles (inset, Fig. 16B) as expected for the LCG mechanism. We have further tested the limits of our LCG approach through studies of ternary GaAsP alloy nanowires.

   The synthesis of ternary III-V alloys is of particular interest for band gap engineering that is critical for electronic and optical devices. LCG of GaAsP nanowires using a GaAso.[beta] o[Lambda]target with a Au catalyst yielded nearly pure nanowhes (Fig. 16C). TEM images, ED and EDX show that these nanowires are single crystals, grow along the <111> directions, have a Ga:As:P ratio, 1.0:0.58:0.41, that is essentially the same as the starting target composition, and terminate in nanoclusters that are composed primarily of Au (inset, Fig. 16C). High-resolution TEM images recorded on nanowires with diameters of ca.10 and 6 nm (Figs. 17C and 17D) show well-ordered (111) lattice planes and no evidence for compositional modulation.

   We believe the observation that the ternary nanowire composition can be controlled by target composition is especially important, because it provides an opportunity to explore exciton energy changes due to both band-gap variations (composition) and quantum confinement (size).
Based on the above results, it is perhaps not surprising that we have also successfully used LCG to prepare III-V binary and ternary materials containing In-As-P (Table-1). We believe that a more significant point is that this synthetic approach can also be easily extended to the preparation of many other classes of nanowires, including the IIVI materials ZnS, ZnSe, CdS and CdSe (Table-1), IV-IV SiGe alloys.

   The cases of the IIVI nanowires CdS and CdSe are especially important, because a stable structural phase of these materials, wurtzite (W), is distinct from the ZB structure of the III-V materials described above and the ZB structure of ZnS and ZnSe. Significantly, we find that nanowhes of CdS and CdSe can be synthesized in high yield using the LCG approach with a Au catalyst (Fig. 18 A). TEM and ED data obtained on individual CdSe nanowires (for example, Figs. 18B and 18C) demonstrate that these materials are single crystals with a W-type structure and <110> growth direction that is clearly distinguished from the <111> direction of ZB structures. Studies of CdS nanowhes (Table-1) show somewhat more complex behavior; that is, W-type nanowires with growth along two distinct <100> and <002> directions.

   It is possible that the <002> direction assigned for a minority of CdS nanowires could correspond to the <111> dhection of a ZB structure. However, X-ray diffraction measurements made on bulk nanowire samples are consistent with the W assignment. In addition, previous studies of W-type CdS and CdSe nanoclusters showed elongation along the <002> dhection. We believe that systematic studies of nanowire structure as a function of growth temperature should help to elucidate the origin of these results for CdS, and could also provide insight into how nanowire growth dhection might be controlled. Lastly, we have used LCG to prepare nanowires of IV-IV binary Si-Ge alloys
(Table-1). Using a Au catalyst, it was possible to synthesize single crystal nanowires over the enthe Si1-xGexcomposition range.

   Unlike the case of GaAsP discussed above, the SiGe alloys do not exhibit the same compositions as the starting targets. Rather, the composition varies continuously within the growth reactor with Si rich materials produced in the hotter central region and Ge rich materials produced at the cooler end. Specifically, LCG growth from a (Si0.7oGeo.3o)o.95Au0.05 target at 1150 [deg.]C produced nanowires with a Si:Ge ratio of 95:5, 81:19, 74:26, 34:66 and 13:87 from the furnace center to end, respectively. This composition variation arises from the fact that the optimal growth temperatures of the two individual nanowire materials are quite different. Such differences can increase the difficulty in synthesizing controlled composition alloys, although our results also show that this can be exploited to prepare a range of alloy compositions in a single growth experiment.

   In conclusion, we have synthesized a wide-range of single crystal binary and ternary compound semiconductor nanowires using our LCG technique. We believe that these results demonstrate clearly the generality of this approach for rational nanowhe synthesis. The availability of these high-quality, single crystal semiconductor nanowires is expected to enable fascinating opportunities in nanometer scale science and technology. For example, these nanowires can be used to probe the confinement, dynamics and transport of excitons in ID, and can serve as optically-active building blocks for nanostructured materials.

   Moreover, by further controlling growth, we believe that our LCG approach can be used to synthesize more complex nanowire structures, including single wire homo- and heterojunctions and superlattices, and thus may enable the synthesis of nanoscale light-emitting diodes and laser devices.
The apparatus and general procedures for LCG growth of nanowhes have been described previously. The targets used in syntheses consisted of (material)o.95Au0.05. Typical conditions used for synthesis were (i) 100-500 torr Ar:H2(95:5), (ii) 50-150 sscm gas flow, and (iii) ablation with a pulsed Nd:YAG laser ([lambda]=1064 nm; 10 Hz pulse rate; 2.5 W average power). Specific temperatures used for the growth of different nanowire materials are given in Table-1.

   The nanowire products were collected at the down-stream cold end of the furnace.
The nanowire samples were characterized using X-ray diffraction (SCINTAG XDS 2000), FE-SEM (LEO 982), and TEM (Philips 420 and JEOL 2010). Electron diffraction and composition analysis (EDX) measurements were also made on the TEMs. Samples for TEM analysis were prepared as follows: samples were briefly sonicated in ethanol, which suspended the nanowire material, and then a drop of suspension was placed on a TEM grid and allowed to dry.
Template mediated methods using membranes and nanotubes have been used to prepare a number of materials. However, these nanowires typically have diameters >10 nm, which are larger than those desired for strong quantum confinement effects, and often have polycrystalline structures that make it difficult to probe intrinsic physical properties.

   Table 1 is a summary of single crystal nanowires synthesized. The growth temperatures correspond to ranges explored in these studies. The minimum (Min.) and average (Ave.) nanowhe diameters (Diam.) were determined from TEM and FE-SEM images. Structures were determined using electron diffraction and lattice resolved TEM imaging: ZB, zinc blende; W, wurtzite; and D, diamond structure types. Compositions were determined from EDX measurements made on individual nanowires. All of the nanowires were synthesized using Au as the catalyst, except GaAs, for which Ag and Cu were also used. The GaAs nanowires obtained with Ag and Cu catalysts have the same size, structure and composition as those obtained with the Au catalyst.
Material Growth Min. Diam. Ave. Diam. Structure Growth Ratio of
Temp.

   TO (nm) (nm) Direction Components
GaAs 800-1030 3 19 ZB <111> 1.00:0.97
GaP 870-900 3-5 26 ZB <U1> 1.00:0.98
GaAso.[delta]Po.4 800-900 4 18 ZB <111> 1.00: 0.58: 0.41
InP 790-830 3-5 25 ZB <111> 1.00:0.98
InAs 700-800 3-5 11 ZB <111> 1.00:1.19
InAso.5Po.5 780-900 3-5 20 ZB <111> 1.00: 0.51: 0.51
ZnS 990-1050 4-6 30 ZB <111> 1.00:1.08
ZnSe 900-950 3-5 19 ZB <111> 1.00:1.01
CdS 790-870 3-5 20 W <100>, 1.00:1.04 <002>
CdSe 680-1000 3-5 16 w <110> 1.00:0.99
Sii-xGex 820-1150 3-5 18 D <111> Si[iota]-xGex
 <EMI ID=61.1> 

Fig. 15 shows a pseudobinary phase diagram for Au and GaAs. The liquid Au-GaAs component is designated by L.
Figs. 16A-16C show FE-SEM images of GaAs (Fig. 16A), GaP (Fig. 16B) and GaAso.[delta]Po.4(Fig- 16C) nanowhes prepared by LCG. The scale bars in Figs. 16A-1 C are 2 [mu]m.

   The insets in Figs. 16A-16C are TEM images of GaAs, GaP and GaAs0.6P0.4 nanowires, respectively. The scale bars in are all 50 nm. The high contrast (dark) features correspond to the solidified nanocluster catalysts.
Fig. 17 A shows a diffraction contrast TEM image of a ca. 20 nm diameter GaAs nanowire. The inset shows a convergent beam electron diffraction pattern (ED) recorded along the <112> zone axis. The [111] dhection of the ED pattern is parallel to the whe axis, and thus shows that growth occurs along the [111] direction. The scale bar corresponds to 20 nm. Fig. 17B shows a high-resolution TEM image of a ca. 20 nm diameter GaAs nanowhe. The lattice spacing perpendicular to the nanowire axis, 0.32 +- 0.01 nm, is in good agreement with the 0.326 nm spacing of (111) planes in bulk GaAs. The scale bar corresponds to 10 nm.

   Figs. 17C and 17D show high-resolution TEM images of 10 and 6 nm diameter, respectively, GaAso.[omicron]Po[Lambda]nanowires. The (111) lattice planes (perpendicular to the wire axes) are clearly resolved in all three nanowires. The scale bars in Figs. 17C and 17D are 5 nm.
Fig. 18A shows a FE-SEM image of CdSe nanowires prepared by LCG. The scale bar corresponds to 2 [mu]m. The inset in Fig. 18A is a TEM image of an individual CdSe nanowire exhibiting nanocluster (dark feature) at the whe end. EDX shows that the nanocluster is composed primarily of Au. The scale bar is 50 nm. Fig. 18B shows a diffraction contrast TEM image of a 18 nm diameter CdSe nanowire. The uniform contrast indicates that the nanowhe is single crystal. The inset in Fig. 18B is an ED pattern, which has been indexed to the wurtzite structure, recorded along the <001> zone axis.

   The [110] direction of the ED pattern is parallel to the wire axis, and thus shows that growth occurs along the [110] direction. The scale bar is 50 nm. Fig. 18C shows a high-resolution TEM image of a ca. 13 nm diameter CdSe nanowire exhibiting well-resolved (100) lattice planes. The experimental lattice spacing, 0.36 +- 0.01 nm is consistent with the 0.372 nm separation in bulk crystals. The 30[deg.] orientation (100) lattice planes with respect to the nanowhe axis is consistent with the [110] growth direction determined by ED. The scale bar corresponds to 5 nm.
Laser-Assisted Catalytic Growth of Single Crystal GaN Nanowires Single crystalline GaN nanowires have been synthesized in bulk quantities using laser-assisted catalytic growth (LCG).

   Laser ablation of a (GaN, Fe) composite target generates liquid nanoclusters that serve as catalytic sites confining and directing the growth of crystalline nanowires. Field emission scanning electron microscopy shows that the product primarily consists of wire-like structures, with diameters on the order of 10 nm, and lengths greatly exceeding 1 [mu]m. Powder X-ray diffraction analyses of bulk nanowire samples can be indexed to the GaN wurtzite structure, and indicate >95% phase purity. Transmission electron microscopy, convergent beam electron diffraction, and energy dispersive X-ray fluorescence analyses of individual nanowires show that they are GaN single crystals with a [100] growth dhection.

   The synthesis of bulk quantities of single crystal nanowires of GaN and other technologically important semiconducting nitride materials should open up many opportunities for further fundamental studies and applications. Herein we report the bulk synthesis of single crystalline GaN nanowires. Laser ablation of a composite target of GaN and a catalytic metal generates liquid nanoclusters that serve as reactive sites confining and directing the growth of crystalline nanowhes. Field emission scanning electron microscopy (FE-SEM) shows that the product primarily consists of wire-like structures. Powder X-ray diffraction (PXRD) analyses of bulk nanowire sample can be indexed to the GaN wurtzite structure, and indicate >95% phase purity.

   Transmission electron microscopy (TEM), convergent beam electron diffraction (CBED), and energy dispersive X-ray fluorescence (EDX) analyses of individual nanowires show that they are GaN single crystals with a [100] growth direction.
Nanostructured GaN materials have attracted extensive interest over the past decade due to their significant potential for optoelectronics. These studies have primarily focused on zero dimensional (OD) quantum dots and two dimensional (2D) quantum well structures, which can be readily synthesized using established methods. Investigations of one dimensional (ID) GaN nanowires, which could enable unique opportunities in fundamental and applied research, have been limited due to difficulties associated with their synthesis. Specifically, there has been only one report of GaN nanowire growth.

   In this work, carbon nanotubes were used as templates in the presence of Ga-oxide and NH3vapor to yield GaN nanowires. We have exploited predictable synthetic approach for GaN nanowire growth called laser-assisted catalytic growth (LCG). In this method, a pulsed laser is used to vaporize a solid target containing deshed material and a catalyst, and the resulting liquid nanoclusters formed at elevated temperature direct the growth and define the diameter of crystalline nanowires through a vapor-liquid-solid growth mechanism. A key feature of this method is that the catalyst used to define ID growth can be selected from phase diagram data and/or knowledge of chemical reactivity.

   A related approach termed solution-liquid-solid phase growth has been used by Bulro and coworkers to prepare nanowires of several III-V materials in solution, although not nitrides.
In the case of GaN, detailed information on ternary phase diagrams relevant to LCG (i.e., catalyst-Ga-N) is unavailable. However, we can use knowledge of the growth process to choose rationally a catalyst. Specifically, the catalyst should form a miscible liquid phase with GaN but not form a more stable solid phase under the nanowire growth conditions. The guiding principle suggests that Fe, which dissolves both Ga and N, and does not form a more stable compound than GaN will be a good catalyst for GaN nanowire growth by LCG.

   The overall evolution of nanowire growth following the generation of the catalytic nanocluster by laser ablation is illustrated in Fig. 19.
Significantly, we find that LCG using a GaN/Fe target produces a high yield of nanometer diameter wire-like structures. A typical FE-SEM image of the product produced by LCG (Fig. 20A) shows that the product consists primarily of ID structures with diameters on the orders of 10 nm and lengths greatly exceeding 1 [mu]m; that is, high aspect ratio nanowires. The FE-SEM data also show that the products consist of ca. 90% nanowires, with the remaining being nanoparticles. We have also assessed the overall crystal structure and phase purity of the bulk nanowire samples using PXRD (Fig. 20B). All the relatively sharp diffraction peaks in the PXRD pattern can be indexed to a wurtzite structure with lattice constants of a = 3.187 and c = 5.178 A.

   These values are in good agreement with literature values for bulk GaN: a = 3.189, c = 5.182 A. In addition, comparison of the background signal and observed peaks indicates that the GaN wurtzite phase represents >95% of the crystalline material produced in our syntheses.
The LCG experimental apparatus is similar to that reported previously. A GaN/Fe (atomic ratio (GaN):Fe=0.95:0.05) composite target was positioned with a quartz tube at the center of a furnace. The experimental system was evacuated to 30 mtorr, and then refilled with anhydrous ammonia gas. While the pressure and flow rate were maintained at ca. 250 torr and 80 seem, respectively, the furnace temperature was increased to 900 [deg.]C at 30 [deg.]C /min.

   A pulsed Nd-YAG laser (1064 nm, 8 ns pulse width, 10 Hz repetition, 2.5 W average power) was then used to ablate the target with a typical ablation duration of 5 min. After ablation, the furnace was turned off and allowed to cool to room temperature. The system was then vented and light yellowish powders were collected from the end of inner quartz tube wall. The product was used directly for FE-SEM and PXRD studies. The product was suspended in ethanol and then transferred onto TEM grids for TEM, CBED and EDX measurements.
The morphology, structure and composition of the GaN nanowires have been characterized in further detail using TEM, CBED and EDX. TEM studies show that the nanowires are straight with uniform diameters, and typically terminate in a nanoparticle at one end. Fig. 20A shows a representative diffraction contrast image of one nanowire.

   The uniform contrast along the wire axis indicates that the nanowire is a single crystal. The nanoparticle (dark, high contrast feature) observed at the nanowire end is faceted as expected following crystallization of the liquid nanocluster (Fig. 19). We have also used EDX to address the composition of the nanowires and terminal nanoparticles. Data recorded on the nanowire show only Ga and N in a ratio ca. the same as a GaN standard, while the nanoparticles contain Ga, N, and Fe. The presence of Fe (with Ga and N) only in the terminal nanoparticle confirms the catalytic nature of Fe in the synthesis.
To probe further the importance of the catalyst, we have also investigated GaN nanowire growth using a Au catalyst.

   Gold has been used recently as a catalyst for growth of a number of nanowires of III-V and II-VI material, and as such might be expected to also function effectively in the growth of GaN nanowires. However, Au exhibits poor solubility of N and thus may not transport N efficiently to the hquid/solid growth interface. Consistent with this analysis, we have been unable to obtain GaN nanowire using the Au catalyst. We believe that this highlights the important role of the catalyst and how it can be rationally chosen.
Lastly, we have characterized the structure of GaN nanowhes in greater detail using CBED and high resolution TEM (HRTEM). A typical CBED pattern (inset, Fig. 21 A) of a nanowire exhibits a sharp diffraction pattern consistent with the single crystal structure inferred from the diffraction contrast images.

   Indexing this pattern further demonstrates that the [100] dhection is aligned along the wire axis. In addition, Fig. 21B shows a lattice resolved HRTEM image of a GaN nanowhe with a ca. 10 nm diameter. The image, which was recorded along the <001> zone axis, shows clearly the single crystal structure of the nanowire and the lattice planes along the [100], [010] and [-110] directions. This image demonstrates that the [100] direction runs parallel to the wire axis, and thus confirms the [100] growth dhection in GaN nanowires.
In conclusion, we have exploited the LCG method for the rational synthesis of GaN nanowires. Highly pure GaN nanowires were obtained as single crystals with a unique [100] growth direction.

   We believe that this approach, which is based on the predictable choice of catalyst and growth conditions, can be readily extended to the synthesis of InN, (GaIn)N alloys and related nitride nanowires. The synthesis of bulk quantities of single crystal nanowhes of GaN and other technologically important semiconducting nitride materials is expected to open up many opportunities for further fundamental studies and applications.
Fig. 19 is a schematic diagram showing GaN nanowhe growth by laser-assisted catalytic growth.
Fig. 20 A shows a FE-SEM (LEO 982) image of bulk GaN nanowires synthesized by LCG. The scale bar corresponds to 1 [mu]m. Fig. 20B shows a PXRD (Scintag, XDS2000) pattern recorded on bulk GaN nanowires.

   The numbers above the peaks correspond to the (hkl) values of the wurtzite structure.
Fig. 21 A shows a diffraction contrast TEM (Philips, EM420) image of a GaN nanowire that terminates in a faceted nanoparticle of higher (darker) contrast. The inset in Fig. 21 A shows a CBED pattern recorded along <001> zone axis over the region indicated by the white circle. The white scale bar corresponds to 50 nm. Fig. 21B shows a HRTEM (JEOL 2010) image of another GaN nanowire with a diameter of ca. 10 nm. The image was taken along <001> zone axis. The [100], [010] and [-110] directions are indicated with the [100] parallel to the wire axis.

   The white scale bar corresponds to 5 nm.
Nanoscale electronic and optoelectronic devices assembled from indium phosphide nanowire building blocks
One dimensional nanostructures, such as nanowires (NWs) and nanotubes (NTs), are ideally suited for efficient transport of charge carriers and excitons, and thus are expected to be critical building blocks for nanoscale electronics and optoelectonics. Studies of electrical transport in carbon NTs have led to the creation of field effect transistors (FETs), single electron transistors, rectifying junctions and chemical sensors. These results indicate exciting applications possible from such materials, although the use of NT building blocks is quite limited in that selective growth and/or assembly of semiconducting or metallic NTs is not currently possible.

   The use of nanoscale structures as building blocks for bottom-up assembly of active devices and device arrays, which can eliminate the need for costly fabrication lines, will require that the electronic properties of the different blocks be both defined and controllable. To this end we report the rational assembly of functional nanoscale devices from compound semiconductor NW building blocks in which the electrical properties have been controlled by doping. Gate-dependent transport measurements demonstrate that indium phosphide (InP) NWs can be synthesized with controlled n-type and p-type doping, and can function as nanoscale FETs. In addition, the availability of well-defined n- and p-type materials has enabled the creation of p-n junctions by forming crossed NW arrays. Transport measurements reveal that the nanoscale p-n junctions exhibit well-defined current rectification.

   Significantly, forward biased InP p-n junctions exhibit strong, quantum confined light emission making these structures perhaps the smallest light emitting diodes created to date. Lastly, electric field directed assembly is shown to be one strategy capable of creating highly integrated and functional devices from these new nanoscale building blocks.
Single crystal InP NWs have been prepared by a laser-assisted catalytic growth (LCG), which has been described previously. The n-type and p-type InP NWs were prepared using tellurium (Te) and zinc (Zn) as dopants, respectively, and found to be of similar high quality as NWs produced without the addition of dopants. Field emission scanning electron microscopy (FE-SEM) images of as-synthesized Zn-doped InP NWs (Fig. 22 A) demonstrate that the wires extend up to tens of micrometers in length with diameters on the order of 10 nanometers.

   High-resolution transmission electron microscopy (TEM) images (inset, Fig. 22A) further show that the doped NWs are single crystals with <111> growth directions. Generally, a 1-2 nm amorphous over-layer on the NWs is visible in TEM images. This thin layer is attributed to oxides formed when the NWs are exposed to ah after synthesis. The overall composition of individual NWs determined by energy dispersive X-ray (EDX) analysis was found to be 1:1 In:P, thus confirming the stoichiometric composition of the NWs. EDX and other elemental analytic methods are, however, insufficiently sensitive to determine the doping level in individual NWs.
To confirm the presence and type of dopants in the NWs, we have performed gatedependent, two terminal transport measurements on individual NWs.

   In these measurements, the NW conductance will respond in an opposite way to change in gate voltage (Vg) for n-and p-type NWs. Specifically, Vg> 0 will lead to an accumulation of electrons and an increase in conductance for n-type NWs, while the same applied gate will deplete holes and reduce conductance for p-type NWs. Figs. 22B and 22C and 100c show the typical gate-dependent I-V curves obtained from individual Te- and Zn-doped NWs respectively. The I-V curves are nearly linear for both types of NWs at Vg= 0, indicating the metal electrodes make ohmic contact to the NWs. The transport data (Fig. 22B) recorded on Te-dopedNWs show an increase in conductance for Vg> 0, while the conductance decreases for Vg< 0. These data clearly show that Te-doped InP NWs are ntype.

   Gate-dependent transport data recorded on Zn-doped NWs show opposite changes in conductance with variation in Vgcompared to the n-type, Te-doped InP NWs. Specifically, for Vg> 0, conductance decreases and for Vg< 0 conductance increases (Fig. 22C). These results demonstrate that the Zn-doped InP NWs are p-type.
Our results are quite reproducible. Measurements made on over twenty individual NWs, with diameters ranging from 20 nm to 100 nm, show gate effects in each case that are consistent with the dopant used during InP NW synthesis. In addition, the gate voltage can be used to completely deplete electrons and holes in n- and p-type NWs such that the conductance becomes immeasurably small. For example, the conductance of the NW in Fig. 22B can be switched from a conducting (on) to an insulating (off) state when Vgis less than or equal to -20 V, and thus it functions as a FET.

   The conductance modulation can be as large as 4-5 orders of magnitude for some of the NWs. The relatively large switching voltage is related to the thick (600 nm) oxide barrier used in our measurements. This gate-dependent behavior is similar to that of metal-oxide-semiconductor (MOS) FETs and recent studies of semiconducting NT FETs. An important distinction of our work with respect to NTs is that predictable semiconducting behavior can be achieved in every NW. Taken together, these results clearly illustrate that single crystal InP NWs can be synthesized with controlled carrier type. Because these NWs are produced in bulk quantities, they represent a readily available material for assembling devices and device arrays.

   The availability of well-defined n-and p-type NW building blocks opens up the possibility of creating complex functional devices by forming junctions between two or more wires. To explore this exciting opportunity, we have studied the transport behavior of n-n, p-p and p-n junctions formed by crossing two n-type, two p-type, and one n-type and one p-type NW, respectively. Fig. 23 A shows a representative crossed NW device formed with a 29 nm and 40 nm diameter NW. The four arms are designated as A, B, C, D for the simplicity of discussion below. Significantly, the types of junctions studied are controllable for every experiment since we can select the types of NWs used to produce the crossed junction prior to assembly. Figs. 23B and 23C show the current-voltage (I-V) data recorded on n-n and p-p junctions, respectively.

   For both types of junctions, the transport data recorded on the individual NWs (AC, BD) show linear or nearly linear I-V behavior (curves 80, Fig. 23B and curve 82, Fig. 23C). These results show that the metal electrodes used in the experiments make ohmic or nearly ohmic contact to the NWs, and will not malce nonlinear contributions to the I-V measurements across junctions. In general, transport measurements made across the n-n and p-p junctions show linear or nearly linear behavior, and allow us to infer two important points about junctions made in this way. First, interface oxide between individual NWs does not produce a significant tunneling barrier, since such a barrier will lead to highly non-linear I-V behavior.

   Second, the I-V curves recorded through each pair (AB, AD, CB, CD) of adjacent arms shows a similar current level, which is smaller than that of the individual NWs themselves. These results demonstrate that the junction dominates the transport behavior. Lastly, our data indicate that individual NWs make reasonably good electrical contact with each other, despite the small contact area (10<"12>-10<_1>[deg.] cm<2>) and simple method of junction fabrication.
The good contact between individual NWs provides the basis for exploring these NW to make functional devices. As an example, we have made p-n junctions from crossed p- and n-type NWs. These junctions can be made reproducibly by sequential deposition of dilute solutions of n- and p-type NWs with intermediate drying. Fig. 23D shows typical I-V behavior of a crossed NW p-n junction.

   The linear I-V of the individual n- and p-type NWs components (curves 84 and 86) indicates ohmic contact between the NWs and metal electrodes. Transport behavior across the p-n junction (curves 88) shows clear current rectification; i.e., little current flows in reverse bias, while there is a sharp current onset in forward bias. Significantly, the behavior is similar to bulk semiconductor p-n junctions, wliich form the basis for many critical electronic and optoelectronic devices. In a standard p-n junction, rectification arises from the potential barrier formed at the interface between p- and n-type materials.

   When the junction is forward biased (p-side positively biased), the barrier is reduced and a relatively large current can flow through the junction; on the other hand, only small current can flow in reverse bias since the barrier is further increased.
There are several reasons we believe that the observed rectification is due to the pn junction fo[pi]ned at the crossing point between p- and n-type InP NWs. First, the linear or nearly linear I-V behavior of individual p- and n-type NWs used to make the junction shows that ohmic contact have been made between the NWs and metal electrodes. This excludes the possibility that rectification arises from metal-semiconductor Schottky diodes.

   Second, the I-V behavior of the junction determined through every pair (AB, AD, CD, CD) of adjacent electrodes (curves 88 in Fig. 23D) exhibits a similar rectification effect and current level, which is also much smaller than the current level through the individual NWs. These results demonstrate that the junction dominates the I-V behavior. Thhd, four terminal measurements in which current is passed through two adjacent electrodes (e.g., A-B) while the junction voltage drop is measured across two independent electrodes (e.g., C-D) exhibit similar I-V and rectification with only a slightly smaller voltage drop (0.1-0.2 V) compared to two terminal measurements at the same current level.

   Lastly, measurements made on ten independent p-n junctions showed similar rectification in the I-V data; i.e., significant current can only flow through p-n junctions when the ptype NW is positively biased.
The above data show unambiguously that we can now rationally fabricate nanoscale p-n junctions. In direct band gap semiconductors like InP, the p-n junction forms the basis for the critical optoelectronics devices, including light emitting diodes (LED) and lasers. To assess whether our nanoscale devices might behavior similarly, we have studied the photoluminescence (PL) and electroluminescence (EL) from crossed NW p-n junctions. Significantly, EL can be readily observed from these nanoscale junctions in forward bias. Fig. 24A shows an EL image taken from a typical NW p-n junction at forward bias, and the inset shows the PL image of a crossed NW junction.

   The PL image clearly shows two elongated wire-like structures, and the EL image shows that the light comes from a point-like source. Comparison of the EL and PL images shows that the position of the EL maximum corresponds to the crossing point in the PL image, thus demonstrating the light indeed comes out from the NW p-n junction.
The I-V characteristic of the junction (inset, Fig. 24B) shows clear rectification with a sharp current onset at -1.5 volts. The EL intensity versus voltage curve of the junction shows significant light can be detected with our system at a voltage as low as 1.7 volts. The EL intensity increases rapidly with the bias voltage, and resembles the I-V behavior. The EL spectrum (Fig. 24C) shows a maximum intensity around 820 nm, which is significantly blue shifted relative to the bulk band gap of InP (925 nm).

   The blue-shift is due in part to quantum confinement of the excitons, although other factors may also contribute. The importance of quantum confinement can be seen clearly in EL results recorded from p-n junctions assembled from smaller (and larger) diameter NWs (Fig. 24D), which show larger (smaller) blue-shifts. The ability to tune color with size in these nanoLEDs might be especially useful in the future. The quantum efficiency (electron to photon) of these initial devices is relatively low, -0.001%, which is not surprising since we have paid little attention to optimization. The efficiency is actually comparable to that (¯0.002%) of early bulk InP LEDs.

   We attribute the low quantum efficiency to nonradiative recombination via surface states, and believe that this deleterious process can be reduced by surface passivation.
GaN is a dhect wide bandgap semiconductor material, which emits light in the short wavelength (UV and blue) region at room temperature. Blue LEDs are important as emitters where strong, energy efficient and reliable light source are needed. Also it is important to enable production of full color LED displays and LED white lamp, since blue is one of the three primary colors (red, green and blue).
Here we report the first made BLUE/UV nanoLEDs (light emitting region on the order of 10 nm's), which is constructed with P-type Si and N-type (unintentionally doped) GaN nanowires.

   Together with the nanoLED we reported before wliich emits light in the near IR region, we show the great potential of making LEDs with different materials that would cover the full color spectrum.
Fig. 25A shows an EL image taken from two P-type Si and N-type GaN crossed nanojunctions. The p-Si is doped with Boron. Fig. 25B shows current vs. voltage for various gate voltages. The nanojunction shows good rectification at different gate voltages. The El spectrum shown in Fig 25C shows light emission is about 380 nm and 470nm. A n-InP and p-Si nanojunction has good rectification.
To make highly integrated NW-based devices will ultimately require techniques to align and assemble these building blocks into well-defined arrays.

   To demonstrate the viability of this next stage of development, we have used electric fields (E-field) to align and position individual NWs into parallel and crossed arrays-two basic geometries for integration. The E-field directed assembly was carried out by placing a solution of NWs between electrodes (Fig. 26A), and then applying a bias of 50-100 V. The potential of this approach is readily seen in the case of alignment of a chlorobenzene suspended NWs between parallel electrodes (Fig. 26B). FE-SEM images show that nearly all of the NWs are aligned perpendicular to the parallel electrodes and along E-field direction. We have also used electrode arrays to position individual NWs at specific positions.

   For example, E-field assembly of NWs between an array of electrodes (Fig. 26C) demonstrates that individual NWs can be positioned to bridge pairs of diametrically-opposed electrodes and form a parallel array. In addition, by changing the field direction, the alignment can be done in a layer-by-layer fashion to produce crossed NW junctions (Fig. 26D). These data clearly show that E-field assembly represents a strategy to rationally deposit individual NWs with high degrees of directional and spatial control. We believe that highly integrated functional devices will be readily accessible using our NW building blocks in conjunction with this E-field and/or other assembly techniques.
Taken as a whole, the results presented in this letter provide a rational approach for the bottom-up assembly of nanoscale electronic and optoelectronic devices.

   Our demonstrated ability to assemble active devices in the absence of multi-billion dollar fabrication lines is of critical importance to the field and we believe augers well for the immediate and longer-term advances. We believe that the broad range of NW materials now available and the clearly defined ability to control their electronic properties will make possible nanoscale LEDs that cover the entire visible and near infrared range (e.g., GaN NWs for blue color). Such nanoscale light sources might be useful in creating new types of highly parallel optical sensors and for optical inter-connects in nanoelectronics. Moreover, the assembly of doped NW building blocks clearly has great potential for creating many other types of electronic devices and possibly even lasers. InP NWs were synthesized using LCG.

   The LCG target typically consisted of
94% (atomic ratio) InP, 5% Au as the catalyst, and 1% of Te or Zn as the doping element. The furnace temperature (middle) was set at 800[deg.]C during growth, and the target was placed at the upstream end rather than middle of the furnace. A pulsed (8 ns, 10 Hz) NdYAG laser (1064 nm) was used to vaporize the target. Typically, growth was carried out for 10 minutes with NWs collected at the downstream, cool end of the furnace.
Transport measurement on individual NWs were carried out using published procedures. Briefly, NWs were first dispersed in ethanol, and then deposited onto oxidized silicon substrates (600 nm oxide, 1-10 [Omega]*cm resistivity), with the conductive silicon used as a back gate. Electrical contact to the NWs was defined using electron beam lithography (JEOL 6400). Ni/In/Au contact electrodes were thermally evaporated.

   Electrical transport measurements were made using home built system with < lpA noise under computer control. The n-n and p-p junctions were obtained by random deposition. We first deposited NWs onto oxidized silicon substrates using relatively high concentrations, determined the positions of crossed NWs, and then defined electrodes on all four arms of the cross by electron beam lithography. Ni/In/Au electrodes were used to make contact to the NWs. The p-n junctions were obtained by layer-by-layer deposition. Fhst, a dilute solution of one type (e.g., n-type) of NW was deposited on the substrate, and the position of individual NWs was recorded. In a second step, a dilute solution of the other type (e.g., p-type) of NW was deposited, and the positions of crossed n- and p-type NWs were recorded. Metal electrodes were then defined and transport behavior was measured.

   EL was studied with a home-built micro-luminescence instrument. PL or scattered light (514 nm, Ar-ion laser) was used to locate the position of the junction. When the junction was located, the excitation laser was shut off, and then the junction was forward biased. EL images were taken with a liquid nitrogen cooled CCD camera, and EL spectra were obtained by dispersing EL with a 150 line/mm grating in a 300 mm spectrometer. Figs. 22A-22C illustrate doping and electrical transport of InP NWs. Fig. 22A shows a typical FE-SEM image of Zn-doped InP NWs. Scale bar is 10 [mu]m. inset, lattice resolved TEM image of one 26 nm diameter NW. The (111) lattice planes are visible perpendicular to the wire axis. Scale bar is 10 nm. Figs. 22B and 22C show gatedependent I-V behavior for Te- and Zn-doped NWs, respectively.

   The insets in Figs. 22B and 22C show the NW measured with two terminal Ni/In/Au contact electrodes. The scale bars correspond to 1 [mu]m. The diameter of the NW in Fig. 22B is 47 nm, while that in Fig. 22C is 45 nm. Specific gate- voltages used in the measurements are indicated on the right hand sides of the Figs, on the corresponding I-V curves. Data were recorded at room temperature. Figs. 23 A-23D illustrate crossed NW junctions and electrical properties. Fig. 23 A shows a FE-SEM image of a typical crossed NW device with Ni/In/Au contact electrodes. The scale bar corresponds to 2 [mu]m. The diameters of the NWs are 29 nm (A-C) and 40 nm (B-D); the diameters of the NWs used to make devices were in the range of 20-75 mn. Figs. 23B-23D show I-V behavior of n-n, p-p and p-n junctions, respectively.

   The curves 80 and 82 correspond to the I-V behavior of individual n- and p-NWs in the junctions, respectively. The curves 88 represent the I-V behavior across the junctions. The current recorded for the p- and n- type NWs in Fig. 23D is divided by 10 for better viewing. The solid lines represent transport behavior across one pair of adjacent arms, and the dashed lines represent that of the other three pairs of adjacent arms. Data were recorded at room temperature.
Figs. 24A-24D illustrate optoelectrical characterization of NW p-n junctions. Fig. 24 A is an EL image of the light emitted from a forward biased NW p-n junction at 2.5 V. The inset in Fig. 24A shows the PL image of the junction. Both scale bars correspond to 5 [mu]m. Fig. 24B shows the EL intensity versus voltage.

   The inset in Fig. 24B shows the I-V characteristics and the inset in the inset shows the FE-SEM image of the junction itself. The scale bar corresponds to 5 [mu]m. The n-type and p-type NWs forming this junction have diameters of 65 and 68 nm, respectively. Fig. 24C shows an EL spectrum of the junction shown hi Fig. 24 A. The spectrum peaks at 820 nm. Fig. 24D shows an EL spectrum recorded from a second forward biased crossed NW p-n junction. The EL maximum occurs at 680 nm. The inset in Fig. 24D shows the EL image and demonstrates that the EL originates from the junction region. The scale bar is 5 [mu]m. The n-type and ptype NWs forming this junction have diameters of 39 and 49 nm, respectively. Figs. 26A-26D illustrate parallel and orthogonal assembly of NWs with E-fields.
Fig. 26A is a schematic view of E-field alignment.

   The electrodes (orange) are biased at 50-100 V after a drop of NW solution is deposited on the substrate (blue) Fig. 26B shows a parallel array of NWs aligned between two parallel electrodes. The NWs were suspended in chlorobenzene and aligned using an applied bias of 100 V. Fig. 26C shows a spatially positioned parallel array of NWs obtained following E-field assembly using a bias of 80 V. The top inset in Fig. 26C shows 15 pairs of parallel electrodes with individual NWs bridging each diametrically opposed electrode pair. Fig. 26D shows a crossed NW junction obtained using layer-by-layer alignment with the E-field applied in orthogonal directions in the two assembly steps. The applied bias in both steps was 80 V.

   The scale bars in Figs. 26B-26D correspond to 10 [mu]m.
Bottom-Up Assembly of Nanoscale Electronic Devices from Silicon Nanowires
Four types of important functional nanodevices have been created by rational bottom-up assembly from p and n-type silicon nanowires (SiNWs) with well controlled dopant type and level. In all these devices, electrical transport measurements on individual p and n-type SiNWs suggested ohmic or nearly ohmic contact between SiNWs and leads. Significantly, four-probe measurements across pn junctions consisting of crossed p-type and n-type SiNWs showed current rectification behavior as expected for pn diode behavior. n<+>pn crossed junctions were also assembled to create bipolar transistors, in which common base/emitter current gains as large as 0.94/16 were obtained.

   Complementary inverters made of crossed lightly doped pn junctions showed clear output voltage inverse to input voltage with a gain of 0.13. Tunnel diodes in form of heavily doped SiNW pn crosses showed negative differential resistance (NDR) behavior in forward bias with a peak-to-valley ratio (PVR) of 5 to 1.
Miniaturization of conventional electronics has been intensely pursued recently. But the fundamental limits of lithographical methods will prevent the current techniques from reaching the deep nanoelectronics regime. The use of nanoscale structures as building blocks for the bottom-up assembly of integrated devices, where both the fabrication and assembly of individual blocks are expected to be cheap, can thus eliminate greatly the cost of fabrication lines while still maintaining some concepts that have proven successful in microelectronics.

   One dimensional structures such as nanowires (NWs) and nanotubes (NTs) are ideal candidates as critical building blocks for nanoelectronics. How to construct the functional nanodevices and device arrays with these building blocks is essential to nano science and technology. NTs have been tested as field effect transistors, single electron transistors. The NT-NW heterojunctions, NT intramolecular junctions and crossed junctions have also been demonstrated.

   However, the use of NTs in rational assembly is limited by unpredictability of individual tube properties because the specific growth of metallic and semiconductor NTs is not controllable and controlled doping of semiconductor NTs is difficult.
Previously, we demonstrated the controlled doping of single crystal semiconductor SiNWs, where the type of dopant (p-type and n-type) and the relative doping concentration (from lightly to degenerately) were well controlled. These SiNWs, whose properties are predictable and controllable, therefore provide the critical building blocks for bottom-up assembly of active devices and device arrays. It is possible that the highly dense SiNW device arrays can be formed by the directed assembly of chemical assembly, for example, the specific peptide binding to semiconductor, DNA base matching interaction, and/or the ligand-receptor interaction.

   To realize workable integrated devices, understanding the electrical properties of individual bottom-up assembled active devices is the prerequisite. Here we report the rational assembly of functional nanodevices from these SiNWs with diameters from 20 to 50nm and the device electrical properties. And we demonstrate that control of dopant type and doping level provides us the capability to fabricate multiple types of electronic devices. Four types of important functional structures including pn diodes, bipolar transistors, complementary inverters and tunnel diodes were created by controllably combining SiNWs of varying p and n-type doping levels. Nanoscale pn junctions were created in form of crossed SiNW junctions. Electrical transport measurements on these pn junctions showed the current rectification predictable by semiconductor physics.

   We have exploited our ability to construct n<+>pn crossed SiNW junctions to bipolar transistors which were demonstrated to have common base/emitter current gains as large as 0.94/16. The inverters made of lightly doped pn crosses showed clearly the output voltage inverse to the input voltage with voltage gain of 0.13. And the results of tunnel diodes made of heavily doped pn crossed showed NDR behavior in forward bias with a PVR of 5 to 1. The p-type and n-type SiNWs were synthesized by using diborane and phosphorus, respectively as doping source during laserassisted catalytic growth of SiNWs. Metal leads contact with SiNWs on doped silicon substrate with 600nm thermal oxide were defined by electron beam lithography. The pn, pp and nn junctions were formed by crossing one p-type and one n-type, two p-type and two n-type SiNWs, respectively.

   The types of junctions were controlled by choosing the types of SiNWs used to create a given junction. A typical field emission scanning electron microscopy (FE-SEM) image of cross junctions is shown in Fig. 27 A, where the four contact leads are labeled as 1, 2, 3 and 4 for the convenience of discussion. Fig. 27B shows current versus voltage (I-V) data on a pn crossed junction with diameters of p and n-type SiNWs as small as 20.3 nm and 22.5 nm, respectively. Four-terminal measurements across junction were performed by flowing current between two adjacent leads (e.g., leads 1-2 or leads 1-4, the positive current dhection is from p to n-type SiNW) and measuring the voltage drop between the other two leads (e.g., leads 3-4 or leads 3-2).

   The I-V curve across junction (Fig. 27B curve 130) shows little current in reverse bias (negative bias in our setup) and very sharp current onset in forward bias (positive bias). In contrast, single p (between leads 1-3) and n-type (between leads 2-4) SiNWs show linear I-V behavior (Fig. 27B curves 110 and 120, respectively), which suggests ohmic (not rectifying) contact between SiNWs and leads. And thus this rectifying behavior must be caused by junction itself. This behavior can be explained by the energy band diagrams of a pn junction diode. The built-in potential barrier forms at the junction interface when p and n-type SiNW contact with each other. Electrons can not tunnel through the wide space charge region forming at the junction interface but can be transported by thermal excitation.

   Forward bias decreases the built-in potential barrier and thus large amount of current can flow (Fig. 27E), while reverse bias increases the barrier and thus current level is low (Fig. 27F).
The p and n-type SiNWs were dispersed in to aceton separately, p-n junctions were obtained by sequential deposition. The solution of one type of SiNWs (e.g., n-type) was first deposited onto the substrate and the positions of SiNWs were recorded with respect to alignment marks. Secondly, the solution of the other type of SiNWs (e.g., p-type) was deposited and the positions of crossed pn junctions were recorded, pp or nn junctions were obtained by depositing only one type of SiNWs : p-type or n-type. The junction positions were then recorded.

   The reasons why we believe the rectifying behavior is pn diode behavior instead of some other asymmetric tunneling barrier at the junction interface are: (a). The intrinsic oxide layer of SiNWs is thin enough that electrons can easily tunnel through the oxide layer and the reasonable strong coupling between p and n-type whe at the junction still exists and thus the built-in potential barrier can form. This is confirmed by the transport measurements on pp and nn junctions. The single wires (between leadsl-3, 2-4) in pp (Fig. 27C curves 110) and nn junctions (Fig. 27D curves 120) show linear or almost linear I-V behavior suggesting good contact. Two terminal measurements (between leadsl-2, 1-4, 23, or 3-4) on pp (Fig.27C curves 130) and nn (Fig. 27D curves 130) junctions show linear and almost linear I-V.

   Comparing two-terminal measurement resistance across junctions to single SiNW resistance, we find that the magnitude of junction resistance is similar to the wire resistance, suggesting that the oxide doesn't cause significant electron tunneling barrier, (b) The measurements on 20 independent pn junctions showed consistent correct rectifying behavior.
As the basic unit of most semiconductor devices, pn junctions provide the characteristics needed for rectifiers, amplifiers, switching circuits and many other electronic circuit functions. Success in making pn junction from SiNW crosses provides us the possibility to make other important functional devices. To demonstrate we can create not only passive device: p-n diode, but also the active device, we constructed bipolar transistor, which is capable of current gain.

   A bipolar transistor is a n<+>pn (Fig. 28A left) or p<+>np junction device, which requhes high doping level in emitter, low doping in base and collector. Well control in doping of SiNWs provides us the capability to make this complex device. Our n<+>pn bipolar transistors were constructed by mechanically manipulating two n-type SiNWs (one heavily doped, the other lightly doped) onto one lightly doped p-type wire and were operated in common base configuration (Fig. 28A right). Fig. 28B is a typical SEM image of bipolar transistors. The SiNWs and junctions in transistors were first characterized individually. The I-V curves of three individual SiNWs are linear and the two individual junctions have correct rectifying behavior. Then the n<+>type SiNW was used as emitter while the n-type as collector to do bipolar transistor measurements.

   The emitter-base (E-B) is always forward biased to inject electrons into base region. When the collector-base (C-B) voltage is greater than zero, the transistor is operated in the active mode, in which the C-B junction is reverse biased and only a very small leakage current will flow across the junction. However, the electrons injected from emitter can diffuse through the base to reach the C-B junction space charge region and will be collected by collector. The actual collector current depends only on the injected electrons from emitter and thus depends only on the E-B voltage. This is clearly seen in Fig. 28C regime II, where the collector current goes high with the forward E-B voltage while change slowly with C-B voltage which results from Early effect and the existence of slowly increasing leakage current with reverse bias.

   This demonstrates the transistor action: large current flow in a reverse biased collector junction can result from carriers injected from a nearby emitter junction. When the (C-B) voltage is bellow zero, the bipolar transistor works in saturation mode (Fig. 28C regime I), in which both E-B and CB junctions are forward biased. The collector current from emitter injection will be compensated by the forward biased C-B current. So the collector current goes down with forward C-B voltage. The higher the forward bias on E-B, the higher the forward bias on C-B needed to compensate the current to zero (Fig. 28C curve 1 to 4).
The n<+>[rho]n bipolar transistors were fabricated by deposition and machanical manipulation. First, p-type SiNWs were deposited from solution onto the substrate.

   In the second step, the n<+>and n-type SiNWs were attached to sharp STM tips and released onto the p-type SiNWs under optical microscope.
The common base current gain of the bipolar transistor in active mode is as large as 0.94 (Fig. 28D) and the common emitter current gain is 16. Three important points are suggested from this large current gain, (a) The efficiency of electron injection from emitter to base is quite high, resulting from the higher doping concentration in emitter than in base, (b) Although the base region is wide (15um), the active interaction between emitter and collect still exists.

   Most of injected electrons from emitter can go through the base to reach the collector, which suggests that the mobility of electrons in base is quite high, (c) The space charge region between base and collector has high efficiency to collect electrons and sweep them into collector, suggesting that the oxide barrier at the interface doesn't contribute significantly, which further confirms our analysis on single pn junctions. Our bipolar transistor can be improved, for example, by reducing the base width, to approach the performace of the commercial one in which the typical common base current gain is larger than 0.99.
To exploit the applications of these bottom-up building blocks in logic circuit, and to further demonstrate the capability that contolled doping of SiNWs can provide us, we create a complementary inverter in form of a lightly p and a lightly n-doped SiNW cross.

   The schematics of an crossed SiNW inverter structure is shown in Fig. 29 A (bottom) while that of an inverter in semiconductor physics is shown in Fig. 29 A (top). The lightly doped p and n-type SiNWs in the inverter show very large gate effect and can be completely depleted as is shown for p-type SiNW in Fig. 29B inset. As seen in Fig. 29B, the output voltage is negative (zero) with the positive(negative) input voltage, which is the typical inverter behavior. This behavior can explained like this: the depletion of n-type (p-type) wires by negative (positive) input makes the output equal to ground (bias). The voltage gain is calculated as 0.13, the slope of voltage inversion.

   The gain is lower than that in commercial inverters which is larger than 1, but can be improved by using thinner gate oxide layer instead of the 600nm oxide, which reduces the gate response of SiNWs, and using more lightly doped SiNWs, which needs more effort to make ohmic contact with and to be further investigated.
While two crossed lightly doped p and n-type SiNWs make inverters, two crossed degenerately doped p<+>and n<+>-type SiNWs can form tunnel diodes. In contrast to the pn junction, the tunnel diode do not show rectifying behavior, but rather showNDR behavior in forward bias, with a PVR of 5 to 1 shown in Fig. 29C. The difference can be explained by Esaki diode mechanism. The built-in potential forms when p<+>and n<+>-ty[rho]e contact each other, but the space charge region width is thin enough to allow electron tunneling.

   Electrons can tunnel through this thin space charge region under reverse bias (Fig. 29D left) and low forward bias (Fig. 29D middle) causing the current to flow. Beyond a certain point, a further increase in the forward bias results in the condunction band of the n-side moving into the band gap of the p-side (Fig. 29D right) which suppresses electron tunneling and thereby reduces current. Further increases of forward bias reduce the built-in potential barrier which allows thermal excitation mechanism to dominate conduction and the current goes high.
The results described here demonstrate the bottom-up assembly of multiple types of nanoscale electronic devices from doped SiNWs with control over both dopant type and doping level. The individual devices show predictable behaviors similar to the conventionally fabricated devices.

   The mass production and high mtergration of these functional nanodevices can be realized by chemical assembly assisted with electric field and flowing solution alignment, which will lead to exciting practical applications in nanoelectronics while avoiding high cost fabrication lines. Moreover, we can expect that, in conjunction with optical signal, pn diode crosses can function as photodiodes and pn solar cells, and bipolar transistor crosses can form phototransistors.
The alignment of NW by electric field and flowing solution produced one-type of parallel NW arrays. Switching the direction of electric field and flowing solution to lay down the the other type of NWs can form very dense NW crosses. Figs. 27A-27F illustrate crossed SiNW junctions. Fig. 27A shows atypical FE[not]
SEM image of crossed NW junctions with Al/Au as contact leads.

   The scale bar is 2 [mu]m.The diameters of NWs are in the range of 20 to 50nm. Figs. 27B-27D show I-V behavior of pn, pp and nn junctions, respectively. The curves 110 and 120 correspond to the I-V behavior of individual p and n-type SiNWs in junctions, respectively. The curves 130 represent the fom-terrninal I-V through pn junction in Fig. 27B and two terminal I-V through pp and nn junction in Figs. 27C and 27D, respectively. In Fig. 27B, the solid line is I-V by following current between lead 1 and 2 and simultaneouly measuring the voltage between lead 3 and 4 while the dashed line correponds to that by following current between 1 and 4 and measuring voltage between 3 and 2. In Figs. 27C and 27D, the solid lines are I-V across one pair of adjacent leads (1-2) and the dashed lines are those across the other three pairs (1-4, 2-3, 3-4).

   Figs. 27E and 27F show the energy band diagrams of a pn junction under forward bias and reverse bias, respectively.
Figs. 28A-28D illustrate n<+>pn crossed SiNW bipolar transistors. Fig. 28A shows the common base configuration schematics of an n pn bipolar transistor in semiconductor physics (left) and in crossed SiNW structure (right). The n , p and n-type SiNWs function as emitter, base and collector, respectively. Base is grounded. Emitter is negatively biased at specific values. Collector voltage is scanned from postive to negative. Fig. 28B shows a typical FE-SEM image of SiNW bipolar transistor. The scale bar is 5 [mu]m. Fig. 28C shows a collector current vs collector-base voltage behavior recorded on an n<+>pn transistor with emitter and base SiNWs 15um apart. Curve 1 to 4 correspond to the behavior at emitter-base voltages of -1, -2, -3, -4V.

   Regime I and II are separated by dashed line, correponding to saturation mode and active mode, respectively. Fig. 28D shows common base current gain vs collector-base voltage.
Figs. 29A-29D illustrate complementary inverters and tunnel diodes. Fig. 29A shows schematics of a complementary inverter structure in semicondutor physics (top) and that formed by a lightly doped pn cross (bottom). In bottom schematics, one end' of n-type NW is biased at -5V and one end of p-type NW is grounded. Input voltage is back gate voltage and the other ends of p and n-type NWs are shorted as output terminal. Fig. 29B shows output voltage vs input voltage data in a pn cross inverter. The inset in Fig. 29B is the I-V curves of p-type NW in the inverter. Curve 1 to 5 correspond to I-V at back gate voltage -50, -30, -10, 0 and 10V, respectively.

   The n-type NW in this inverter has similar I-V behavior and can be completely depleted at a gate voltage of -30V. Fig. 29C shows two terminal mearsurement data of a tunnel diode made from a heavily doped pn cross. The I-V behavior of individual p and n-type SiNWs have been tested to be linear. The inset in Fig. 29C spreads out the part of I-V curve showing NDR. Fig. 29D shows the energy band diagrams of a crossed SiNW tunnel diode. At reverse bias (e.g. at position 1 in Fig. 29C) , electrons can tunnel through the junction (left diagram). At small forward bias (e.g. at position 2 in Fig. 29C), electron tunneling is also permitted (middle diagram). At further increased forward bias (e.g. at position 3 in Fig. 29C), electron tunneling is forbidden (right diagram).
Controlled Placement of Nanowires on Surfaces I.

   A stable suspension of Nanowhes (NWs) in ethanol was prepared by sonicating NWs in ethanol in a bath sonicator for around 3 minutes.
2. The substrate ( silicon wafter ) was covered by a self-assembled monolayer (SAM) with -NH2 termination.
3. The microfluidic molds are made of PDMS . A microchannel formed when the substrate came in contact with PDMS mold, with three walls of the conduit corresponding to the molded feathures in the mold and the fourth corresponded to the surface of the substrate, which was chemically modified as described in 2. 4. The NW suspension flowed through as-made microchannel with an application of +100 volt bias on the substrate. After a flowing time around lOmin, the channel was washed with ethanol, then let dry naturally. When the PDMS stamp was removed, we got NWs arrays aligned in the flow direction on the substrate surface.
5.

   By alteration the flow direction, and applying layer-by-layer scheme we can get multiple cross-bars out of the NW arrays, which is supposed to be the most important configuration for the devices we made from NWs.
6. By patterning the surface, we can get the NWs aligned ( positioned) in certain place, thus make it possible to create more regular arrays of devices.
Patterning process: I. a layer of PMMA was spin-coated on the substrate surface, then use EBL (Electron Beam Lithography) to write pattern, i.e. to selectively exposed Si surface which was later chemically functionalized. (as in 2). II. Now we have the PMMA trenches, the bottom of which is exposed Si surface covered with -NH2 SAM. When we flow NW suspensions over these patterns, (as described in 4, 5, just the surface in this case is patterned), the NWs will be directed into PMMA trenches.

   At last we lift off the PMMA, together with the NWs stick on PMMA surface. So only those stay on the bottom of the PMMA trenches left on the substrate surface, thus we get clean arrays of devices.
Directed Assembly of One Dimensional Nanostructures into Functional Networks
One-dimensional nanostructures, such as nanowhes and nanotubes, represent the smallest dimension for efficient transport of electrons and excitons, and thus are ideal building blocks for hierarchical assembly of functional nanoscale electronic and photonic structures. We report an approach for the hierarchical assembly of one-dimensional nanostructures into well-defined functional networks. We show that nanowires can be assembled into parallel arrays with control of the average separation, and by combining fluidic alignment with surface patterning techniques that it is also possible to control periodicity.

   In addition, complex crossed nanowire arrays can be prepared using layer-bylayer assembly with different flow directions for sequential steps. Transport studies show that the crossed nanowire arrays form electrically conducting networks, with individually addressable device function at each cross point.
Nanoscale materials, for example, nanoclusters and nanowhes (NWs), represent attractive building blocks for hierarchical assembly of functional nanoscale devices that could overcome fundamental and economic limitations of conventional lithography-based fabrication. Research focused on zero-dimensional nanoclusters has led to significant advances, including the assembly of arrays with order extending from nanometer to micrometer length scales.

   In contrast, the assembly of one-dimensional (ID) nanostructures, such as NWs and carbon nanotubes (NTs), has met with much less success, although these materials offer great potential as building blocks for applications in nanoelectronics and photonics.
To achieve the substantial potential of NWs and NTs in these and other areas of nanotechnology, will require the controlled and predictable assembly of well-ordered structures. We report an approach for hierarchical assembly of ID nanostructures whereby NWs are aligned in fluid flows with the separation and spatial location readily controlled. Crossed NW arrays were also prepared using layer-by -layer assembly with different flow directions for sequential steps. Transport studies show that the crossed NW arrays form electrically conducting networks, with individually addressable device function at each NW/NW cross point.

   This approach can be potentially used for organizing other ID nanostructures into highly integrated device arrays, and thus offers a general pathway for bottom-up assembly of new electronic and photonic nanosystems.
The gallium phosphide (GaP), indium phosphide (InP) and silicon (Si) NWs used in these studies were synthesized by laser assisted catalytic growth, and subsequently suspended in ethanol solution. In general, we have assembled arrays of NWs by passing suspensions of the NWs through fluidic channel structures formed between a [rho]oly(dimethylsiloxane) (PDMS) mold and a flat substrate (Fig. 30A and 30B).

   Parallel and crossed arrays of NWs can be readily achieved using single (Fig. 30 A) and sequential crossed (Fig. 30B) flows, respectively, for the assembly process as described below.
A typical example of parallel assembly of NWs (Fig. 31A) shows that virtually all the NWs are aligned along one dhection; i.e. the flow direction. There are also some small deviations with respect to the flow direction, which we will discuss below. Examination of the assembled NWs on larger length scales (Fig. 3 IB) shows that the alignment readily extends over hundreds of micrometers.

   Indeed, alignment of the NWs has been found to extend up to millimeter length scales, and seem to be limited by the size of the fluidic channels, based on experiments carried out using channels with widths ranging from 50 to 500 [mu]m and lengths from 6-20 mm.
We have carried out several types of experiments to understand factors controlling the alignment and average separation of the NWs. First, we find that the degree of alignment can be controlled by the flow rate. With increasing flow rates, the width of the NW angular distribution with respect to the flow dhection (e.g., inset Fig. 31C) significantly narrows. Comparison of the distribution widths measured over a range of conditions shows that the width decreases quickly from our lowest flow rate, ¯ 4 mm/s, and approaches a nearly constant value at ¯ 10 mm/s (Fig. 31 C).

   At the highest flow rates examined in our studies, more than 80% of the NWs are aligned within +- 5 degrees of the flow direction (inset, Fig. 31C). Our observed results can be explained within the framework of shear flow. Specifically, the channel flow near the substrate surface resembles a shear flow and aligns the NWs in the flow direction before they are immobilized on the substrate. Higher flow rates produce larger shear forces, and hence lead to better alignment.
In addition, the average NW surface coverage can be controlled by the flow duration (Fig. 3 ID). Experiments carried out at constant flow rate show that the NW density increases systematically with flow duration. In these experiments, a flow duration of 30 min produced a density of ca. 250 NWs/lOO [mu]m or an average NW/NW separation of ¯400 nm.

   Extended deposition time can produce NW arrays with spacings on the order of 100 nm or less. We note that the deposition rate and hence average separation versus time depends strongly on the surface chemical functionality. Specifically, we have shown that the GaP, InP and Si NWs deposit more rapidly on animo-terminated monolayers, which possesses a partial positive charge, than on either methyl-terminated monolayers or bare SiO2surfaces. It is also important to recognize that the minimum separation of aligned NWs that can be achieved without NW-NW contacts will depend on the lengths of the NWs used in the assembly process.

   Recent progress demonstrating control of NW lengths from the 100 nanometer to tens of micrometer scale should increase the range of accessible spacings without contact.
Our results demonstrate ordering of NW structure over multiple length scalesorganization of nanometer diameter wires with 100 nm to micrometer scale separations over millimeter scale areas. This hierarchical order can readily bridge the microscopic and macroscopic worlds, although to enable assembly with greatest control requires that the spatial position also be defined. We have achieved this important goal by utilizing complementary chemical interactions between chemically patterned substrates and NWs (Fig. 32A). SEM images of representative experiments (Figs. 32B-32D) show parallel NW arrays with lateral periods the same as those of the surface patterns.

   These data demonstrate that the NWs are preferentially assembled at positions defined by the chemical pattern, and moreover, show that the periodic patterns can organize the NWs into a regular superstructure. It is important to recognize that the patterned surface alone does not provide good control of the ID nanostructure organization. Assembly of NTs and NWs on patterned substrates shows ID nanostructures aligned with, bridging, and looping around patterned areas with little directional control. Our use of fluid flows avoids these significant problems and enables controlled assembly in one or more directions.

   By combining this approach with other surface patterning methods, such as nanoscale domain formation in diblock copolymers and spontaneous ordering of molecules, it should be possible to generate well-ordered NW arrays beyond the limitations of conventional lithography.
Our general approach can be used to organize NWs into more complex crossed structures, which are critical for building dense nanodevice arrays,.using the layer-by-layer scheme illustrated in Fig. 3 IB. The formation of crossed and more complex structures requires that the nanostructure-substrate interaction is sufficiently strong that sequential flow steps do not affect preceding ones: we find that this condition can be achieved. For example, alternating the flow in orthogonal directions in a two-step assembly process yields crossbar structures (Fig 33 A and 33B).

   Both Figs, show that multiple crossbars can be obtained with only hundreds of nanometer separations between individual cross points in a very straightforward, low cost, fast and scalable process. Although the separations between individual NWs are not completely uniform, a periodic array can be easily envisioned using a patterned surface as described above. Significantly, these crossbar structures can yield functional devices (see below).
We believe that our approach for directed assembly of multiple crossed NW arrays offers significant advantages over current efforts, which have used random deposition, direct manipulation of individual NWs and NTs and electric fields to malce single crossed structures. With random deposition and manipulation it is difficult to obtain multiple crossbars required for integrated nanodevices.

   While electric fields enable more control over assembly, this method is also limited by (i) electrostatic interference between nearby electrodes as separations are scaled below the micrometer level and (ii) the requirement of extensive lithography to fabricate the electrodes for assembly of multiple NW device structures. Our fluidic approach is intrinsically very parallel and scalable, and moreover, it allows for the directed assembly of geometrically complex structures by simply controlling the angles between flow directions in sequential assembly steps. For example, an equilateral triangle (Fig. 33C) was assembled in a three-layer deposition sequence using 60[deg.] angles between the three flow directions.

   The method of flow alignment thus provides a flexible way to meet the requirements of many device configurations, including those requhing assembly of multiple 'layers' of NWs.
Electric fields can be used to align suspensions of semiconductor NWs into parallel NW arrays and single NW crosses, where patterned micro-electrode arrays are used to create a field pattern. Fringing fields and charging can, however, lead to significant complications in the assembly of multiple crosses at the submicron scale. An important feature of this layer-by-layer assembly scheme is that each layer is independent of the others, and thus a variety of homo- and hetero-junction configurations can be obtained at each crossed point by simply changing the composition of the NW suspension used for each step.

   For example, it should be possible to directly assemble and subsequently address individual nanoscale devices using our approach with n-type and ptype NWs and NTs, in which the NWs/NTs act as both the wiring and active device elements. A typical 2x2 crossbar array made of n-type InP NWs, in which all eight ends of the NWs are connected by metal electrodes, demonstrates this point (Fig 33D). Transport measurements (Fig. 33E) show that current can flow through any two of the eight ends, and enable the electrical characteristics of individual NWs and the NW-NW junctions to be assessed. The current- voltage (I-V) data recorded for each of the four cross points exhibit linear or nearly linear behavior (curves 200), and are consistent with expectations for n-n type junctions.

   Because single NW/NW p-n junctions formed by random deposition exhibit behavior characteristic of light-emitting diodes (LEDs), we believe it is apparent that our approach could be used to assemble high-density and individually addressable nanoLEDs and electronically more complex nanodevices.
These studies provide a general and rational approach for hierarchical assembly of ID nanomaterials into well-defined functional networks that can bridge the nanometer through millimeter size regimes. We have shown that NWs can be assembled into parallel arrays with control of the average separation, and by combining fluidic alignment with surface patterning techniques that it is also possible to control periodicity.

   In addition, we have demonstrated the possibility of layer-by-layer assembly of crossed and more complex structures by varying the flow direction in sequential steps, and have obtained preliminary results suggesting that this approach can be extended to ID nanostructures, such as carbon NTs. We believe that flow assembly represents a general strategy for organization of NW and NT building blocks into structures needed for wiring, interconnects and functional devices, and thus could enable a bottom-up manufacturing paradigm for future nanotechnologies. Additional studies show that suspensions of single- walled carbon nanotubes and duplex DNA can be aligned in parallel arrays using the fluidic approach.
Figs. 30A and 30B are schematics of fluidic channel structures for flow assembly. Fig. 30A shows a channel formed when the PDMS mold was brought in contact with a flat substrate.

   NW assembly was carried out by flowing aNW suspension inside the channel with a controlled flow rate for a set duration. Parallel arrays of NWs are observed in the flow direction on the substrate when the PDMS mold is removed. Fig. 3 OB illustrates that multiple crossed NW arrays can be obtained by changing the flow direction sequentially in a layer-by-layer assembly process.
Figs. 31A-31D illustrate parallel assembly of NW arrays. Figs. 31 A and 3 IB are SEM images of parallel arrays of InP NWs aligned in channel flow. The scale bars correspond to 2 [mu]m and 50 [mu]m in Figs. 31A and 3 IB, respectively. The silicon (SiO2/Si) substrate used in flow assembly was functionalized with an amino-terminated self assembled monolayer (SAM) by immersion in a lmM chloroform solution of 3aminopropyltriethoxy silane (APTES) for 30 min, followed by heating at 110 [deg.]C for 10 min.

   All of the substrates used in the following experiment were functionalized in a similar way unless otherwise specified. Fig. 31 C shows NW angular spread with respect to the flow direction vs. flow rate. Each data point in the Fig. was obtained by statistical analysis of angular distribution of ¯200 NWs (e.g., see inset). The inset shows histogram of NW angular distribution at a flow rate of 9.40 mm/s. Fig. 3 ID shows the average density of NW arrays vs. flow thne. The average density was calculated by dividing the average number of NWs at any cross section of the channel by the width of the channel. All of the experiments were carried out with a flow rate of 6.40 mm/s. Figs. 32A-32D illustrate assembly of periodic NW arrays. Fig. 32A is a schematic view of the assembly of NWs onto a chemically patterned substrate.

   The light gray areas correspond to amino-terminated surfaces, while the dark gray area corresponds to either methyl-terminated or bare surfaces. NWs are preferentially attracted to the aminoterminated regions of the surface. Figs. 32B and 32C show parallel arrays of GaP NWs aligned on poly(methylmethacrylate) (PMMA) patterned surface with 5 [mu]m and 2 [mu]m separation. The dark regions in the image correspond to residual PMMA, while the bright regions correspond to the amino-terminated SiO /Si surface. The NWs are preferentially attracted to amino-terminated regions. The PMMA was patterned with standard electron beam (E-beam) lithography, and the resulting SiO surface was functionalized by immersing in a solution of 0.5% APTES in ethanol for 10 min, followed by 10 min at 100 [deg.]C. The scale bars correspond to 5 [mu]m and 2 [mu]m in Figs. 32B and 32C, respectively.

   Fig. 32D shows parallel arrays of GaP NWs with 500 nm separation obtained using a patterned SAM surface. The SiO2/Si surface was first functionalized with methyl-terminated SAM by immersing in pure hexamethyldisilazane (IIMDS) for 15 min at 50 [deg.]C, followed by 10 min at 110 [deg.]C. This surface was patterned by E-beam lithography to form an array of parallel features with 500 nm period, followed by functionalization using APTES. The scale bar corresponds to 500 nm.
Figs. 33A-33E illustrate layer-by-layer assembly and transport measurements of crossed NW arrays. Figs. 33 A and 33B show typical SEM images of crossed arrays of InP NWs obtained in a two-step assembly process with orthogonal flow directions for the sequential steps. Flow directions are highlighted by arrows in the images.

   Fig. 33C shows an equilateral triangle of GaP NWs obtained in three-step assembly process, with 60[deg.] angles between flow directions, which are indicated by numbered arrows. The scale bars correspond to 500 nm in the three images. Fig. 33D shows an SEM image of a typical 2x2 cross array made by sequential assembly of n-type InP NWs using orthogonal flows. Ni/In/Au contact electrodes, which were deposited by thermal evaporation, were patterned by E-beam lithography. The NWs were briefly (3-5 s) etched in 6% HF solution to remove the amorphous oxide outer layer prior to electrode deposition. The scale bar corresponds to 2 [mu]m. Fig. 33E shows representative I-V curves from two-terminal measurements on a 2x2 crossed array.

   The curves 210 represent the I-V of four individual NWs (ad, bg, cf, eh), and the curves 200 represent I-V across the four n-n crossed junctions (ab, cd, ef, gh). We have demonstrated field effect transistors, pn junctions, light emission diodes, bipolar transistors, complementary inverters, tunnel diodes. We can make all the existing types of semiconductor devices using nanowires.

   The following are potential applications:
(I) Chemical and biological sensors (2) Memory and computing
(3) Photodetector and polarized light detector
(4) Indicating tag using the photoluminescence properties
(5) Single electron transistors
(6) Lasers (7) Photovoltaic solar cells
(8) Ultra-sharp tip for scanning probe microscopy and near-filed imaging
(9) Ultra-small electrodes for electrochemical and biological applications
(10) Interconnect wires for nanoelectronics and optoelectronics
(II) Temperature sensors (12) Pressure sensors
(13) Flow sensors
(14) Mass sensors
(15) Single photon emitters and detectors
(16) Ballistic transport and coherent transport for quantum computing (17) Spintronics devices
(18) Assembly of nanowires for 2D and 3D photonic bandgap materials
The following is a description of alternate techniques for assembling nanowires to form devices.

   Fluidics can be used to assemble nanowires. Nanowires (or any other elongated structures) can be aligned by inducing a flow of nanowire solution on surface, wherein the flow can be a channel flow or flow by any other ways.
Nanowire arrays with controlled position and periodicity can be produced by patterning the surface of the substrate and/or conditioning surface of the nanowires with different functionalities
Wherein the position and periodicity control is achieved by designing specific complementary forces (chemical or biological or electrostatic or magnetic or optical) between the patterned surface and wires, such as A wire goes to A' patterned area, B wire goes to B' patterned area, C wire goes to C patterned area, etc.
Wherein the surface of the substrate and/or nanowires can be conditioned with different molecules/materials, or different charges,

   different magnetos or different light intensities (eg. by interference/diffraction patterns from light beams.) or a combination of these.
As-assembled nanowhe arrays could also be transferred to another substrate. ( e.g. by stamping )
Nanowires can be assembled by complementary interaction. Flow is used for assembly of nanowires in the above methods, although it is not limited to flow only.
Complementary chemical, biological, electrostatic, magnetic or optical interactions alone can also be exploited for nanowire assembly (although with less control).
Nanowires can be assembled using physical patterns. Deposit nanowire solution onto substrate with physical patterns, such as surface steps, trenches, etc.

   Nanowires can be aligned along the corner of the surface steps or along the trenches.
Physical patterns can be formed by the natural crystal lattice steps or selfassembled diblock copolymer stripes, or imprinted patterns or any other patterns Nanowhes may be assembled by electrostatic or magnetic force between nanowires. By introducing charge onto nanowire surface, electrostatic forces between nanowires can align them into certain patterns, such as parallel arrays.
Nanowires can be assembled using a LB film. Nanowires were first surface conditioned and dispersed to the surface of a liquid phase to form a Langmuir-Blodgett (LB) film. Nanowhes can then be aligned into different patterns ( such as parallel arrays) by compressing the surface.

   Then the nanowire patterns can be transferred onto deshed substrate.
Nanowires can be assembled by shear stretching by dispersing nanowires in a flexible matrix (which could be polymers), followed by sfretching the matrix in one direction, nanowires can be aligned in the stretching dhection by the shear force induced. The matrix can then be removed and the aligned nanowire arrays can be transferred to deshed substrate. Wherein the stretching of the matrix can be induced by mechanical, electrical optical, magnetic force. And the stretching direction could be either in the plane of the substrate or not.
Having now described some illustrative embodiments of the invention claimed below, it should be apparent to those skilled in the art that the foregoing is merely illustrative and not limiting, having been presented by way of example only.

   Numerous modification and other illustrative embodiments are within the scope of one of ordinary skill in the art and are contemplated as falling within the scope of the claims set forth below. In particular, although many of the examples presented herein involve specific combinations of method acts or system elements, it should be understood that those acts and those elements may be combined in other ways to accomplish the same objectives. Acts, elements and features discussed only in connection with one embodiment of a system or method are not intended to be excluded from a similar role in other embodiments.

   Further, for the one or more means-plus-function limitations recited in the following claims, the means are not intended to be limited to the means disclosed herein for performing the recited function, but are intended to cover in scope any equivalent means, known now or later developed, for performing the recited function. What is claimed is:

Claims

- 92 -
CLAIMS 1. A free-standing and bulk-doped semiconductor comprising at least one portion having a smallest width of less than 500 nanometers.
2. The semiconductor of claim 1, wherein the semiconductor comprises: an interior core comprising a first semiconductor; and one or more exterior shells exterior to the interior core, at least one ofthe exterior shells comprising a different material than the first semiconductor.
3. The semiconductor of claim 1, wherein the semiconductor comprises an elemental semiconductor.
4. The semiconductor of claim 3, wherein the elemental semiconductor is selected from a group consisting of: Si, Ge, Sn, Se, Te, B, Diamond and P.
5. The semiconductor of claim 1, wherein the semiconductor comprises a solid solution of elemental semiconductors.
6. The semiconductor of claim 5, wherein the solid solution is selected from a group consisting of: B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn.
7. The semiconductor of claim 1, wherein the semiconductor comprises a Group IV- Group IV semiconductor.
8. The semiconductor of claim 7, wherein the Group IV-Group IN semiconductor is
SiC.
9. The semiconductor of claim 1, wherein the semiconductor comprises a Group Ill-
Group N semiconductor.
10. The semiconductor of claim 9, wherein the Group Ill-Group V semiconductor is selected from a group consisting of: BΝ/BP/BAs, AlΝ/AlP/AlAs/AlSb, - 93 - GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb.
11. The semiconductor of claim 1 , wherein the semiconductor comprises an alloy comprising a combination of two or more Group Ill-Group V semiconductors from a group consisting of: BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb.
12. The semiconductor of claim 1, wherein the semiconductor comprises a Group II- Group VI semiconductor.
13. The semiconductor of claim 12, wherein the semiconductor is selected from a group consisting of: ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe.
14. The semiconductor of claim 1, wherein the semiconductor comprises an alloy comprising a combination of two or more Group II-Group VI semiconductors from a group consisting of: ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe,
BeS/BeSe/BeTe/MgS/MgSe.
15. The semiconductor of claim 1, wherein the semiconductor comprises an alloy comprising a combination of a Group II-Group VI semiconductors from a group consisting of: ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe and a Group Ill-Group V semiconductors from a group consisting of: BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb.
16. The semiconductor of claim 1, wherein the semiconductor comprises a Group IV- Group VI semiconductor.
17. The semiconductor of claim 16, wherein the semiconductor is selected from a group consisting of: GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe - 94 -
18. The semiconductor of claim 1 , wherein the semiconductor comprises a Group I- Group VII semiconductor.
19. The semiconductor of claim 18, wherein the semiconductor is selected from a group consisting of: CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl.
20. The semiconductor of claim 1 , wherein the semiconductor comprises a semiconductor selected from a group consisting of: BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, TI, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3 and A12CO.
21. The semiconductor of claim 1 , wherein the semiconductor comprises a p-type dopant.
22. The semiconductor of claim 1 , wherein the semiconductor comprises an n-type dopant from.
23. The semiconductor of claim 1, wherein the semiconductor comprises a p-type dopant from Group III ofthe periodic table.
24. The semiconductor of claim 1, wherein the semiconductor comprises an n-type dopant from Group V ofthe periodic table.
25. The semiconductor of claim 1 , wherein the semiconductor comprises a p-type dopant selected from a group consisting of: B, Al and In.
26. The semiconductor of claim 1 , wherein the semiconductor comprises an n-type dopant selected from a group consisting of: P, As and Sb.
27. The semiconductor of claim 1, wherein the semiconductor comprises a p-type dopant from Group II ofthe periodic table. - 95 -
28. The semiconductor of claim 27, wherein the p-type dopant is selected from a group consisting of: Mg, Zn, Cd and Hg.
29. The semiconductor of claim 1, wherein the semiconductor comprises a p-type dopant from Group IV ofthe periodic table.
30. The semiconductor of claim 29, wherein the p-type dopant is selected from a group consisting of: C and Si.
31. The semiconductor of claim 27, wherein the n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
32. The semiconductor of claim 1 , wherein the smallest width is less than 200 nanometers.
33. The semiconductor of claim 1 , wherein the smallest width is less than 150 nanometers.
34. The semiconductor of claim 1 , wherein the smallest width is less than 100 nanometers.
35. The semiconductor of claim 1, wherein the smallest width is less than 80 nanometers.
36. The semiconductor of claim 1 , wherein the smallest width is less than 70 nanometers.
37. The semiconductor of claim 1 , wherein the smallest width is less than 60 nanometers.
38. The semiconductor of claim 1, wherein the smallest width is less than 40 nanometers. - 96 -
39. The semiconductor of claim 1, wherein the smallest width is less than 20 nanometers.
40. The semiconductor of claim 1, wherein the smallest width is less than 10 nanometers
41. The semiconductor of claim 1 , wherein the smallest width is less than 5 nanometers
42. The semiconductor of claim 1, wherein the semiconductor is elongated, and the at least one portion is a longitudinal section.
43. The semiconductor of claim 42, wherein the longitudinal section, a ratio ofthe length ofthe section to a longest width is greater than 4: 1.
44. The semiconductor of claim 42, wherein the longitudinal section, a ratio ofthe length ofthe section to a longest width is greater than 10:1.
45. The semiconductor of claim 42, wherein the longitudinal section, a ratio ofthe length ofthe section to a longest width is greater than 100: 1.
46. The semiconductor of claim 42, wherein the longitudinal section, a ratio ofthe length ofthe section to a longest width is greater than 1000:1.
47. The semiconductor of claim 1, wherein the semiconductor comprises a single crystal.
48. The semiconductor of claim 1 , wherein the semiconductor is part of a device.
49. The semiconductor of claim 1 , wherein the semiconductor is n-doped.
50. The semiconductor of claim 1 , wherein the semiconductor is p-doped. - 97 -
51. The semiconductor of claim 1 , wherein the semiconductor is magnetic.
52. The semiconductor of claim 51 , wherein the semiconductor comprises a dopant making the semiconductor magnetic.
5
53. The semiconductor of claim 51 , wherein the semiconductor is ferromagnetic.
54. The semiconductor of claim 53, wherein the semiconductor comprises a dopant that makes the semiconductor ferromagnetic.
70
55. The semiconductor of claim 54, wherein the semiconductor comprises manganese.
56. An elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers.
75
57. The semiconductor of claim 56, wherein the semiconductor comprises: an interior core comprising a first semiconductor; and one or more exterior shells exterior to the interior core, at least one ofthe exterior shells comprising a different material than the first semiconductor. 20
58. The semiconductor of claim 56, wherein, at any point along the longitudinal axis ofthe semiconductor, a ratio ofthe length ofthe section to a longest width is greater than 4:1.
25 59. The semiconductor of claim 56, wherein, at any point along the longitudinal axis ofthe semiconductor, a ratio ofthe length ofthe section to a longest width is greater than 10:1.
60. The semiconductor of claim 56, wherein, at any point along the longitudinal axis 30 ofthe semiconductor, a ratio of the length ofthe section to a longest width is greater than 100:1 - 98 -
61. The semiconductor of claim 56, wherein, at any point along the longitudinal axis ofthe semiconductor, a ratio ofthe length ofthe section to a longest width is greater than 1000:1
62. The semiconductor of claim 56, wherein the point has a smallest width less than 200 nanometers.
63. The semiconductor of claim 56, wherein the point has a smallest width less than 150 nanometers.
64. The semiconductor of claim 56, wherein the point has a smallest width less than 100 nanometers.
65. The semiconductor of claim 56, wherein the point has a smallest width less than 80 nanometers.
66. The semiconductor of claim 56, wherem the point has a smallest width less than 70 nanometers.
67. The semiconductor of claim 56, wherein the point has a smallest width less than 60 nanometers.
68. The semiconductor of claim 56, wherein the point has a smallest width less than 40 nanometers.
69. The semiconductor of claim 56, wherein the point has a smallest width less than 20 nanometers.
70. The semiconductor of claim 56, wherein the point has a smallest width less than 10 nanometers. - 99 -
71. The semiconductor of claim 56, wherein the point has a smallest width less than 5 nanometers.
72. The semiconductor of claim 56, wherein the semiconductor comprises a single crystal.
73. The semiconductor of claim 56, wherein the semiconductor is free-standing.
74. The semiconductor of claim 56, wherein the semiconductor is part of a device.
75. The semiconductor of claim 56, wherein the semiconductor is n-doped.
76. The semiconductor of claim 56, wherein the semiconductor is p-doped.
77. A doped semiconductor comprising a single crystal.
78. The semiconductor of claim 77, wherein the semiconductor comprises: an interior core comprising a first semiconductor; and one or more exterior shells exterior to the interior core, at least one ofthe exterior shells comprising a different material than the first semiconductor.
79. The semiconductor of claim 77, wherein the semiconductor is bulk-doped.
80. The semiconductor of claim 77, wherein the semiconductor is free-standing.
81. The semiconductor of claim 77, wherein the semiconductor comprises a portion having a width of less than 500 nanometers.
82. The semiconductor of claim 77, wherein the semiconductor is elongated.
83. The semiconductor of claim 77, wherein the semiconductor is part of a device. - 100 -
84. The semiconductor of claim 77, wherein the semiconductor is n-doped.
85. The semiconductor of claim 77, wherein the semiconductor is p-doped.
86. A doped semiconductor that was doped during growth ofthe semiconductor.
87. The semiconductor of claim 86, wherein the doped semiconductor was grown by applying energy to one or more molecules ofthe semiconductor and one or more molecules of a dopant.
88. The semiconductor of claim 86, wherein the doped semiconductor was grown by applying energy to one or more molecules ofthe semiconductor and one or more molecules of a dopant.
89. The semiconductor of claim 86, wherein the doped semiconductor was grown by applying energy to one or more molecules ofthe semiconductor and one or more molecules of a dopant.
90. The semiconductor of claim 86, wherein the semiconductor is bulk-doped.
91. The semiconductor of claim 86, wherein the semiconductor comprises a single crystal.
92. The semiconductor of claim 86, wherein the semiconductor is free-standing.
93. The semiconductor of claim 86, wherein the semiconductor comprises a portion having a width of less than 500 nanometers.
94. The semiconductor of claim 86, wherein the semiconductor is elongated.
95. The semiconductor of claim 86, wherein the semiconductor is n-doped. - 101 -
96. The semiconductor of claim 86, wherein the semiconductor is p-doped.
97. A bulk-doped semiconductor that is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, wherein a phenomena produced by a section ofthe bulk-doped semiconductor exhibits a quantum confinement caused by a dimension ofthe section.
98. The semiconductor of claim 97, wherein the semiconductor is elongated and the dimension is a width at any point along a longitudinal section ofthe semiconductor.
99. The semiconductor of claim 98, wherein the longitudinal section is capable of transporting electrical carriers without scattering.
100. The semiconductor of claim 99, wherein the longitudinal section is capable of transporting electrical carriers such that the electrical carriers pass through the longitudinal section ballistically.
101. The semiconductor of claim 99, wherein the longitudinal section is capable of transporting electrical carriers such that the electrical carriers pass through the longitudinal section coherently.
102. The semiconductor of claim 98, wherein the longitudinal section is capable of transporting electrical carriers such that the electrical carriers are spin-polarized.
103. The semiconductor of claim 102, wherein the longitudinal section is capable of transporting electrical carriers such that the spin-polarized electrical carriers pass through the longitudinal section without losing spin information.
104. The semiconductor of claim 98, wherein the longitudinal section is capable of emitting light in response to excitation, wherein a wavelength ofthe emitted light is - 102 - related to the width.
105. The semiconductor of claim 99, wherein the wavelength of the emitted light is proportional to the width.
106. A bulk-doped semiconductor that exhibits coherent transport.
107. A bulk-doped semiconductor that exhibits ballistic transport.
108. A bulk-doped semiconductor that exhibits Luttinger liquid behavior.
109. A solution comprising one or more doped semiconductors, wherein at least one of the semiconductors is at least one ofthe following: a single crystal, an elongated and bulk- doped semiconductor that, at any point along its longitudinal axis, has a largest cross- sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
110. A device comprising at least one doped semiconductor, wherein the at least one doped semiconductor is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross- sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
111. The device of claim 110, wherein the device comprises at least two doped semiconductors, wherein both ofthe at least two doped semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein a first ofthe at least two doped semiconductors exhibits quantum confinement and a second o the at least two - 103 - doped semiconductor manipulates the quantum confinement ofthe first.
112. The device of claim 110, wherein the device comprises at least two doped semiconductor, wherein both ofthe at least two doped semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
113. The device of claim 111, wherein the at least two bulk-doped semiconductors are in physical contact with each other.
114. The device of claim 113, wherein a first of the at least two bulk-doped semiconductors is of a first conductivity type, and a second ofthe at least two bulk-doped semiconductors is of a second conductivity type.
115. The device of claim 114, wherein the first conductivity type is n-type, and the second type of conductivity type is p-type.
116. The device of claim 115, wherein the at least two bulk-doped semiconductors form a p-n junction.
117. The device of claim 110, wherein the at least one semiconductor is free-standing.
118. The device of claim 110, wherein the at least one semiconductor is elongated.
119. The device of claim 110, wherein the at least one semiconductor comprises a single crystal.
120. The device of claim 110, wherein the at least one semiconductor comprises: an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. - 104 -
121. The device of claim 110, wherein the device comprises a switch.
122. The device of claim 110, wherein the device comprises a diode.
123. The device of claim 110, wherein the device comprises a Light-Emitting Diode.
124. The device of claim 110, wherein the device comprises a tunnel diode.
125. The device of claim 110, wherein the device comprises a Schottky diode.
126. The device of claim 125, wherein the transistor comprises a Bipolar Junction Transistor.
127. The device of claim 125, wherein the transistor comprises a Field Effect Transistor.
128. The device of claim 110, wherein the device comprises an inverter.
129. The device of claim 128, wherein the inverter is a complimentary inverter.
130. The device of claim 110, wherein the device comprises an optical sensor.
131. The device of claim 110, wherein the device comprises a sensor for an analyte.
132. The device of claim 110, wherein the analyte is a DNA.
133. The device of claim 110, wherein the device comprises a memory device.
134. The device of claim 133, wherein the memory device is a dynamic memory device.
135. The device of claim 133, wherein the memory device is a static memory device. - 105 -
136. The device of claim 110, wherein the device comprises a laser.
137. The device of claim 110, wherein the device comprises a logic gate.
138. The device of claim 137, wherem the logic gate is an AND gate.
139. The device of claim 137, wherein the logic gate is a NAND gate.
140. The device of claim 137, wherein the logic gate is an EXCLUSIVE-AND gate.
141. The device of claim 137, wherein the logic gate is a OR gate.
142. The device of claim 137, wherein the logic gate is aNOR gate.
143. The device of claim 137, wherein the logic gate is an EXCLUSIVE-OR gate.
144. The device of claim 110, wherein the device comprises a latch.
145. The device of claim 110, wherein the device comprises a register.
146. The device of claim 110, wherein the device comprises clock circuitry.
147. The device of claim 110, wherein the device comprises a logic array.
148. The device of claim 110, wherein the device comprises a state machine.
149. The device of claim 110, wherein the device comprises a programmable circuit.
150. The device of claim 110, wherein the device comprises an amplifier.
151. The device of claim 110, wherein the device comprises a transformer. - 106 -
152. The device of claim 110, wherein the device comprises a signal processor.
153. The device of claim 110, wherein the device comprises a digital circuit.
154. The device of claim 110, wherein the device comprises an analog circuit.
155. The device of claim 110, wherein the device comprises a light emission source.
156. The device of claim 155, wherein the light emission source emits light at a higher frequency than would the semiconductor if the semiconductor had a shortest width greater than the shortest width at any portion ofthe semiconductor.
157. The device of claim 110, wherein the device comprises a photoluminescent device.
158. The device of claim 110, wherein the device comprises an electroluminescent device.
159. The device of claim 110, wherein the device comprises a rectifier.
160. The device of claim 110, wherein the device comprises a photodiode.
161. The device of claim 110, wherein the device comprises a p-n solar cell.
162. The device of claim 110, wherein the device comprises a phototransistor.
163. The device of claim 110, wherein the device comprises a single-electron transistor.
164. The device of claim 110, wherein the device comprises a single photon emitter.
165. The device of claim 110, wherein the device comprises a single photon detector.
166. The device of claim 110, wherein the device comprises a spintronic device. - 107 -
167. The device of claim 110, wherein the device comprises an ultra-shaφ tip for atomic force microscope.
168. The device of claim 110, wherein the device comprises a scanning tunneling microscope.
169. The device of claim, wherein the device comprises a field emission device
170. The device of claim, wherein the device comprises a photoluminescence tag
171. The device of claim, wherein the device comprises a photovoltaic device
172. The device of claim, wherein the device comprises photonic band gap materials
173. The device of claim 110, wherein the device comprises a scanning near field optical microscope tips.
174. The device of claim 110, wherein the device comprises a circuit that has digital and analog components.
175. The device of claim 110, wherein the device comprises another semiconductor that is electrically coupled to the at least one bulk-doped semiconductor.
176. The device of claim 175, wherein the other semiconductor is a bulk-doped semiconductor comprising at least one portion having a smallest width of less than 500 nanometers.
177. The device of claim 110, wherein the device comprises another semiconductor that is optically coupled to the at least one bulk-doped semiconductor.
178. The device of claim 177, wherein the other semiconductor is a bulk-doped semiconductor comprising at least one portion having a smallest width of less than 500 - 108 - nanometers.
179. The device of claim 110, wherein the device comprises another semiconductor that is magnetically coupled to the at least one bulk-doped semiconductor.
180. The device of claim 179, wherein the other semiconductor is a bulk-doped semiconductor comprising at least one portion having a smallest width of less than 500 nanometers.
181. The device of claim 110, wherein the device comprises another semiconductor that physically contacts the at least one bulk-doped semiconductor.
182. The device of claim 179, wherein the other semiconductor is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
183. The device of claim 110, wherein the at least one semiconductor is coupled to an electrical contact.
184. The device of claim 110, wherein the at least one semiconductor is coupled to an optical contact.
185. The device of claim 110, wherein the at least one semiconductor is coupled to a magnetic contact.
186. The device of claim 110, wherein a conductivity of the at least one semiconductor is controllable in response to a signal.
187. The device of claim 186, wherein the conductivity of the at least one semiconductor is controllable to have any value within a range of values. - 109 -
188. The device of claim 186, wherein the at least one semiconductor is switchable between two or more states.
189. The device of claim 188, wherein the at least one semiconductor is switchable between a conducting state and an insulating state by the signal.
190. The device of claim 188, wherein two or more states ofthe at least one semiconductor are maintainable without an applied signal.
191. The device of claim 186, wherein the conductivity of the at least one semiconductor is controllable in response to an electrical signal.
192. The device of claim 186, wherein the conductivity of the at least one semiconductor is controllable in response to an optical signal.
193. The device of claim 186, wherein the conductivity of the at least one semiconductor is controllable in response to a magnetic signal.
194. A device of claim 186, wherein the conductivity ofthe at least one semiconductor is controllable in response to a signal of a gate terminal.
195. The device of claim 194, wherein the gate terminal is not in physical contact with the at least one semiconductor.
196. The device of claim 110, wherein at least two of the semiconductors form an array, and at least one ofthe semiconductors in the array is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
197. The device of claim 196, wherein the array is an ordered array. - 110 -
198. The device of claim 196, wherein said array is not an ordered array.
199. The device of claim 110, wherein the device comprises two or more separate and interconnected circuits, at least one ofthe circuits not comprising a doped semiconductor that is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
200. The device of claim 110, wherein the device is embodied on a chip having one or more pinouts
201. The device of claim 200, wherein the chip comprises separate and interconnected circuits, at least one ofthe circuits not comprising a doped semiconductor that is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
202. A collection of reagents for growing a doped semiconductor that will be at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers that comprises at least one portion having a smallest width of less than 500 nanometers, wherein the collection comprises a semiconductor reagent and a dopant reagent.
203. A method of growing a semiconductor, the method comprising an act of: (A) doping the semiconductor during growth ofthe semiconductor.
204. The method of claim 203, wherein the grown semiconductor is a doped semiconductor that is at least one ofthe following: a single crystal, an elongated and bulk- doped semiconductor that, at any point along its longitudinal axis, has a largest cross- - Ill - sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
205. The method of claim 203, further comprising an act of:
(B) adding one or more other materials to a surface ofthe doped semiconductor.
206. The method of claim 205, wherein act (B) comprises forming a shell around the doped semiconductor.
207. The method of claim 203, wherein act (A) comprises: controlling an extent ofthe doping.
208. The method of claim 203, wherein act (A) comprises growing the doped semiconductor by applying energy to a collection of molecules, the collection of molecules comprising molecules ofthe semiconductor and molecules of a dopant.
209. The method of claim 208, wherein act (A) comprises an act of: controlling an extent ofthe doping.
210. The method of claim 209, wherein the act of controlling doping comprises controlling a ratio of an amount ofthe semiconductor molecules to an amount ofthe dopant molecules.
211. The method of claim 209, wherein act (A) further comprises: vaporizing the molecules using a laser to form vaporized molecules.
212. The method of claim 211, wherein act (A) further comprises : growing the semiconductor from the vaporized molecules. - 112 -
213. The method of claim 211, wherein act (A) further comprises: condensing the vaporized molecules into a liquid cluster.
214. The method of claim 212, wherein act (A) further comprises : growing the semiconductor from the liquid cluster.
215. The method of claim 211, wherein act (A) is performed using laser-assisted catalytic growth.
216. The method of claim 208, wherein the collection of molecules comprises a cluster of molecules of a catalyst material.
217. The method of claim 216, wherein act (A) comprises: controlling a width ofthe semiconductor.
218. The method of claim 217, wherein controlling the width of the semiconductor comprises: controlling a width ofthe catalyst cluster.
219. The method of claim 203 , wherein act (A) further comprises: performing chemical vapor deposition on at least the molecules.
220. The method of claim 203, wherein the grown semiconductor has at least one portion having a smallest width of less than 20 nanometers.
221. The method of claim 220, wherein the grown semiconductor has at least one portion having a smallest width of less than 10 nanometers.
222. The method of claim 220, wherein the grown semiconductor has at least one portion having a smallest width of less than 5 nanometers.
223. The method of claim 203 , wherein the grown semiconductor is magnetic.
- 113 - 224. The method of claim 223, wherein act (A) comprises: doping the semiconductor with a material that makes the grown semiconductor magnetic.
225. The method of claim 203, wherein the grown semiconductor is ferromagnetic.
226. The method of claim 225, act (A) comprises: doping the semiconductor with a material that makes the grown semiconductor ferromagnetic.
227. The method of claim 226, wherein act (A) comprises: doping the semiconductor with manganese.
228. A method of fabricating a device, comprising an act of: (A) contacting one or more semiconductors to a surface, wherein at least one ofthe semiconductors is at least one ofthe following: a single crystal, an elongated and bulk- doped semiconductor that, at any point along its longitudinal axis, has a largest cross- sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
229. The method of claim 228, wherein the surface is a substrate.
230. The method of claim 228, further comprising an act of: (B) prior to act (A), growing at least one ofthe semiconductors by applying energy to molecules of a semiconductor and molecules of a dopant.
231. The method of claim 228, wherein act (A) comprises: contacting a solution comprising the one or more semiconductors to the surface.
232. The method of claim 231 , further comprising:
(B) aligning one or more ofthe semiconductors on the surface using an electric - 114 - field.
233. The method of claim 232, wherein act (B) comprises: generating an electric field between at least two electrodes; and positioning one or more ofthe semiconductors between the electrodes.
234. The method of claim 231 , further comprising an act of:
(B) repeating act (A) with another solution comprising one or more other semiconductors, wherein at least one ofthe other semiconductor is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
235. The method of claim 228, further comprising an act of:
(B) conditioning the surface to attach the one or more contacted semiconductors to the surface.
236. The method of claim 235, wherein act (B) comprises: forming channels on the surface.
237. The method of claim 235, wherein act (B) comprises: patterning the surface.
238. The method of claim 228, further comprising:
(B) aligning one or more ofthe semiconductors on the surface using an electric field.
239. The method of claim 238, wherein act (B) comprises: generating an electric field between at least two electrodes; and positioning one or more ofthe semiconductors between the electrodes. - 115 -
240. A method of generating light, comprising an act of:
(A) applying energy to one or more semiconductors causing the one or more semiconductors to emit light, wherein at least one ofthe semiconductors is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
241. The method of claim 240, wherein the semiconductor comprises a direct-band-gap semiconductor.
242. The method of claim 240, wherein act (A) comprises applying a voltage across a junction of two crossed semiconductors, each semiconductor having a smallest width of less than 500 nanometers.
243. The method of claim 242, wherein each semiconductor has a smallest width of less than 100 nanometers
244. The method of claim 240, further comprising an act of: (B) controlling a wavelength ofthe emitted light by controlling a dimension of the at least one semiconductor having a smallest width of less than 100 nanometers.
245. The method of claim 244, wherein the semiconductor is elongated, and act (B) comprises: controlling a width ofthe elongated semiconductor.
246. The method of claim 244, wherein: the semiconductor has a property that a mass ofthe semiconductor emits light at a first wavelength if the mass has a minimum shortest dimension, and the controlled dimension ofthe semiconductor is less than the minimum shortest dimension. - 116 -
247. A method of fabricating a device having a doped semiconductor component and one or more other components, the method comprising acts of:
(A) doping a semiconductor during its growth to produce the doped semiconductor component; and (B) attaching the doped semiconductor component to at least one ofthe one or more other components.
248. The method of claim 247, wherein the doped semiconductor component is at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
249.
250. A process for controllably assembling a semiconductor device having elongated elements with a characteristic dimension in a transverse direction ofthe element on a nanometer scale, comprising: producing at least one first elements of a first doping type, orienting said first element in a first direction, and connecting said first element to at least one first contact to allow an electrical current to flow through the first element.
251. The process of claim 250, further comprising: producing at least one second element of a second doping type, orienting said second element in a second direction different from the first direction, enabling an electrical contact between the first element and the second element, and connecting said second element to at least one second contact to allow an electrical current to flow between the first and second element.
252. The process of claim 251 , wherein the second doping type is n-type if the first doping type is p-type, and p-type if the first doping type is n-type. - 117 -
253. The process of claim 251 , wherein the second element is oriented by applying at least one of an electric field or a fluid flow.
254. The process of claim 250, further comprising: connecting said first element to spaced-apart contacts and arranging a gate electrode proximate to the first element between the spaced-apart contacts, thereby forming an FET.
255. The process of claim 250, wherein the semiconductor device is made of a material selected from the group consisting of Si, Ge, Sn, Se, Te, B, Diamond, P, B-C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, TI, Fe)(S, Se, Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, and A12CO.
256. The process of claim 250, wherein the first doping type is one of n-type or p-type.
257. The process of claim 250, wherein the first element is oriented by applying at least one of an electric field or a fluid flow.
258. The process of claim 257, wherein the first element is suspended in the fluid flow.
259. The process of claim 250, wherein the first element is oriented by applying a mechanical tool.
260. The process of claim 250, wherein the second element is suspended in the fluid flow.
261. The process of claim 250, wherein the second element is oriented by applying a mechanical tool. - 118 -
262. A semiconductor device, comprising a silicon substrate having an array of metal contacts a crossbar switch element formed in electrical communication with the array and having a first bar formed of a p-type semiconductor nanowire, and a second bar formed of an n-type semiconductor nanowire and being spaced away from the first bar and being disposed transversely thereto.
263. A semi device of claim 262, wherein the second bar is spaces between 1-10 nm from the first bar.
264. A method for manufacturing a nanowire semiconductor device comprising positioning a first nanowire between two contact points by applying a potential between the contact points; positioning a second nanowire between two other contact points.
265. A method for manufacturing a nanowire semiconductor device comprising formmg a surface with one or more regions that selectively attract nanowires.
266. A method for manufacturing a light-emitting diode from nanowires, the diode having an emission wavelength determined by a dimension of a p-n junction between two doped nanowires.
267. A method for manufacturing a semiconductor junction by crossing a p-type nanowire and an n-type nanowire.
268. A method of assembling one or more elongated structures on a surface, the method comprising acts of:
(A) flowing a fluid that comprises the one or more elongated structures onto the surface; and
(B) aligning the one or more elongated structures on the surface to form an array of the elongated structures.
269. The method of claim 268, wherein act (A) comprises flowing the fluid in a first direction and act (B) comprises aligning the one or more elongated stractures as the fluid - 119 - flows in the first direction to form a first layer of arrayed structures, and wherein the method further comprises:
(C) changing a direction ofthe flow from the first direction to a second direction; and (D) repeating acts (A) and (B) in the second direction to form a second layer of arrayed structures.
270. The method of claim 269, comprising repeating acts (C)and (D) one or more times.
271. The method of claim 269, wherein at least a first elongated structure from the first layer contacts at least a second elongated structure from the second array.
272. The method of claim 271, wherein one ofthe first and second elongated stractures is doped semiconductor of a first conductivity type and another of first and second elongated structures is doped semiconductor of a second conductivity type.
273. The method of claim 272, wherein the first conductivity type is p-type and the second conductivity type is n-type, and wherein the first and second elongated structures form a p-n junction.
274. The method of claim 268; wherein the surface is a surface of a substrate.
275. The method of claim 274, wherein the method further comprises:
(C) transferring the array of elongated structures from the surface ofthe substrate to a surface of another substrate.
276. The method of claim 275, wherein act (C) comprises stamping.
277. The method of claim 268, wherein the one or more elongated structured are aligned onto the surface while still comprised in the fluid.
278. The method of claim 268, wherein the method further comprises:
(C) conditioning the surface with one or more functionalities that attract the one or - 120 - more elongated structures to particular positions on the surface, wherein act (B) comprises attracting the one or more elongated stractures to the particular positions using the one or more functionalities.
279. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more molecules..
280. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more charges.
281. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more magnetos.
282. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more light intensities.
283. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using chemical force.
284. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated stractures to particular positions on the surface using optical force.
285. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated stractures to particular positions on the surface using electrostatic force.
286. The method of claim 278, wherein act (C) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated stractures to particular positions on the surface using magnetic force. - 121 -
287. The method of claim 268, wherein the method further comprises:
(C) patterning the surface to receive the one or more elongated stractures at particular positions on the surface.
288. The method of claim 287, wherein act (C) comprises: creating physical patterns on the surface.
289. The method of claim 288, wherein the physical patterns are trenches.
290. The method of claim 288, wherein the physical patterns are steps.
291. The method of claim 288, wherein the surface is a surface of a substrate, and wherein creating physical patterns on the surface comprises: using crystal lattice steps ofthe substrate.
292. The method of claim 288, wherein the surface is a surface of a substrate, and wherein creating physical patterns on the surface comprises: using self-assembled di-block polymer strips.
293. The method of claim 288, wherein creating physical patterns on the surface comprises: using patterns.
294. The method of claim 293, wherein creating physical patterns on the surface comprises: using imprinted patterns.
295. The method of claim 268, wherein act (A) comprises controlling the flow ofthe fluid using a channel.
296. The method of claim 268, wherein at least one ofthe elongated structures are semiconductors. - 122 -
297. The method of claim 268, wherein at least one ofthe elongated structures are doped semiconductors.
298. The method of claim 297, wherein at least one ofthe elongated structures are bulk- doped semiconductors.
299. The method of claim 268, wherein at least one ofthe structures is a doped single- crystal semiconductor.
300. The method of claim 268, wherein at least one ofthe structures is an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross- sectional dimension less than 500 nanometers.
301. The method of claim 268, wherein at least one ofthe stractures is a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
302. The method of claim 268, wherein at least one ofthe structures is a doped semiconductor that is at least one ofthe following: a single crystal, an elongated and bulk- doped semiconductor that, at any point along its longitudinal axis, has a largest cross- sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers.
303. The method of claim 302, wherein the doped semiconductor comprises a semiconductor selected from a group consisting of: Si, Ge, Sn, Se, Te, B, Diamond, P, B- C, B-P(BP6), B-Si, Si-C, Si-Ge, Si-Sn and Ge-Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag)(Al, Ga, In, TI, Fe)(S, Se, - 123 - Te)2, Si3N4, Ge3N4, A12O3, (Al, Ga, In)2(S, Se, Te)3, A12CO.
304. The method of claim 302, wherein the doped semiconductor comprises a dopant selected from a group consisting of:: a p-type dopant from Group III ofthe periodic table; an n-type dopant from Group V ofthe periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II ofthe periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV ofthe periodic table; a p-type dopant selected from a group consisting of: C and Si.; and an n- type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
305. The method of claim 302, wherein the doped semiconductor is doped during growth ofthe semiconductor.
306. A method of assembling one or more elongated stractures on a surface, wherein one or more ofthe elongated structures are at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of:
(A) conditioning the surface with one or more functionalities that attract the one or more elongated stractures to particular positions on the surface, and
(B) aligning the one or more elongated structures by attracting the one or more elongated structures to the particular positions using the one or more functionalities.
307. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more molecules..
308. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more charges. - 124 -
309. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more magnetos.
310. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more light intensities.
311. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated stractures to particular positions on the surface using chemical force.
312. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using optical force.
313. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using electrostatic force.
314. The method of claim 306, wherein act (A) comprises: conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface using magnetic force.
315. A method of assembling a plurality of elongated stractures on a surface, wherein one or more ofthe elongated structures are at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of:
(A) depositing the plurality of elongated structures onto the surface; and (B) electrically charging the surface to produce electrostatic forces between two or more ofthe plurality ofthe elongated stractures. - 125 -
316. The method of claim 315, wherein the electrostatic forces cause the two or more elongated structures to align themselves.
317. The method of claim 316, wherein the electrostatic forces cause the two or more elongated structures to align themselves into one or more patterns.
318. The method of claim 317, wherein the one or more patterns comprise a parallel array.
319. A method of assembling a plurality of elongated structures on a surface, wherein one or more ofthe elongated stractures are at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of:
(A) dispersing the one or more elongated structures on a surface of a liquid phase to form a Langmuir-Blodgett film;
(B) compressing the Langmuir-Blodgett film; and
(C) transferring the compressed Langmuir-Blodgett film onto a surface
320. The method of claim 319, wherein the surface id the surface of a substrate.
321. A method of assembling a plurality of one or more elongated stractures on a surface, wherein at least one ofthe elongated stractures are at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the method comprises acts of: (A) dispersing the one or more elongated stractures in a flexible matrix; (B) stretching the flexible matrix in a direction to produce a shear force on the one or more elongated stractures that causes the at least one elongated structure to align in the direction;
(C) removing the flexible matrix; and - 126 - (D) transferring the at least one aligned elongated structure to a surface.
322. The method of claim 321, wherein the direction is parallel to a plane ofthe surface.
323. The method of claim 321, wherein act (B) comprises: stretching the flexible matrix with an electrically-induced force.
324. The method of claim 321, wherein act (B) comprises: stretching the flexible matrix with an optically-induced force.
325. The method of claim 321, wherein act (B) comprises: stretching the flexible matrix with a mechanically-induced force.
326. The method of claim 321 , wherein act (B) comprises: stretching the flexible matrix with a magnetically-induced force.
327. The method of claim 321, wherein the surface is a surface of a substrate.
328. The method of claim 321 , wherein the flexible matrix is a polymer.
329. A system for growing a doped semiconductor, the system comprising: means for providing a molecules ofthe semiconductor and molecules of a dopant; and means for doping the molecules ofthe semiconductor with the molecules ofthe dopant during growth ofthe semiconductor to produce the doped semiconductor.
330. A system for assembling one or more elongated structures on a surface, the system comprising: means for flowing a fluid that comprises the one or more elongated structures onto the surface; and means for aligning the one or more elongated structures on the surface to form an array ofthe elongated structures. - 127 -
331. A system for assembling one or more elongated stractures on a surface, wherein one or more ofthe elongated structures are at least one ofthe following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises:
. means for conditioning the surface with one or more functionalities that attract the one or more elongated structures to particular positions on the surface, and means for aligning the one or more elongated structures by attracting the one or more elongated structures to the particular positions using the one or more functionalities.
332. A system for assembling a plurality of elongated structures on a surface, wherein one or more ofthe elongated stractures are at least one ofthe following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises means for depositing the plurality of elongated stractures onto the surface; and means for electrically charging the surface to produce electrostatic forces between two or more ofthe plurality ofthe elongated structures.
333. A system for assembling a plurality of elongated structures on a surface, wherein one or more ofthe elongated structures are at least one ofthe following: is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises: means for dispersing the one or more elongated structures on a surface of a liquid phase to form a Langmuir-Blodgett film; means for compressing the Langmuir-Blodgett film; and means for transferring the compressed Langmuir-Blodgett film onto a surface - 128 -
334. A system for assembling a plurality of one or more elongated structures on a surface, wherein at least one ofthe elongated stractures are at least one ofthe following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers, and wherein the system comprises: means for dispersing the one or more elongated structures in a flexible matrix; means for stretching the flexible matrix in a direction to produce a shear force on the one or more elongated structures that causes the at least one elongated structure to align in the direction; means for removing the flexible matrix; and means for transferring the at least one aligned elongated structure to a surface.
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Cited By (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005450A2 (en) 2001-05-18 2003-01-16 President And Fellows Of Harvard College Nanoscale wires and related devices
WO2003104789A1 (en) * 2002-06-06 2003-12-18 Rutgers, The State University Of New Jersey MULTIFUNCTIONAL BIOSENSOR BASED ON ZnO NANOSTRUCTURES
EP1376606A1 (en) * 2002-06-20 2004-01-02 STMicroelectronics S.r.l. A molecular memory obtained using DNA strand molecular switches and carbon nanotubes, and manufacturing method thereof
WO2004010552A1 (en) * 2002-07-19 2004-01-29 President And Fellows Of Harvard College Nanoscale coherent optical components
WO2004038767A2 (en) * 2002-07-16 2004-05-06 President And Fellows Of Harvard College Doped nanoscale wires and method of manufacture
WO2004042830A1 (en) * 2002-11-05 2004-05-21 Koninklijke Philips Electronics N.V. Nanostructure, electronic device having such nanostructure and method of preparing nanostructure
US6781166B2 (en) 1999-07-02 2004-08-24 President & Fellows Of Harvard College Nanoscopic wire-based devices and arrays
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6878871B2 (en) 2002-09-05 2005-04-12 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
WO2005054869A1 (en) * 2003-12-08 2005-06-16 Postech Foundation Biosensor comprising zinc oxide-based nanorod and preparation thereof
EP1547139A2 (en) * 2002-09-30 2005-06-29 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP1563555A2 (en) * 2002-09-30 2005-08-17 Nanosys, Inc. Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
JP2005244240A (en) * 2004-02-26 2005-09-08 Samsung Sdi Co Ltd Thin-film transistor, flat plate display device equipped with the same, manufacturing methods of the thin-film transistor, flat plate display device, and manufacturing method of donor sheet
JP2005260221A (en) * 2004-02-26 2005-09-22 Samsung Sdi Co Ltd Donor sheet, method of manufacturing the donor sheet, method of manufacturing thin film transistors using the donor sheet and method of manufacturing flat panel display device using the donor sheet
US6949206B2 (en) 2002-09-05 2005-09-27 Nanosys, Inc. Organic species that facilitate charge transfer to or from nanostructures
WO2005089165A2 (en) 2004-03-10 2005-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
JP2006501689A (en) * 2002-09-30 2006-01-12 ナノシス・インコーポレイテッド Integrated display using nanowire transistors
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
US7056409B2 (en) 2003-04-17 2006-06-06 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US7067328B2 (en) 2003-09-25 2006-06-27 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
US7074294B2 (en) 2003-04-17 2006-07-11 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US7091120B2 (en) 2003-08-04 2006-08-15 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
EP1696473A2 (en) * 2005-02-25 2006-08-30 Samsung Electronics Co.,Ltd. Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires
US7105428B2 (en) 2004-04-30 2006-09-12 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
US7112525B1 (en) * 2003-12-22 2006-09-26 University Of South Florida Method for the assembly of nanowire interconnects
US7115971B2 (en) 2004-03-23 2006-10-03 Nanosys, Inc. Nanowire varactor diode and methods of making same
KR100661696B1 (en) * 2005-02-22 2006-12-26 삼성전자주식회사 Semiconductor Nanowire of Heterostructure and Method for Producing the same
WO2007038164A2 (en) 2005-09-23 2007-04-05 Nanosys, Inc. Methods for nanostructure doping
WO2007078304A2 (en) 2005-03-24 2007-07-12 Nanosys, Inc. Medical device applications of nanostructured surfaces
WO2007084114A2 (en) * 2005-01-12 2007-07-26 New York University System and method for processing nanowires with holographic optical tweezers
US7267875B2 (en) 2004-06-08 2007-09-11 Nanosys, Inc. Post-deposition encapsulation of nanostructures: compositions, devices and systems incorporating same
WO2007133271A2 (en) 2005-12-29 2007-11-22 Nanosys, Inc. Methods for oriented growth of nanowires on patterned substrates
JP2007329500A (en) * 2002-11-15 2007-12-20 Samsung Electronics Co Ltd Nonvolatile memory device using vertical nanotubes
US7335908B2 (en) 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
US7339184B2 (en) 2004-07-07 2008-03-04 Nanosys, Inc Systems and methods for harvesting and integrating nanowires
US7345307B2 (en) 2004-10-12 2008-03-18 Nanosys, Inc. Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
US7365395B2 (en) 2004-09-16 2008-04-29 Nanosys, Inc. Artificial dielectrics using nanostructures
WO2008060640A2 (en) * 2006-02-02 2008-05-22 William Marsh Rice University Nanoparticle / nanotube-based nanoelectronic devices and chemically-directed assembly thereof
US7473943B2 (en) 2004-10-15 2009-01-06 Nanosys, Inc. Gate configuration for nanowire electronic devices
US7501315B2 (en) 2004-06-08 2009-03-10 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7528002B2 (en) 2004-06-25 2009-05-05 Qunano Ab Formation of nanowhiskers on a substrate of dissimilar material
US7560366B1 (en) 2004-12-02 2009-07-14 Nanosys, Inc. Nanowire horizontal growth and substrate removal
US7566435B2 (en) * 2005-12-30 2009-07-28 Industrial Technology Research Institute Nanowires and method for making the same
US7569503B2 (en) 2004-11-24 2009-08-04 Nanosys, Inc. Contact doping and annealing systems and processes for nanowire thin films
US7572393B2 (en) 2002-09-05 2009-08-11 Nanosys Inc. Organic species that facilitate charge transfer to or from nanostructures
US7586130B2 (en) 2004-10-04 2009-09-08 Panasonic Corporation Vertical field effect transistor using linear structure as a channel region and method for fabricating the same
US7595528B2 (en) 2004-03-10 2009-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US7662313B2 (en) 2002-09-05 2010-02-16 Nanosys, Inc. Oriented nanostructures and methods of preparing
US7666708B2 (en) 2000-08-22 2010-02-23 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
US7772125B2 (en) 2005-02-10 2010-08-10 Panasonic Corporation Structure in which cylindrical microstructure is maintained in anisotropic groove, method for fabricating the same, and semiconductor device, TFT driving circuit, panel, display and sensor using the structure in which cylindrical microstructure is maintained in anisotropic groove
US7776760B2 (en) 2006-11-07 2010-08-17 Nanosys, Inc. Systems and methods for nanowire growth
US7776758B2 (en) 2004-06-08 2010-08-17 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7826336B2 (en) 2006-02-23 2010-11-02 Qunano Ab Data storage nanostructures
US7847238B2 (en) 2006-11-07 2010-12-07 New York University Holographic microfabrication and characterization system for soft matter and biological systems
US7851841B2 (en) 2002-09-30 2010-12-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
US7858965B2 (en) 2005-06-06 2010-12-28 President And Fellows Of Harvard College Nanowire heterostructures
US7892610B2 (en) 2007-05-07 2011-02-22 Nanosys, Inc. Method and system for printing aligned nanowires and other electrical devices
US7911009B2 (en) 2000-12-11 2011-03-22 President And Fellows Of Harvard College Nanosensors
US7910064B2 (en) 2003-06-03 2011-03-22 Nanosys, Inc. Nanowire-based sensor configurations
WO2011072787A1 (en) 2009-12-17 2011-06-23 Merck Patent Gmbh Deposition of nanoparticles
US7968273B2 (en) 2004-06-08 2011-06-28 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7985454B2 (en) 2004-04-30 2011-07-26 Nanosys, Inc. Systems and methods for nanowire growth and manufacturing
US8025960B2 (en) 2004-02-02 2011-09-27 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US8030141B2 (en) 2007-04-25 2011-10-04 Lg Display Co., Ltd. Thin film transistor and method for fabricating the same, and liquid crystal display device and method for manufacturing the same
EP2378597A1 (en) 2005-11-21 2011-10-19 Nanosys, Inc. Nanowire structures comprising carbon
US8049203B2 (en) 2006-12-22 2011-11-01 Qunano Ab Nanoelectronic structure and method of producing such
US8058640B2 (en) 2006-09-11 2011-11-15 President And Fellows Of Harvard College Branched nanoscale wires
US8154002B2 (en) 2004-12-06 2012-04-10 President And Fellows Of Harvard College Nanoscale wire-based data storage
US8174742B2 (en) 2008-03-14 2012-05-08 New York University System for applying optical forces from phase gradients
US8183587B2 (en) 2006-12-22 2012-05-22 Qunano Ab LED with upstanding nanowire structure and method of producing such
US8232584B2 (en) 2005-05-25 2012-07-31 President And Fellows Of Harvard College Nanoscale sensors
US8323789B2 (en) 2006-08-31 2012-12-04 Cambridge Enterprise Limited Nanomaterial polymer compositions and uses thereof
US8364243B2 (en) 2008-04-30 2013-01-29 Nanosys, Inc. Non-fouling surfaces for reflective spheres
US8377683B2 (en) 2002-06-06 2013-02-19 Rutgers, The State University Of New Jersey Zinc oxide-based nanostructure modified QCM for dynamic monitoring of cell adhesion and proliferation
US8390066B2 (en) 2010-03-15 2013-03-05 Kabushiki Kaisha Toshiba Semiconductor nanowire memory device
US8540889B1 (en) 2008-11-19 2013-09-24 Nanosys, Inc. Methods of generating liquidphobic surfaces
US8558311B2 (en) 2004-09-16 2013-10-15 Nanosys, Inc. Dielectrics using substantially longitudinally oriented insulated conductive wires
US8575663B2 (en) 2006-11-22 2013-11-05 President And Fellows Of Harvard College High-sensitivity nanoscale wire sensors
US8591952B2 (en) 2006-10-10 2013-11-26 Massachusetts Institute Of Technology Absorbant superhydrophobic materials, and methods of preparation and use thereof
KR101386268B1 (en) 2005-08-26 2014-04-17 스몰텍 에이비 Interconnects and heat dissipators based on nanostructures
CN103840080A (en) * 2013-12-05 2014-06-04 南昌大学 Voltage control storage based on one-dimensional cadmium doping zinc oxide nanowire and preparing method of voltage control storage
US8790462B2 (en) 2003-04-04 2014-07-29 Qunano Ab Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
US9006133B2 (en) 2008-10-24 2015-04-14 Oned Material Llc Electrochemical catalysts for fuel cells
US9040208B2 (en) 2009-05-04 2015-05-26 Oned Material Llc Catalyst layer for fuel cell membrane electrode assembly, fuel cell membrane electrode assembly using the catalyst layer, fuel cell, and method for producing the catalyst layer
US9102521B2 (en) 2006-06-12 2015-08-11 President And Fellows Of Harvard College Nanosensors and related technologies
US9297796B2 (en) 2009-09-24 2016-03-29 President And Fellows Of Harvard College Bent nanowires and related probing of species
US9390951B2 (en) 2009-05-26 2016-07-12 Sharp Kabushiki Kaisha Methods and systems for electric field deposition of nanowires and other devices
US10049871B2 (en) 2013-02-06 2018-08-14 President And Fellows Of Harvard College Anisotropic deposition in nanoscale wires
US10263149B2 (en) 2006-12-22 2019-04-16 Qunano Ab Nanostructured LED array with collimating reflectors
US10279341B2 (en) 2004-02-02 2019-05-07 Oned Material Llc Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US10374072B2 (en) 2004-06-04 2019-08-06 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US10435817B2 (en) 2014-05-07 2019-10-08 President And Fellows Of Harvard College Controlled growth of nanoscale wires
US10490817B2 (en) 2009-05-19 2019-11-26 Oned Material Llc Nanostructured materials for battery applications
US10567152B2 (en) 2016-02-22 2020-02-18 Mc10, Inc. System, devices, and method for on-body data and power transmission
CN111477560A (en) * 2020-05-14 2020-07-31 包头美科硅能源有限公司 Rapid detection method for distinguishing gallium-boron-doped single crystal silicon rods for solar cell
US10986465B2 (en) 2015-02-20 2021-04-20 Medidata Solutions, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation

Families Citing this family (419)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (en) 1997-12-30 2000-01-28 Commissariat Energie Atomique METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS
US7015546B2 (en) * 2000-02-23 2006-03-21 Semiconductor Research Corporation Deterministically doped field-effect devices and methods of making same
US6919119B2 (en) * 2000-05-30 2005-07-19 The Penn State Research Foundation Electronic and opto-electronic devices fabricated from nanostructured high surface to volume ratio thin films
KR100360476B1 (en) * 2000-06-27 2002-11-08 삼성전자 주식회사 Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US20060175601A1 (en) * 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
EP1329913A4 (en) * 2000-08-30 2006-08-23 Japan Science & Tech Agency Magnetic semiconductor material and method for preparation thereof
JP2004532133A (en) 2001-03-30 2004-10-21 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・カリフォルニア Method for assembling nanostructures and nanowires and device assembled therefrom
AU2008200507B2 (en) * 2001-03-30 2010-04-22 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
US6835591B2 (en) * 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
US7259410B2 (en) * 2001-07-25 2007-08-21 Nantero, Inc. Devices having horizontally-disposed nanofabric articles and methods of making the same
US6924538B2 (en) * 2001-07-25 2005-08-02 Nantero, Inc. Devices having vertically-disposed nanofabric articles and methods of making the same
US6706402B2 (en) 2001-07-25 2004-03-16 Nantero, Inc. Nanotube films and articles
WO2003010143A1 (en) * 2001-07-26 2003-02-06 Samsung Electronics Co., Ltd. Dialkylhydroxybenzoic acid derivatives containing metal chelating groups and their therapeutic uses
US7385262B2 (en) * 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6882767B2 (en) * 2001-12-27 2005-04-19 The Regents Of The University Of California Nanowire optoelectric switching device and method
US7279718B2 (en) * 2002-01-28 2007-10-09 Philips Lumileds Lighting Company, Llc LED including photonic crystal structure
EP1341183B1 (en) * 2002-02-25 2008-12-03 STMicroelectronics S.r.l. Optically readable molecular memory obtained using carbon nanotubes, and method for storing information in said molecular memory
AU2003214246A1 (en) * 2002-03-22 2003-10-13 Penn State Research Foundation Thermal production of nanowires
US20040026684A1 (en) * 2002-04-02 2004-02-12 Nanosys, Inc. Nanowire heterostructures for encoding information
US7335395B2 (en) * 2002-04-23 2008-02-26 Nantero, Inc. Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
US20040067530A1 (en) * 2002-05-08 2004-04-08 The Regents Of The University Of California Electronic sensing of biomolecular processes
US20050126628A1 (en) * 2002-09-05 2005-06-16 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
EP1537445B1 (en) * 2002-09-05 2012-08-01 Nanosys, Inc. Nanocomposites
AU2002334664A1 (en) * 2002-09-17 2004-04-08 Midwest Research Institute Carbon nanotube heat-exchange systems
US7051945B2 (en) * 2002-09-30 2006-05-30 Nanosys, Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US7067867B2 (en) * 2002-09-30 2006-06-27 Nanosys, Inc. Large-area nonenabled macroelectronic substrates and uses therefor
US7619562B2 (en) * 2002-09-30 2009-11-17 Nanosys, Inc. Phased array systems
US6841235B2 (en) * 2002-10-11 2005-01-11 General Motors Corporation Metallic nanowire and method of making the same
DE10250829B4 (en) * 2002-10-31 2006-11-02 Infineon Technologies Ag Nonvolatile memory cell, memory cell array, and method of making a nonvolatile memory cell
US7355216B2 (en) * 2002-12-09 2008-04-08 The Regents Of The University Of California Fluidic nanotubes and devices
US7898005B2 (en) * 2002-12-09 2011-03-01 The Regents Of The University Of California Inorganic nanotubes and electro-fluidic devices fabricated therefrom
US7211143B2 (en) * 2002-12-09 2007-05-01 The Regents Of The University Of California Sacrificial template method of fabricating a nanotube
JP4434575B2 (en) * 2002-12-13 2010-03-17 キヤノン株式会社 Thermoelectric conversion element and manufacturing method thereof
JP4428921B2 (en) * 2002-12-13 2010-03-10 キヤノン株式会社 Nanostructure, electronic device, and manufacturing method thereof
US20040200734A1 (en) * 2002-12-19 2004-10-14 Co Man Sung Nanotube-based sensors for biomolecules
KR20040059300A (en) * 2002-12-28 2004-07-05 학교법인 포항공과대학교 Nanostructure comprising magnetic material and nanomaterial and method for manufacturing thereof
US7535019B1 (en) 2003-02-18 2009-05-19 Nanosolar, Inc. Optoelectronic fiber
US7075141B2 (en) * 2003-03-28 2006-07-11 Nantero, Inc. Four terminal non-volatile transistor device
US6944054B2 (en) * 2003-03-28 2005-09-13 Nantero, Inc. NRAM bit selectable two-device nanotube array
US7294877B2 (en) * 2003-03-28 2007-11-13 Nantero, Inc. Nanotube-on-gate FET structures and applications
US7113426B2 (en) * 2003-03-28 2006-09-26 Nantero, Inc. Non-volatile RAM cell and array using nanotube switch position for information state
WO2004088755A1 (en) * 2003-04-04 2004-10-14 Startskottet 22286 Ab Nanowhiskers with pn junctions and methods of fabricating thereof
US20050038498A1 (en) * 2003-04-17 2005-02-17 Nanosys, Inc. Medical device applications of nanostructured surfaces
US7579077B2 (en) * 2003-05-05 2009-08-25 Nanosys, Inc. Nanofiber surfaces for use in enhanced surface area applications
US20060122596A1 (en) * 2003-04-17 2006-06-08 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US20050221072A1 (en) * 2003-04-17 2005-10-06 Nanosys, Inc. Medical device applications of nanostructured surfaces
US6995046B2 (en) 2003-04-22 2006-02-07 Nantero, Inc. Process for making byte erasable devices having elements made with nanotubes
US7045421B2 (en) * 2003-04-22 2006-05-16 Nantero, Inc. Process for making bit selectable devices having elements made with nanotubes
JP4871726B2 (en) * 2003-04-28 2012-02-08 ナノシス・インク. Super lyophobic surface, its preparation and use
TWI427709B (en) * 2003-05-05 2014-02-21 Nanosys Inc Nanofiber surfaces for use in enhanced surface area applications
US7803574B2 (en) 2003-05-05 2010-09-28 Nanosys, Inc. Medical device applications of nanostructured surfaces
WO2005019793A2 (en) * 2003-05-14 2005-03-03 Nantero, Inc. Sensor platform using a horizontally oriented nanotube element
CA2532864A1 (en) * 2003-07-28 2005-06-30 The Regents Of The University Of California Langmuir-blodgett nanostructure monolayers
WO2005017967A2 (en) * 2003-08-13 2005-02-24 Nantero, Inc. Nanotube device structure and methods of fabrication
JP2007502545A (en) * 2003-08-13 2007-02-08 ナンテロ,インク. Nanotube-based exchange element with a plurality of control devices and circuit produced from said element
US7235421B2 (en) * 2003-09-16 2007-06-26 Nasreen Chopra System and method for developing production nano-material
US20050214197A1 (en) * 2003-09-17 2005-09-29 Molecular Nanosystems, Inc. Methods for producing and using catalytic substrates for carbon nanotube growth
US7235159B2 (en) * 2003-09-17 2007-06-26 Molecular Nanosystems, Inc. Methods for producing and using catalytic substrates for carbon nanotube growth
JP5260830B2 (en) 2003-09-23 2013-08-14 古河電気工業株式会社 Method for manufacturing a one-dimensional semiconductor substrate
DE10345157B4 (en) * 2003-09-29 2009-01-08 Qimonda Ag Thermally conductive packaging of electronic circuit units
US7012279B2 (en) * 2003-10-21 2006-03-14 Lumileds Lighting U.S., Llc Photonic crystal light emitting device
FR2861497B1 (en) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
US7258807B2 (en) * 2003-12-12 2007-08-21 Yale University Controlled growth of gallium nitride nanostructures
US7421173B2 (en) * 2003-12-16 2008-09-02 President And Fellows Of Harvard College Subwavelength-diameter silica wires for low-loss optical waveguiding
US7208094B2 (en) * 2003-12-17 2007-04-24 Hewlett-Packard Development Company, L.P. Methods of bridging lateral nanowires and device using same
JP2007525830A (en) * 2003-12-22 2007-09-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Fabrication of semiconductor nanowire group and electronic device including nanowire group
EP1700346A1 (en) * 2003-12-23 2006-09-13 Koninklijke Philips Electronics N.V. Semiconductor device comprising a pn-heterojunction
US7018549B2 (en) * 2003-12-29 2006-03-28 Intel Corporation Method of fabricating multiple nanowires of uniform length from a single catalytic nanoparticle
WO2005110057A2 (en) * 2004-01-06 2005-11-24 The Regents Of The University Of California Crystallographic alignment of high-density nanowire arrays
JP2007526200A (en) * 2004-01-14 2007-09-13 ザ リージェンツ オブ ザ ユニヴァーシティ オブ カリフォルニア Diluted magnetic semiconductor nanowires exhibiting magnetoresistance
WO2005067524A2 (en) * 2004-01-15 2005-07-28 Nanosys, Inc. Nanocrystal doped matrixes
US7645397B2 (en) * 2004-01-15 2010-01-12 Nanosys, Inc. Nanocrystal doped matrixes
US7553371B2 (en) * 2004-02-02 2009-06-30 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US7354850B2 (en) * 2004-02-06 2008-04-08 Qunano Ab Directionally controlled growth of nanowhiskers
TW200537143A (en) * 2004-02-11 2005-11-16 Koninkl Philips Electronics Nv Integrated optical wave guide for light generated by a bipolar transistor
US20090227107A9 (en) * 2004-02-13 2009-09-10 President And Fellows Of Havard College Nanostructures Containing Metal Semiconductor Compounds
US7253431B2 (en) * 2004-03-02 2007-08-07 International Business Machines Corporation Method and apparatus for solution processed doping of carbon nanotube
KR100534204B1 (en) * 2004-03-17 2005-12-07 한국과학기술연구원 Nanowire assisted laser desorption/ionization mass spectrometric analysis
US20050205883A1 (en) * 2004-03-19 2005-09-22 Wierer Jonathan J Jr Photonic crystal light emitting device
FR2868201B1 (en) * 2004-03-23 2007-06-29 Ecole Polytechnique Dgar METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS AND ELECTRONIC COMPONENTS OBTAINED THEREBY
US20050212531A1 (en) * 2004-03-23 2005-09-29 Hewlett-Packard Development Company, L.P. Intellectual Property Administration Fluid sensor and methods
US7305869B1 (en) * 2004-04-12 2007-12-11 U. S. Department Of Energy Spin microscope based on optically detected magnetic resonance
US7785922B2 (en) 2004-04-30 2010-08-31 Nanosys, Inc. Methods for oriented growth of nanowires on patterned substrates
US7700459B2 (en) * 2004-06-01 2010-04-20 Nikon Corporation Method for producing electronic device and electronic device
US8563133B2 (en) 2004-06-08 2013-10-22 Sandisk Corporation Compositions and methods for modulation of nanostructure energy levels
US8088483B1 (en) 2004-06-08 2012-01-03 Nanosys, Inc. Process for group 10 metal nanostructure synthesis and compositions made using same
WO2006107312A1 (en) * 2004-06-15 2006-10-12 President And Fellows Of Harvard College Nanosensors
US7161403B2 (en) 2004-06-18 2007-01-09 Nantero, Inc. Storage elements using nanotube switching elements
US7288970B2 (en) * 2004-06-18 2007-10-30 Nantero, Inc. Integrated nanotube and field effect switching device
US7164744B2 (en) 2004-06-18 2007-01-16 Nantero, Inc. Nanotube-based logic driver circuits
WO2006001332A1 (en) * 2004-06-25 2006-01-05 Japan Science And Technology Agency Method of spin recording and apparatus
EP1771884B1 (en) * 2004-07-20 2010-10-06 Nxp B.V. Semiconductor device and method of manufacturing the same
US7442964B2 (en) * 2004-08-04 2008-10-28 Philips Lumileds Lighting Company, Llc Photonic crystal light emitting device with multiple lattices
US8309843B2 (en) * 2004-08-19 2012-11-13 Banpil Photonics, Inc. Photovoltaic cells based on nanoscale structures
TWI399864B (en) 2004-09-16 2013-06-21 Nantero Inc Light emitters using nanotubes and methods of making same
US20060084128A1 (en) * 2004-09-22 2006-04-20 Hongye Sun Enzyme assay with nanowire sensor
US7400665B2 (en) * 2004-11-05 2008-07-15 Hewlett-Packard Developement Company, L.P. Nano-VCSEL device and fabrication thereof using nano-colonnades
US7307271B2 (en) * 2004-11-05 2007-12-11 Hewlett-Packard Development Company, L.P. Nanowire interconnection and nano-scale device applications
WO2006052891A1 (en) * 2004-11-09 2006-05-18 The Regents Of The University Of California Analyte identification using electronic devices
WO2006073562A2 (en) * 2004-11-17 2006-07-13 Nanosys, Inc. Photoactive devices and components with enhanced efficiency
US7582534B2 (en) * 2004-11-18 2009-09-01 International Business Machines Corporation Chemical doping of nano-components
US7405129B2 (en) * 2004-11-18 2008-07-29 International Business Machines Corporation Device comprising doped nano-component and method of forming the device
US7842432B2 (en) 2004-12-09 2010-11-30 Nanosys, Inc. Nanowire structures comprising carbon
CN101107737B (en) 2004-12-09 2012-03-21 奈米系统股份有限公司 Nanowire-based membrane electrode assemblies for fuel cells
US8278011B2 (en) 2004-12-09 2012-10-02 Nanosys, Inc. Nanostructured catalyst supports
US7939218B2 (en) * 2004-12-09 2011-05-10 Nanosys, Inc. Nanowire structures comprising carbon
CN100376906C (en) * 2004-12-11 2008-03-26 鸿富锦精密工业(深圳)有限公司 Colour optical filter
CN100487879C (en) * 2004-12-28 2009-05-13 松下电器产业株式会社 Semiconductor nano-wire, making method thereof and semiconductor device provided with that nano-wire
US7122461B2 (en) * 2005-02-10 2006-10-17 Intel Corporation Method to assemble structures from nano-materials
KR100624461B1 (en) * 2005-02-25 2006-09-19 삼성전자주식회사 Nano wire and manfacturing methof for the same
US7504014B2 (en) * 2005-03-15 2009-03-17 Fujitsu Limited High density interconnections with nanowiring
US20060207647A1 (en) * 2005-03-16 2006-09-21 General Electric Company High efficiency inorganic nanorod-enhanced photovoltaic devices
KR101100887B1 (en) 2005-03-17 2012-01-02 삼성전자주식회사 Thin film transistor, thin film transistor array panel, and manufacturing method thereof
US20070238186A1 (en) * 2005-03-29 2007-10-11 Hongye Sun Nanowire-based system for analysis of nucleic acids
EP1871162B1 (en) * 2005-04-13 2014-03-12 Nanosys, Inc. Nanowire dispersion compositions and uses thereof
WO2006116424A2 (en) * 2005-04-26 2006-11-02 Nanosys, Inc. Paintable nanofiber coatings
US7479654B2 (en) 2005-05-09 2009-01-20 Nantero, Inc. Memory arrays using nanotube articles with reprogrammable resistance
WO2006124625A2 (en) * 2005-05-12 2006-11-23 Nanosys, Inc. Use of nanoparticles in film formation and as solder
KR100833017B1 (en) * 2005-05-12 2008-05-27 주식회사 엘지화학 Method for preparing a high resolution pattern with direct writing means
US7510951B2 (en) * 2005-05-12 2009-03-31 Lg Chem, Ltd. Method for forming high-resolution pattern with direct writing means
WO2006130359A2 (en) * 2005-06-02 2006-12-07 Nanosys, Inc. Light emitting nanowires for macroelectronics
US20080197440A1 (en) * 2005-06-02 2008-08-21 Misuzu R & D Ltd. Nonvolatile Memory
US8359548B2 (en) 2005-06-10 2013-01-22 T-Mobile Usa, Inc. Managing subset of user contacts
US7685530B2 (en) * 2005-06-10 2010-03-23 T-Mobile Usa, Inc. Preferred contact group centric interface
US8370770B2 (en) 2005-06-10 2013-02-05 T-Mobile Usa, Inc. Variable path management of user contacts
US8370769B2 (en) * 2005-06-10 2013-02-05 T-Mobile Usa, Inc. Variable path management of user contacts
US8163575B2 (en) 2005-06-17 2012-04-24 Philips Lumileds Lighting Company Llc Grown photonic crystals in semiconductor light emitting devices
US20090050204A1 (en) * 2007-08-03 2009-02-26 Illuminex Corporation. Photovoltaic device using nanostructured material
US7196262B2 (en) * 2005-06-20 2007-03-27 Solyndra, Inc. Bifacial elongated solar cell devices
US7394016B2 (en) * 2005-10-11 2008-07-01 Solyndra, Inc. Bifacial elongated solar cell devices with internal reflectors
US20100193768A1 (en) * 2005-06-20 2010-08-05 Illuminex Corporation Semiconducting nanowire arrays for photovoltaic applications
US8344238B2 (en) * 2005-07-19 2013-01-01 Solyndra Llc Self-cleaning protective coatings for use with photovoltaic cells
JP5324222B2 (en) * 2005-08-22 2013-10-23 キュー・ワン・ナノシステムズ・インコーポレイテッド Nanostructure and photovoltaic cell implementing it
KR20070040129A (en) * 2005-10-11 2007-04-16 삼성에스디아이 주식회사 Carbon naanotubes structure and vertical alignement method of the carbon nanotubes
WO2007047523A2 (en) * 2005-10-14 2007-04-26 Pennsylvania State University System and method for positioning and synthesizing of nanostructures
KR100845704B1 (en) * 2005-10-19 2008-07-11 주식회사 엘지화학 Method for manufacturing nanowires and substrate on which nanowires are grown
US8314327B2 (en) * 2005-11-06 2012-11-20 Banpil Photonics, Inc. Photovoltaic cells based on nano or micro-scale structures
WO2007062268A2 (en) * 2005-11-28 2007-05-31 University Of Florida Research Foundation, Inc. Method and structure for magnetically-directed, self-assembly of three-dimensional structures
US8816191B2 (en) * 2005-11-29 2014-08-26 Banpil Photonics, Inc. High efficiency photovoltaic cells and manufacturing thereof
US7394094B2 (en) * 2005-12-29 2008-07-01 Massachusetts Institute Of Technology Semiconductor nanocrystal heterostructures
US7741197B1 (en) 2005-12-29 2010-06-22 Nanosys, Inc. Systems and methods for harvesting and reducing contamination in nanowires
US7259322B2 (en) * 2006-01-09 2007-08-21 Solyndra, Inc. Interconnects for solar cell devices
US8791359B2 (en) * 2006-01-28 2014-07-29 Banpil Photonics, Inc. High efficiency photovoltaic cells
US20070186629A1 (en) * 2006-02-10 2007-08-16 Ying-Lan Chang Functionalizable nanowire-based AFM probe
EP2013611A2 (en) * 2006-03-15 2009-01-14 The President and Fellows of Harvard College Nanobioelectronics
US20090014055A1 (en) * 2006-03-18 2009-01-15 Solyndra, Inc. Photovoltaic Modules Having a Filling Material
US20070215197A1 (en) * 2006-03-18 2007-09-20 Benyamin Buller Elongated photovoltaic cells in casings
US20080302418A1 (en) * 2006-03-18 2008-12-11 Benyamin Buller Elongated Photovoltaic Devices in Casings
US8183458B2 (en) 2007-03-13 2012-05-22 Solyndra Llc Photovoltaic apparatus having a filler layer and method for making the same
US20070215195A1 (en) * 2006-03-18 2007-09-20 Benyamin Buller Elongated photovoltaic cells in tubular casings
JP4970997B2 (en) 2006-03-30 2012-07-11 パナソニック株式会社 Manufacturing method of nanowire transistor
US8017860B2 (en) * 2006-05-15 2011-09-13 Stion Corporation Method and structure for thin film photovoltaic materials using bulk semiconductor materials
US9105776B2 (en) * 2006-05-15 2015-08-11 Stion Corporation Method and structure for thin film photovoltaic materials using semiconductor materials
US8255281B2 (en) * 2006-06-07 2012-08-28 T-Mobile Usa, Inc. Service management system that enables subscriber-driven changes to service plans
US7714386B2 (en) * 2006-06-09 2010-05-11 Northrop Grumman Systems Corporation Carbon nanotube field effect transistor
FR2904304B1 (en) * 2006-07-27 2008-10-17 Commissariat Energie Atomique METHOD FOR MANUFACTURING NANOSTRUCTURE ON A PRE-GRAVE SUBSTRATE
US7998788B2 (en) * 2006-07-27 2011-08-16 International Business Machines Corporation Techniques for use of nanotechnology in photovoltaics
US7888753B2 (en) * 2006-07-31 2011-02-15 International Business Machines Corporation Ultra-sensitive detection techniques
US7879685B2 (en) * 2006-08-04 2011-02-01 Solyndra, Inc. System and method for creating electric isolation between layers comprising solar cells
US20080029152A1 (en) * 2006-08-04 2008-02-07 Erel Milshtein Laser scribing apparatus, systems, and methods
WO2008097275A2 (en) * 2006-08-30 2008-08-14 Molecular Nanosystems, Inc. Methods for forming freestanding nanotube objects and objects so formed
US7834424B2 (en) * 2006-09-12 2010-11-16 The Board Of Trustees Of The Leland Stanford Junior University Extendable connector and network
JP5091242B2 (en) * 2006-10-04 2012-12-05 エヌエックスピー ビー ヴィ MIM capacitor
JP2010505728A (en) * 2006-10-05 2010-02-25 日立化成工業株式会社 High array, high aspect ratio, high density silicon nanowires and method for producing the same
US7388200B2 (en) * 2006-10-19 2008-06-17 Hewlett-Packard Development Company, L.P. Sensing method and nanosensing device for performing the same
US8624108B1 (en) * 2006-11-01 2014-01-07 Banpil Photonics, Inc. Photovoltaic cells based on nano or micro-scale structures
WO2008060455A2 (en) 2006-11-09 2008-05-22 Nanosys, Inc. Methods for nanowire alignment and deposition
US20080110486A1 (en) * 2006-11-15 2008-05-15 General Electric Company Amorphous-crystalline tandem nanostructured solar cells
KR100829579B1 (en) * 2006-11-27 2008-05-14 삼성전자주식회사 Field effect transistor using a nano tube and method for manufacturing the transistor
US7786024B2 (en) 2006-11-29 2010-08-31 Nanosys, Inc. Selective processing of semiconductor nanowires by polarized visible radiation
US8258047B2 (en) 2006-12-04 2012-09-04 General Electric Company Nanostructures, methods of depositing nanostructures and devices incorporating the same
US8686490B2 (en) * 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US20080150004A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US20080150009A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
WO2008079078A1 (en) 2006-12-22 2008-07-03 Qunano Ab Elevated led and method of producing such
US20080178927A1 (en) * 2007-01-30 2008-07-31 Thomas Brezoczky Photovoltaic apparatus having an elongated photovoltaic device using an involute-based concentrator
US7851784B2 (en) * 2007-02-13 2010-12-14 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array electronic devices
US20080196759A1 (en) * 2007-02-16 2008-08-21 Thomas Brezoczky Photovoltaic assembly with elongated photovoltaic devices and integrated involute-based reflectors
WO2008143727A2 (en) 2007-02-27 2008-11-27 The Regents Of The University Of California Nanowire photodetector and image sensor with internal gain
US7728333B2 (en) * 2007-03-09 2010-06-01 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array ballistic light emitting devices
KR101345440B1 (en) * 2007-03-15 2013-12-27 삼성전자주식회사 Method for Mass Producing Nanostructure Using Mesoporous Template and Nanostructure Made Thereof
US8212235B2 (en) 2007-04-25 2012-07-03 Hewlett-Packard Development Company, L.P. Nanowire-based opto-electronic device
US7880318B1 (en) 2007-04-27 2011-02-01 Hewlett-Packard Development Company, L.P. Sensing system and method of making the same
CN101675522B (en) * 2007-05-07 2012-08-29 Nxp股份有限公司 A photosensitive device and a method of manufacturing a photosensitive device
KR101356694B1 (en) * 2007-05-10 2014-01-29 삼성전자주식회사 Light emitting diode using Si-nanowire and method of fabricating the same
KR20080100057A (en) * 2007-05-11 2008-11-14 주성엔지니어링(주) Manufacturing method of crystalline silicon solar cell and manufacturing apparatus and system for the same
US7939346B2 (en) * 2007-05-25 2011-05-10 Wisconsin Alumni Research Foundation Nanomembranes for remote sensing
FR2916902B1 (en) * 2007-05-31 2009-07-17 Commissariat Energie Atomique FIELD EFFECT TRANSISTOR WITH CARBON NANOTUBES
US7663202B2 (en) * 2007-06-26 2010-02-16 Hewlett-Packard Development Company, L.P. Nanowire photodiodes and methods of making nanowire photodiodes
US8071179B2 (en) 2007-06-29 2011-12-06 Stion Corporation Methods for infusing one or more materials into nano-voids if nanoporous or nanostructured materials
DE102007031600B4 (en) * 2007-07-06 2015-10-15 Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh Array of vertical UV light-emitting diodes and method for its production
US20110143137A1 (en) * 2007-07-10 2011-06-16 The Regents Of The University Of California Composite Nanorods
EP2171761A4 (en) * 2007-07-19 2011-11-02 California Inst Of Techn Structures of ordered arrays of semiconductors
US7833504B2 (en) * 2007-08-27 2010-11-16 The Research Foundation Of State University Of New York Silylated carbon nanotubes and methods of making same
JP2010538464A (en) * 2007-08-28 2010-12-09 カリフォルニア インスティテュート オブ テクノロジー Polymer embedded semiconductor rod array
KR101345456B1 (en) 2007-08-29 2013-12-27 재단법인서울대학교산학협력재단 Horizontal nanowire growth method at selective location, nanowire prepared therefrom and nano device comprising the same
JP5347377B2 (en) * 2007-08-31 2013-11-20 大日本印刷株式会社 Vertical organic transistor, manufacturing method thereof, and light emitting device
US20090078303A1 (en) * 2007-09-24 2009-03-26 Solyndra, Inc. Encapsulated Photovoltaic Device Used With A Reflector And A Method of Use for the Same
US8287942B1 (en) 2007-09-28 2012-10-16 Stion Corporation Method for manufacture of semiconductor bearing thin film material
US8759671B2 (en) 2007-09-28 2014-06-24 Stion Corporation Thin film metal oxide bearing semiconductor material for single junction solar cell devices
US7745315B1 (en) 2007-10-03 2010-06-29 Sandia Corporation Highly aligned vertical GaN nanowires using submonolayer metal catalysts
US7915146B2 (en) * 2007-10-23 2011-03-29 International Business Machines Corporation Controlled doping of semiconductor nanowires
US8187434B1 (en) 2007-11-14 2012-05-29 Stion Corporation Method and system for large scale manufacture of thin film photovoltaic devices using single-chamber configuration
US8142890B1 (en) * 2007-12-05 2012-03-27 University Of Central Florida Research Foundation, Inc. Fabrication of high aspect ratio core-shell CdS-Mn/ZnS nanowires
JP5519524B2 (en) * 2007-12-06 2014-06-11 ナノシス・インク. Absorbable nano-reinforced hemostatic structure and bandage material
US8319002B2 (en) * 2007-12-06 2012-11-27 Nanosys, Inc. Nanostructure-enhanced platelet binding and hemostatic structures
SG153674A1 (en) * 2007-12-11 2009-07-29 Nanyang Polytechnic A method of doping and apparatus for doping
FR2925221B1 (en) * 2007-12-17 2010-02-19 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER
US8624224B2 (en) * 2008-01-24 2014-01-07 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array bipolar transistors
US8610125B2 (en) * 2008-01-24 2013-12-17 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array light emitting diodes
US8440994B2 (en) * 2008-01-24 2013-05-14 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array electronic and opto-electronic devices
US8492249B2 (en) * 2008-01-24 2013-07-23 Nano-Electronic And Photonic Devices And Circuits, Llc Methods of forming catalytic nanopads
US8610104B2 (en) 2008-01-24 2013-12-17 Nano-Electronic And Photonic Devices And Circuits, Llc Nanotube array injection lasers
US8603246B2 (en) * 2008-01-30 2013-12-10 Palo Alto Research Center Incorporated Growth reactor systems and methods for low-temperature synthesis of nanowires
WO2009100458A2 (en) * 2008-02-08 2009-08-13 Clean Cell International Inc. Composite nanorod-based structures for generating electricity
US8440903B1 (en) 2008-02-21 2013-05-14 Stion Corporation Method and structure for forming module using a powder coating and thermal treatment process
TWI485642B (en) * 2008-02-26 2015-05-21 Epistar Corp A customized manufacturing method for an optoelectrical device
US8075723B1 (en) 2008-03-03 2011-12-13 Stion Corporation Laser separation method for manufacture of unit cells for thin film photovoltaic materials
US8772078B1 (en) 2008-03-03 2014-07-08 Stion Corporation Method and system for laser separation for exclusion region of multi-junction photovoltaic materials
CN101552297B (en) * 2008-04-03 2012-11-21 清华大学 Solar cell
CN101562204B (en) * 2008-04-18 2011-03-23 鸿富锦精密工业(深圳)有限公司 Solar energy battery
CN101552295A (en) * 2008-04-03 2009-10-07 清华大学 Solar cell
CN101527327B (en) * 2008-03-07 2012-09-19 清华大学 Solar cell
CN101562203B (en) * 2008-04-18 2014-07-09 清华大学 Solar energy battery
US8094023B1 (en) * 2008-03-10 2012-01-10 Sandia Corporation Phononic crystal devices
WO2009134687A2 (en) * 2008-04-27 2009-11-05 The Board Of Trustees Of The University Of Illinois Method of fabricating a planar semiconductor nanowire
CN101582450B (en) * 2008-05-16 2012-03-28 清华大学 Thin film transistor
US7939454B1 (en) 2008-05-31 2011-05-10 Stion Corporation Module and lamination process for multijunction cells
US8642138B2 (en) 2008-06-11 2014-02-04 Stion Corporation Processing method for cleaning sulfur entities of contact regions
US9087943B2 (en) 2008-06-25 2015-07-21 Stion Corporation High efficiency photovoltaic cell and manufacturing method free of metal disulfide barrier material
US8003432B2 (en) 2008-06-25 2011-08-23 Stion Corporation Consumable adhesive layer for thin film photovoltaic material
US7960653B2 (en) * 2008-07-25 2011-06-14 Hewlett-Packard Development Company, L.P. Conductive nanowires for electrical interconnect
US8207008B1 (en) 2008-08-01 2012-06-26 Stion Corporation Affixing method and solar decal device using a thin film photovoltaic
US20100051932A1 (en) * 2008-08-28 2010-03-04 Seo-Yong Cho Nanostructure and uses thereof
US9343490B2 (en) 2013-08-09 2016-05-17 Zena Technologies, Inc. Nanowire structured color filter arrays and fabrication method of the same
US9082673B2 (en) 2009-10-05 2015-07-14 Zena Technologies, Inc. Passivated upstanding nanostructures and methods of making the same
US8748799B2 (en) 2010-12-14 2014-06-10 Zena Technologies, Inc. Full color single pixel including doublet or quadruplet si nanowires for image sensors
US8299472B2 (en) 2009-12-08 2012-10-30 Young-June Yu Active pixel sensor with nanowire structured photodetectors
US8835831B2 (en) 2010-06-22 2014-09-16 Zena Technologies, Inc. Polarized light detecting device and fabrication methods of the same
US8269985B2 (en) 2009-05-26 2012-09-18 Zena Technologies, Inc. Determination of optimal diameters for nanowires
US8546742B2 (en) 2009-06-04 2013-10-01 Zena Technologies, Inc. Array of nanowires in a single cavity with anti-reflective coating on substrate
US8229255B2 (en) * 2008-09-04 2012-07-24 Zena Technologies, Inc. Optical waveguides in image sensors
US8890271B2 (en) 2010-06-30 2014-11-18 Zena Technologies, Inc. Silicon nitride light pipes for image sensors
US8889455B2 (en) 2009-12-08 2014-11-18 Zena Technologies, Inc. Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor
US8791470B2 (en) 2009-10-05 2014-07-29 Zena Technologies, Inc. Nano structured LEDs
US9478685B2 (en) 2014-06-23 2016-10-25 Zena Technologies, Inc. Vertical pillar structured infrared detector and fabrication method for the same
US9000353B2 (en) 2010-06-22 2015-04-07 President And Fellows Of Harvard College Light absorption and filtering properties of vertically oriented semiconductor nano wires
US9515218B2 (en) 2008-09-04 2016-12-06 Zena Technologies, Inc. Vertical pillar structured photovoltaic devices with mirrors and optical claddings
US8519379B2 (en) 2009-12-08 2013-08-27 Zena Technologies, Inc. Nanowire structured photodiode with a surrounding epitaxially grown P or N layer
US8866065B2 (en) 2010-12-13 2014-10-21 Zena Technologies, Inc. Nanowire arrays comprising fluorescent nanowires
US8735797B2 (en) 2009-12-08 2014-05-27 Zena Technologies, Inc. Nanowire photo-detector grown on a back-side illuminated image sensor
US9406709B2 (en) 2010-06-22 2016-08-02 President And Fellows Of Harvard College Methods for fabricating and using nanowires
US9299866B2 (en) 2010-12-30 2016-03-29 Zena Technologies, Inc. Nanowire array based solar energy harvesting device
US8274039B2 (en) 2008-11-13 2012-09-25 Zena Technologies, Inc. Vertical waveguides with various functionality on integrated circuits
US7855089B2 (en) 2008-09-10 2010-12-21 Stion Corporation Application specific solar cell and method for manufacture using thin film photovoltaic materials
US8153482B2 (en) * 2008-09-22 2012-04-10 Sharp Laboratories Of America, Inc. Well-structure anti-punch-through microwire device
US8501521B1 (en) 2008-09-29 2013-08-06 Stion Corporation Copper species surface treatment of thin film photovoltaic cell and manufacturing method
US8026122B1 (en) 2008-09-29 2011-09-27 Stion Corporation Metal species surface treatment of thin film photovoltaic cell and manufacturing method
US8476104B1 (en) 2008-09-29 2013-07-02 Stion Corporation Sodium species surface treatment of thin film photovoltaic cell and manufacturing method
US8008110B1 (en) 2008-09-29 2011-08-30 Stion Corporation Bulk sodium species treatment of thin film photovoltaic cell and manufacturing method
US8236597B1 (en) 2008-09-29 2012-08-07 Stion Corporation Bulk metal species treatment of thin film photovoltaic cell and manufacturing method
US8008112B1 (en) 2008-09-29 2011-08-30 Stion Corporation Bulk chloride species treatment of thin film photovoltaic cell and manufacturing method
US8394662B1 (en) 2008-09-29 2013-03-12 Stion Corporation Chloride species surface treatment of thin film photovoltaic cell and manufacturing method
US8383450B2 (en) 2008-09-30 2013-02-26 Stion Corporation Large scale chemical bath system and method for cadmium sulfide processing of thin film photovoltaic materials
US8425739B1 (en) 2008-09-30 2013-04-23 Stion Corporation In chamber sodium doping process and system for large scale cigs based thin film photovoltaic materials
US7910399B1 (en) 2008-09-30 2011-03-22 Stion Corporation Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates
US7863074B2 (en) 2008-09-30 2011-01-04 Stion Corporation Patterning electrode materials free from berm structures for thin film photovoltaic cells
US7947524B2 (en) 2008-09-30 2011-05-24 Stion Corporation Humidity control and method for thin film photovoltaic materials
US8741689B2 (en) 2008-10-01 2014-06-03 Stion Corporation Thermal pre-treatment process for soda lime glass substrate for thin film photovoltaic materials
US20110018103A1 (en) 2008-10-02 2011-01-27 Stion Corporation System and method for transferring substrates in large scale processing of cigs and/or cis devices
US8003430B1 (en) 2008-10-06 2011-08-23 Stion Corporation Sulfide species treatment of thin film photovoltaic cell and manufacturing method
US8435826B1 (en) 2008-10-06 2013-05-07 Stion Corporation Bulk sulfide species treatment of thin film photovoltaic cell and manufacturing method
US8168463B2 (en) 2008-10-17 2012-05-01 Stion Corporation Zinc oxide film method and structure for CIGS cell
WO2010054231A1 (en) * 2008-11-06 2010-05-14 Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University Laterally varying ii-vi alloys and uses thereof
US8344243B2 (en) 2008-11-20 2013-01-01 Stion Corporation Method and structure for thin film photovoltaic cell using similar material junction
US8354291B2 (en) 2008-11-24 2013-01-15 University Of Southern California Integrated circuits based on aligned nanotubes
US8169006B2 (en) * 2008-11-29 2012-05-01 Electronics And Telecommunications Research Institute Bio-sensor chip for detecting target material
US20100148213A1 (en) * 2008-12-12 2010-06-17 Yen-Wei Hsu Tunnel device
KR101539669B1 (en) * 2008-12-16 2015-07-27 삼성전자주식회사 Method of forming core-shell type structure and method of manufacturing transistor using the same
US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
FR2943450B1 (en) 2009-03-17 2011-03-18 Commissariat Energie Atomique HIGH RESOLUTION READING HEAD FOR OPTICAL DISK
US9195966B2 (en) * 2009-03-27 2015-11-24 T-Mobile Usa, Inc. Managing contact groups from subset of user contacts
US8577350B2 (en) 2009-03-27 2013-11-05 T-Mobile Usa, Inc. Managing communications utilizing communication categories
USD631888S1 (en) 2009-03-27 2011-02-01 T-Mobile Usa, Inc. Portion of a display screen with a user interface
US9210247B2 (en) 2009-03-27 2015-12-08 T-Mobile Usa, Inc. Managing contact groups from subset of user contacts
USD631890S1 (en) 2009-03-27 2011-02-01 T-Mobile Usa, Inc. Portion of a display screen with a user interface
USD631889S1 (en) 2009-03-27 2011-02-01 T-Mobile Usa, Inc. Portion of a display screen with a user interface
US9355382B2 (en) 2009-03-27 2016-05-31 T-Mobile Usa, Inc. Group based information displays
US9369542B2 (en) 2009-03-27 2016-06-14 T-Mobile Usa, Inc. Network-based processing of data requests for contact information
USD631891S1 (en) 2009-03-27 2011-02-01 T-Mobile Usa, Inc. Portion of a display screen with a user interface
USD631887S1 (en) 2009-03-27 2011-02-01 T-Mobile Usa, Inc. Portion of a display screen with a user interface
US7902541B2 (en) * 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
US8013324B2 (en) * 2009-04-03 2011-09-06 International Business Machines Corporation Structurally stabilized semiconductor nanowire
US7943530B2 (en) * 2009-04-03 2011-05-17 International Business Machines Corporation Semiconductor nanowires having mobility-optimized orientations
US8237150B2 (en) * 2009-04-03 2012-08-07 International Business Machines Corporation Nanowire devices for enhancing mobility through stress engineering
US20110089402A1 (en) * 2009-04-10 2011-04-21 Pengfei Qi Composite Nanorod-Based Structures for Generating Electricity
JP6236202B2 (en) 2009-05-01 2017-11-22 ナノシス・インク. Matrix with functional groups for dispersion of nanostructures
JP5299105B2 (en) * 2009-06-16 2013-09-25 ソニー株式会社 Vanadium dioxide nanowire and method for producing the same, and nanowire device using vanadium dioxide nanowire
FR2947098A1 (en) * 2009-06-18 2010-12-24 Commissariat Energie Atomique METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER
US8507786B1 (en) 2009-06-27 2013-08-13 Stion Corporation Manufacturing method for patterning CIGS/CIS solar cells
US8623288B1 (en) 2009-06-29 2014-01-07 Nanosys, Inc. Apparatus and methods for high density nanowire growth
US8368125B2 (en) 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors
US8389393B2 (en) * 2009-07-29 2013-03-05 Massachusetts Institute Of Technology Nanoparticle synthesis
US8269257B2 (en) * 2009-07-29 2012-09-18 Massachusetts Institute Of Technology Nanowire synthesis
US8398772B1 (en) 2009-08-18 2013-03-19 Stion Corporation Method and structure for processing thin film PV cells with improved temperature uniformity
KR101016437B1 (en) * 2009-08-21 2011-02-21 한국과학기술연구원 Reconfigurable logic device using spin accumulation and diffusion
US8524527B2 (en) * 2009-09-25 2013-09-03 University Of Southern California High-performance single-crystalline N-type dopant-doped metal oxide nanowires for transparent thin film transistors and active matrix organic light-emitting diode displays
US20120199812A1 (en) * 2009-10-07 2012-08-09 University Of Florida Research Foundation, Incorporated Strain tunable silicon and germanium nanowire optoelectronic devices
US8980656B2 (en) 2009-10-21 2015-03-17 The Board Of Trustees Of The University Of Illinois Method of forming an array of high aspect ratio semiconductor nanostructures
US8809096B1 (en) 2009-10-22 2014-08-19 Stion Corporation Bell jar extraction tool method and apparatus for thin film photovoltaic materials
US8390705B2 (en) * 2009-10-27 2013-03-05 Hewlett-Packard Develoment Company, L.P. Nanowire photodiodes
US20110101302A1 (en) * 2009-11-05 2011-05-05 University Of Southern California Wafer-scale fabrication of separated carbon nanotube thin-film transistors
CN102050424B (en) * 2009-11-06 2013-11-06 清华大学 Method for preparing carbon nanotube thin film and method for preparing thin film transistor
WO2011066570A2 (en) * 2009-11-30 2011-06-03 California Institute Of Technology Semiconductor wire array structures, and solar cells and photodetectors based on such structures
US8563395B2 (en) * 2009-11-30 2013-10-22 The Royal Institute For The Advancement Of Learning/Mcgill University Method of growing uniform semiconductor nanowires without foreign metal catalyst and devices thereof
US8008146B2 (en) * 2009-12-04 2011-08-30 International Business Machines Corporation Different thickness oxide silicon nanowire field effect transistors
JP5753192B2 (en) 2009-12-22 2015-07-22 クナノ・アーベー Method for manufacturing a nanowire structure
KR101132273B1 (en) 2009-12-28 2012-04-02 재단법인대구경북과학기술원 Hybrid solar cell and method for fabricating the same
US8859880B2 (en) 2010-01-22 2014-10-14 Stion Corporation Method and structure for tiling industrial thin-film solar devices
US8263494B2 (en) 2010-01-25 2012-09-11 Stion Corporation Method for improved patterning accuracy for thin film photovoltaic panels
US9202954B2 (en) * 2010-03-03 2015-12-01 Q1 Nanosystems Corporation Nanostructure and photovoltaic cell implementing same
CN101807606B (en) * 2010-03-04 2011-05-25 吉林大学 n-type zinc oxide/p-type diamond heterojunction tunnel diode and manufacturing method thereof
US9263612B2 (en) 2010-03-23 2016-02-16 California Institute Of Technology Heterojunction wire array solar cells
US9096930B2 (en) 2010-03-29 2015-08-04 Stion Corporation Apparatus for manufacturing thin film photovoltaic devices
US20110267436A1 (en) * 2010-04-30 2011-11-03 Nauganeedles Llc Nanowire Bonding Method and Apparatus
CN102971452B (en) * 2010-05-11 2017-03-29 昆南诺股份有限公司 The vapor- phase synthesis of line
US8445337B2 (en) 2010-05-12 2013-05-21 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8519479B2 (en) 2010-05-12 2013-08-27 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8420455B2 (en) 2010-05-12 2013-04-16 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8461061B2 (en) 2010-07-23 2013-06-11 Stion Corporation Quartz boat method and apparatus for thin film thermal treatment
US8628997B2 (en) 2010-10-01 2014-01-14 Stion Corporation Method and device for cadmium-free solar cells
KR101223233B1 (en) * 2010-10-13 2013-01-21 서울대학교산학협력단 An integrated direct-band semiconductor nanowire on mechanical structures to facilitate measurement of structures displacement
US8462333B2 (en) * 2010-10-15 2013-06-11 Hewlett-Packard Development Company, L.P. Apparatus for performing SERS
US8998606B2 (en) 2011-01-14 2015-04-07 Stion Corporation Apparatus and method utilizing forced convection for uniform thermal treatment of thin film devices
US8728200B1 (en) 2011-01-14 2014-05-20 Stion Corporation Method and system for recycling processing gas for selenization of thin film photovoltaic materials
US8593629B2 (en) 2011-02-17 2013-11-26 Hewlett-Packard Development Company, L.P. Apparatus for performing SERS
US8692230B2 (en) 2011-03-29 2014-04-08 University Of Southern California High performance field-effect transistors
FR2973936B1 (en) * 2011-04-05 2014-01-31 Commissariat Energie Atomique METHOD OF SELECTIVE GROWTH ON SEMICONDUCTOR STRUCTURE
CN102259833B (en) * 2011-05-24 2014-11-05 黄辉 Preparation method of nano wire device based on nano wire cross connection
US8860137B2 (en) 2011-06-08 2014-10-14 University Of Southern California Radio frequency devices based on carbon nanomaterials
WO2012170630A2 (en) 2011-06-10 2012-12-13 President And Fellows Of Harvard College Nanoscale wires, nanoscale wire fet devices, and nanotube-electronic hybrid devices for sensing and other applications
KR20130010344A (en) * 2011-07-18 2013-01-28 삼성전자주식회사 Metal nanowire formed with gold nanocluster on the surface for binding a target material and method for binding the metal nanowire with the target material
US8848183B2 (en) 2011-07-22 2014-09-30 Hewlett-Packard Development Company, L.P. Apparatus having nano-fingers of different physical characteristics
EP3978426A1 (en) 2011-07-26 2022-04-06 OneD Material, Inc. Nanostructured battery active materials and methods of producing same
US9377409B2 (en) 2011-07-29 2016-06-28 Hewlett-Packard Development Company, L.P. Fabricating an apparatus for use in a sensing application
US8436445B2 (en) 2011-08-15 2013-05-07 Stion Corporation Method of manufacture of sodium doped CIGS/CIGSS absorber layers for high efficiency photovoltaic devices
WO2013052541A2 (en) * 2011-10-04 2013-04-11 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Quantum dots, rods, wires, sheets, and ribbons, and uses thereof
US8772910B2 (en) 2011-11-29 2014-07-08 International Business Machines Corporation Doping carbon nanotubes and graphene for improving electronic mobility
US8895417B2 (en) 2011-11-29 2014-11-25 International Business Machines Corporation Reducing contact resistance for field-effect transistor devices
TWI472069B (en) 2011-12-19 2015-02-01 Ind Tech Res Inst Thermoelectric composite material
TWI559561B (en) * 2011-12-28 2016-11-21 國立台北科技大學 Array electrospinning for dye sensitized solar cells
JP2015511208A (en) 2012-01-01 2015-04-16 トラセンス システムズ リミテッド Nanostructure and method for producing the same
US9545612B2 (en) 2012-01-13 2017-01-17 California Institute Of Technology Solar fuel generator
US10026560B2 (en) 2012-01-13 2018-07-17 The California Institute Of Technology Solar fuels generator
US9476129B2 (en) 2012-04-02 2016-10-25 California Institute Of Technology Solar fuels generator
EP2809837A4 (en) * 2012-02-03 2015-11-11 Qunano Ab High-throughput continuous gas-phase synthesis of nanowires with tunable properties
WO2013126432A1 (en) 2012-02-21 2013-08-29 California Institute Of Technology Axially-integrated epitaxially-grown tandem wire arrays
WO2013152132A1 (en) 2012-04-03 2013-10-10 The California Institute Of Technology Semiconductor structures for fuel generation
WO2013154490A2 (en) * 2012-04-12 2013-10-17 Sol Voltaics Ab Methods of nanowire functionalization, dispersion and attachment
JP2013239690A (en) * 2012-04-16 2013-11-28 Sharp Corp Superlattice structure, semiconductor device and semiconductor light emitting device including the superlattice structure, and method of making the superlattice structure
JP6297026B2 (en) 2012-04-23 2018-03-20 シーメンス・ヘルスケア・ダイアグノスティックス・インコーポレーテッドSiemens Healthcare Diagnostics Inc. Sensor assembly and manufacturing method thereof
WO2013166259A1 (en) 2012-05-03 2013-11-07 President And Fellows Of Harvard College Nanoscale sensors for intracellular and other applications
DE202012102039U1 (en) * 2012-06-04 2013-02-08 Ramot At Tel Aviv University Ltd. nanostructure
US9139770B2 (en) 2012-06-22 2015-09-22 Nanosys, Inc. Silicone ligands for stabilizing quantum dot films
TWI596188B (en) 2012-07-02 2017-08-21 奈米系統股份有限公司 Highly luminescent nanostructures and methods of producing same
FR2993509B1 (en) * 2012-07-17 2015-03-20 Airbus ELECTRONIC DEVICE FOR PROTECTION AGAINST LIGHTENING OF A PILOT OR DRIVER.
US9457128B2 (en) 2012-09-07 2016-10-04 President And Fellows Of Harvard College Scaffolds comprising nanoelectronic components for cells, tissues, and other applications
US9786850B2 (en) 2012-09-07 2017-10-10 President And Fellows Of Harvard College Methods and systems for scaffolds comprising nanoelectronic components
WO2014043341A1 (en) 2012-09-12 2014-03-20 President And Fellows Of Harvard College Nanoscale field-effect transistors for biomolecular sensors and other applications
FR3000292B1 (en) * 2012-12-20 2015-02-27 Commissariat Energie Atomique PROCESS FOR OBTAINING AT LEAST ONE SILICON-BASED NANOELEMENT IN A SILICON OXIDE WAFER, METHOD FOR MANUFACTURING A DEVICE USING THE PROCESS FOR OBTAINING THE SAME
US9553223B2 (en) 2013-01-24 2017-01-24 California Institute Of Technology Method for alignment of microwires
US9082911B2 (en) 2013-01-28 2015-07-14 Q1 Nanosystems Corporation Three-dimensional metamaterial device with photovoltaic bristles
US9954126B2 (en) 2013-03-14 2018-04-24 Q1 Nanosystems Corporation Three-dimensional photovoltaic devices including cavity-containing cores and methods of manufacture
US20140264998A1 (en) 2013-03-14 2014-09-18 Q1 Nanosystems Corporation Methods for manufacturing three-dimensional metamaterial devices with photovoltaic bristles
WO2014159927A2 (en) 2013-03-14 2014-10-02 Nanosys, Inc. Method for solventless quantum dot exchange
FR3004000B1 (en) * 2013-03-28 2016-07-15 Aledia ELECTROLUMINESCENT DEVICE WITH INTEGRATED SENSOR AND METHOD FOR CONTROLLING THE TRANSMISSION OF THE DEVICE
JP6514231B2 (en) * 2014-01-06 2019-05-15 ナノコ テクノロジーズ リミテッド Cadmium-free quantum dot nanoparticles
US10315191B2 (en) * 2014-03-24 2019-06-11 Hong Kong Polytechnic University Photocatalyst
CN103869103B (en) * 2014-03-27 2016-04-06 上海华力微电子有限公司 Probe unit of microscope with atomic force
US9287516B2 (en) * 2014-04-07 2016-03-15 International Business Machines Corporation Forming pn junction contacts by different dielectrics
US10167193B2 (en) 2014-09-23 2019-01-01 Vanderbilt University Ferroelectric agglomerates and methods and uses related thereto
WO2016069831A1 (en) 2014-10-30 2016-05-06 President And Fellows Of Harvard College Nanoscale wires with tip-localized junctions
US9379327B1 (en) 2014-12-16 2016-06-28 Carbonics Inc. Photolithography based fabrication of 3D structures
CN104538457A (en) * 2015-01-15 2015-04-22 京东方科技集团股份有限公司 Thin film transistor, manufacturing method of thin film transistor, array substrate and display device
WO2016161246A1 (en) * 2015-04-03 2016-10-06 President And Fellows Of Harvard College Nanoscale wires with external layers for sensors and other applications
CN104779275B (en) * 2015-04-30 2017-11-28 湖北工业大学 Autoexcitation spin single electron Electromagnetic Environmental Effect transistor, preparation method and application
CN105088346B (en) * 2015-08-19 2016-06-22 宁波工程学院 A kind of P doping SiC nanowire with superelevation draw ratio and preparation method thereof
KR101742073B1 (en) * 2015-12-01 2017-06-01 주식회사 페타룩스 Electronic device based on copper halide semiconductor, and memory device and logic device having the same
KR101845139B1 (en) * 2015-12-29 2018-05-18 전자부품연구원 Avalanche photodiode using silicon nanowire and silicon nanowire photomultiplier using the same
CN105862122B (en) * 2016-05-09 2018-08-03 北京大学 Indium antimonide nano wire based on multistep Glancing angledeposition is prepared and additive Mn method
US11728477B2 (en) 2016-07-15 2023-08-15 Oned Material, Inc. Manufacturing apparatus and method for making silicon nanowires on carbon based powders for use in batteries
DE102016010764A1 (en) * 2016-09-08 2018-03-08 Forschungszentrum Jülich GmbH Device for measuring small potentials of a sample, method for producing the device and use of the device
US10737938B2 (en) 2016-10-21 2020-08-11 UVic Industry Partnership Inc. Nanowire chain devices, systems, and methods of production
US11111399B2 (en) 2016-10-21 2021-09-07 Quirklogic, Inc. Materials and methods for conductive thin films
US9881835B1 (en) * 2016-10-21 2018-01-30 Uvic Industry Partnerships Inc. Nanowire devices, systems, and methods of production
US10782014B2 (en) 2016-11-11 2020-09-22 Habib Technologies LLC Plasmonic energy conversion device for vapor generation
CN106783809B (en) * 2016-11-23 2019-03-01 华东师范大学 A kind of coaxial capacitor and preparation method of spinning
RU178317U1 (en) * 2017-02-17 2018-03-29 Федеральное государственное бюджетное образовательное учреждение высшего образования "Московский государственный университет имени М.В. Ломоносова" (МГУ) FIELD TRANSISTOR FOR DETERMINING BIOLOGICALLY ACTIVE COMPOUNDS
US10243156B2 (en) 2017-03-16 2019-03-26 International Business Machines Corporation Placement of carbon nanotube guided by DSA patterning
CN107119323B (en) * 2017-04-27 2019-08-06 云南北方驰宏光电有限公司 A kind of doping modification method of CVDZnS crystalline material
KR101940067B1 (en) * 2017-08-24 2019-01-18 건국대학교 산학협력단 Preparation Method for Wire with hollow structure
KR101950114B1 (en) * 2017-10-27 2019-02-19 고려대학교 산학협력단 Semiconductor Nanowire Photoelectric Device
KR102015278B1 (en) * 2017-10-30 2019-08-28 한국생산기술연구원 A method for forming a nanowire pattern using a mold having a channel
TWI638452B (en) * 2017-12-22 2018-10-11 林嘉洤 Room temperature oscillator
CN108914086B (en) * 2018-07-17 2020-05-22 武汉工程大学 Iron-doped diamond diluted magnetic semiconductor and preparation method thereof
WO2020154511A1 (en) * 2019-01-23 2020-07-30 University Of Washington Indium phosphorus quantum dots, clusters, and related methods
US20220213425A1 (en) 2019-06-24 2022-07-07 President And Fellows Of Harvard Cell scaffold comprising an electronic circuit
CN112410933B (en) * 2019-08-20 2023-01-06 Tcl科技集团股份有限公司 Nano material and preparation method thereof and quantum dot light-emitting diode
CN110320195B (en) * 2019-08-21 2021-12-28 合肥工业大学 Colorimetric fluorescent probe and preparation method and application thereof
CN111101192B (en) * 2020-01-09 2021-05-07 西北工业大学 Method for preparing single crystal black phosphorus nanowire by using template method
MX2022013050A (en) * 2020-04-19 2023-01-24 John J Daniels Mask-based diagnostic system using exhaled breath condensate.
CN111663167A (en) * 2020-06-16 2020-09-15 合肥工业大学 Metal wire preparation method based on BPE technology
CN111952322B (en) * 2020-08-14 2022-06-03 电子科技大学 Flexible semiconductor film with periodically adjustable buckling structure and preparation method thereof
CN112216772B (en) * 2020-09-07 2022-03-08 深圳远芯光路科技有限公司 III-group nitride nanowire flexible light-emitting diode and preparation method thereof
CN112816528A (en) * 2021-02-01 2021-05-18 合肥艾创微电子科技有限公司 Perception storage integrated bionic tactile fiber and preparation method thereof
CN113066869B (en) * 2021-03-16 2021-12-10 扬州国宇电子有限公司 Fast recovery diode chip and preparation method thereof
CN113096749B (en) * 2021-06-10 2021-11-05 武汉大学深圳研究院 Multi-scale coupling simulation method for preparing n-type co-doped diamond semiconductor material

Family Cites Families (227)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444100A (en) * 1963-10-30 1969-05-13 Trancoa Chem Corp Radiation resistant semiconductor grade silicon containing a metal oxide
US3873360A (en) * 1971-11-26 1975-03-25 Western Electric Co Method of depositing a metal on a surface of a substrate
US3873359A (en) * 1971-11-26 1975-03-25 Western Electric Co Method of depositing a metal on a surface of a substrate
US3900614A (en) * 1971-11-26 1975-08-19 Western Electric Co Method of depositing a metal on a surface of a substrate
US4190631A (en) * 1978-09-21 1980-02-26 Western Electric Company, Incorporated Double crucible crystal growing apparatus
JPS6194042A (en) 1984-10-16 1986-05-12 Matsushita Electric Ind Co Ltd Molecular construction and its manufacture
US4939556A (en) 1986-07-10 1990-07-03 Canon Kabushiki Kaisha Conductor device
CA1336110C (en) * 1989-02-03 1995-06-27 Robert Gregory Swisher Polymeric-containing compositions with improved oxidative stability
US5089545A (en) 1989-02-12 1992-02-18 Biotech International, Inc. Switching and memory elements from polyamino acids and the method of their assembly
US5023139A (en) * 1989-04-04 1991-06-11 Research Corporation Technologies, Inc. Nonlinear optical materials
EP0605408A1 (en) 1989-10-18 1994-07-13 Research Corporation Technologies, Inc. Coated particles and methods of coating particles
US5196212A (en) * 1990-05-08 1993-03-23 Knoblach Gerald M Electric alignment of fibers for the manufacture of composite materials
US5225366A (en) * 1990-06-22 1993-07-06 The United States Of America As Represented By The Secretary Of The Navy Apparatus for and a method of growing thin films of elemental semiconductors
US5332910A (en) 1991-03-22 1994-07-26 Hitachi, Ltd. Semiconductor optical device with nanowhiskers
US5274602A (en) 1991-10-22 1993-12-28 Florida Atlantic University Large capacity solid-state memory
JP3243303B2 (en) * 1991-10-28 2002-01-07 ゼロックス・コーポレーション Quantum confined semiconductor light emitting device and method of manufacturing the same
EP0543391B1 (en) * 1991-11-22 2000-08-30 Canon Kabushiki Kaisha Photoelectric conversion device and method of driving the same
JP2697474B2 (en) * 1992-04-30 1998-01-14 松下電器産業株式会社 Manufacturing method of microstructure
US5475341A (en) 1992-06-01 1995-12-12 Yale University Sub-nanoscale electronic systems and devices
US5252835A (en) 1992-07-17 1993-10-12 President And Trustees Of Harvard College Machining oxide thin-films with an atomic force microscope: pattern and object formation on the nanometer scale
US5453970A (en) 1993-07-13 1995-09-26 Rust; Thomas F. Molecular memory medium and molecular memory disk drive for storing information using a tunnelling probe
WO1995002709A2 (en) 1993-07-15 1995-01-26 President And Fellows Of Harvard College EXTENDED NITRIDE MATERIAL COMPRISING β-C3N¿4?
IT1271141B (en) * 1993-07-29 1997-05-27 Promox S R L PROCEDURE FOR THE POTABILIZATION OF WATER INTENDED FOR HUMAN CONSUMPTION
US5962863A (en) * 1993-09-09 1999-10-05 The United States Of America As Represented By The Secretary Of The Navy Laterally disposed nanostructures of silicon on an insulating substrate
US5900160A (en) * 1993-10-04 1999-05-04 President And Fellows Of Harvard College Methods of etching articles via microcontact printing
US5512131A (en) 1993-10-04 1996-04-30 President And Fellows Of Harvard College Formation of microstamped patterns on surfaces and derivative articles
US5776748A (en) * 1993-10-04 1998-07-07 President And Fellows Of Harvard College Method of formation of microstamped patterns on plates for adhesion of cells and other biological materials, devices and uses therefor
US6180239B1 (en) * 1993-10-04 2001-01-30 President And Fellows Of Harvard College Microcontact printing on surfaces and derivative articles
US5936703A (en) * 1993-10-13 1999-08-10 Nof Corporation Alkoxysilane compound, surface processing solution and contact lens
JP3254865B2 (en) * 1993-12-17 2002-02-12 ソニー株式会社 Camera device
EP0659911A1 (en) 1993-12-23 1995-06-28 International Business Machines Corporation Method to form a polycrystalline film on a substrate
CN1040043C (en) 1994-04-29 1998-09-30 武汉大学 Ultramicro nm electrode and ultramicro sensor
JP3332130B2 (en) * 1994-05-16 2002-10-07 シャープ株式会社 Image display device
US5620850A (en) 1994-09-26 1997-04-15 President And Fellows Of Harvard College Molecular recognition at surfaces derivatized with self-assembled monolayers
AU3894595A (en) * 1994-11-08 1996-05-31 Spectra Science Corporation Semiconductor nanocrystal display materials and display apparatus employing same
US5581091A (en) * 1994-12-01 1996-12-03 Moskovits; Martin Nanoelectric devices
US5866434A (en) * 1994-12-08 1999-02-02 Meso Scale Technology Graphitic nanotubes in luminescence assays
US5449627A (en) 1994-12-14 1995-09-12 United Microelectronics Corporation Lateral bipolar transistor and FET compatible process for making it
US5539214A (en) * 1995-02-06 1996-07-23 Regents Of The University Of California Quantum bridges fabricated by selective etching of superlattice structures
US5524092A (en) * 1995-02-17 1996-06-04 Park; Jea K. Multilayered ferroelectric-semiconductor memory-device
EP0812434B1 (en) 1995-03-01 2013-09-18 President and Fellows of Harvard College Microcontact printing on surfaces and derivative articles
BR9607193B1 (en) 1995-03-10 2009-01-13 multispecific multispecific electrochemical test.
US5747180A (en) 1995-05-19 1998-05-05 University Of Notre Dame Du Lac Electrochemical synthesis of quasi-periodic quantum dot and nanostructure arrays
US5824470A (en) 1995-05-30 1998-10-20 California Institute Of Technology Method of preparing probes for sensing and manipulating microscopic environments and structures
JP2953996B2 (en) * 1995-05-31 1999-09-27 日本電気株式会社 Metal-coated carbon nanotube and method for producing the same
US5751156A (en) 1995-06-07 1998-05-12 Yale University Mechanically controllable break transducer
US6190634B1 (en) * 1995-06-07 2001-02-20 President And Fellows Of Harvard College Carbide nanomaterials
US5757038A (en) 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
WO1997019208A1 (en) * 1995-11-22 1997-05-29 Northwestern University Method of encapsulating a material in a carbon nanotube
JP3469392B2 (en) * 1995-11-22 2003-11-25 富士ゼロックス株式会社 Reproducible image recording medium
US6445006B1 (en) * 1995-12-20 2002-09-03 Advanced Technology Materials, Inc. Microelectronic and microelectromechanical devices comprising carbon nanotube components, and methods of making same
US6538262B1 (en) * 1996-02-02 2003-03-25 The Regents Of The University Of California Nanotube junctions
US5897945A (en) 1996-02-26 1999-04-27 President And Fellows Of Harvard College Metal oxide nanorods
US6036774A (en) 1996-02-26 2000-03-14 President And Fellows Of Harvard College Method of producing metal oxide nanorods
KR100469868B1 (en) 1996-03-06 2005-07-08 하이페리온 커탤리시스 인터내셔널 인코포레이티드 Functionalized Nanotubes
DE19610115C2 (en) 1996-03-14 2000-11-23 Fraunhofer Ges Forschung Detection of molecules and molecular complexes
DE69707853T2 (en) 1996-03-15 2002-06-27 Harvard College METHOD FOR SHAPING OBJECTS AND MICROSTRUCTURING SURFACES BY MOLDING WITH CAPILLARY EFFECT
US6355198B1 (en) * 1996-03-15 2002-03-12 President And Fellows Of Harvard College Method of forming articles including waveguides via capillary micromolding and microtransfer molding
US6060121A (en) 1996-03-15 2000-05-09 President And Fellows Of Harvard College Microcontact printing of catalytic colloids
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
RU2099808C1 (en) 1996-04-01 1997-12-20 Евгений Инвиевич Гиваргизов Process of growing of oriented systems of whiskers and gear for its implementation ( versions )
US5942443A (en) 1996-06-28 1999-08-24 Caliper Technologies Corporation High throughput screening assay systems in microscale fluidic devices
US6187214B1 (en) * 1996-05-13 2001-02-13 Universidad De Seville Method and device for production of components for microfabrication
US5726524A (en) * 1996-05-31 1998-03-10 Minnesota Mining And Manufacturing Company Field emission device having nanostructured emitters
AU4055297A (en) * 1996-08-08 1998-02-25 William Marsh Rice University Macroscopically manipulable nanoscale devices made from nanotube assemblies
JPH10106960A (en) * 1996-09-25 1998-04-24 Sony Corp Manufacture of quantum thin line
IL119719A0 (en) * 1996-11-29 1997-02-18 Yeda Res & Dev Inorganic fullerene-like structures of metal chalcogenides
US6038060A (en) 1997-01-16 2000-03-14 Crowley; Robert Joseph Optical antenna array for harmonic generation, mixing and signal amplification
US5908692A (en) * 1997-01-23 1999-06-01 Wisconsin Alumni Research Foundation Ordered organic monolayers and methods of preparation thereof
US5997832A (en) * 1997-03-07 1999-12-07 President And Fellows Of Harvard College Preparation of carbide nanorods
US6683783B1 (en) * 1997-03-07 2004-01-27 William Marsh Rice University Carbon fibers formed from single-wall carbon nanotubes
CA2283502C (en) 1997-03-07 2005-06-14 William Marsh Rice University Carbon fibers formed from singlewall carbon nanotubes
JP3183845B2 (en) 1997-03-21 2001-07-09 財団法人ファインセラミックスセンター Method for producing carbon nanotube and carbon nanotube film
US5847565A (en) 1997-03-31 1998-12-08 Council Of Scientific And Industrial Research Logic device
US6359288B1 (en) * 1997-04-24 2002-03-19 Massachusetts Institute Of Technology Nanowire arrays
US5864823A (en) * 1997-06-25 1999-01-26 Virtel Corporation Integrated virtual telecommunication system for E-commerce
US6069380A (en) 1997-07-25 2000-05-30 Regents Of The University Of Minnesota Single-electron floating-gate MOS memory
US7001996B1 (en) * 1997-08-21 2006-02-21 The United States Of America As Represented By The Secretary Of The Army Enzymatic template polymerization
US6187165B1 (en) * 1997-10-02 2001-02-13 The John Hopkins University Arrays of semi-metallic bismuth nanowires and fabrication techniques therefor
US5903010A (en) 1997-10-29 1999-05-11 Hewlett-Packard Company Quantum wire switch and switching method
JP3740295B2 (en) * 1997-10-30 2006-02-01 キヤノン株式会社 Carbon nanotube device, manufacturing method thereof, and electron-emitting device
US6004444A (en) 1997-11-05 1999-12-21 The Trustees Of Princeton University Biomimetic pathways for assembling inorganic thin films and oriented mesoscopic silicate patterns through guided growth
US6123819A (en) 1997-11-12 2000-09-26 Protiveris, Inc. Nanoelectrode arrays
US6762056B1 (en) * 1997-11-12 2004-07-13 Protiveris, Inc. Rapid method for determining potential binding sites of a protein
US20030135971A1 (en) * 1997-11-12 2003-07-24 Michael Liberman Bundle draw based processing of nanofibers and method of making
US6207392B1 (en) 1997-11-25 2001-03-27 The Regents Of The University Of California Semiconductor nanocrystal probes for biological applications and process for making and using such probes
JP3902883B2 (en) * 1998-03-27 2007-04-11 キヤノン株式会社 Nanostructure and manufacturing method thereof
JP2000041320A (en) * 1998-05-20 2000-02-08 Yazaki Corp Grommet
US6287765B1 (en) * 1998-05-20 2001-09-11 Molecular Machines, Inc. Methods for detecting and identifying single molecules
EP0962773A1 (en) 1998-06-03 1999-12-08 Mark Howard Jones Electrochemical based assay processes instrument and labels
US6159742A (en) 1998-06-05 2000-12-12 President And Fellows Of Harvard College Nanometer-scale microscopy probes
US6203864B1 (en) 1998-06-08 2001-03-20 Nec Corporation Method of forming a heterojunction of a carbon nanotube and a different material, method of working a filament of a nanotube
US6346189B1 (en) 1998-08-14 2002-02-12 The Board Of Trustees Of The Leland Stanford Junior University Carbon nanotube structures made using catalyst islands
US7416699B2 (en) 1998-08-14 2008-08-26 The Board Of Trustees Of The Leland Stanford Junior University Carbon nanotube devices
DE69941294D1 (en) 1998-09-18 2009-10-01 Univ Rice William M CHEMICAL DERIVATION OF UNIFORM CARBON NANOTUBES TO FACILITATE THEIR SOLVATATION AND USE OF DERIVATED NANORESE
JP4630459B2 (en) 1998-09-24 2011-02-09 インディアナ・ユニバーシティ・リサーチ・アンド・テクノロジー・コーポレーション Water-soluble luminescent quantum dots and biomolecular conjugates thereof
AU6267299A (en) 1998-09-28 2000-04-17 Xidex Corporation Method for manufacturing carbon nanotubes as functional elements of mems devices
DE19849196A1 (en) * 1998-10-26 2000-04-27 Degussa Process for neutralizing and reducing residual halogen content in alkoxysilanes or alkoxysilane-based compositions
US6705152B2 (en) 2000-10-24 2004-03-16 Nanoproducts Corporation Nanostructured ceramic platform for micromachined devices and device arrays
US6468657B1 (en) 1998-12-04 2002-10-22 The Regents Of The University Of California Controllable ion-exchange membranes
JP3754568B2 (en) 1999-01-29 2006-03-15 シャープ株式会社 Quantum wire manufacturing method
US20020013031A1 (en) * 1999-02-09 2002-01-31 Kuen-Jian Chen Method of improving the reliability of gate oxide layer
US6624420B1 (en) 1999-02-18 2003-09-23 University Of Central Florida Lutetium yttrium orthosilicate single crystal scintillator detector
US6149819A (en) 1999-03-02 2000-11-21 United States Filter Corporation Air and water purification using continuous breakpoint halogenation and peroxygenation
US6143184A (en) 1999-03-02 2000-11-07 United States Filter Corporation Air and water purification using continuous breakpoint halogenation
US6459095B1 (en) 1999-03-29 2002-10-01 Hewlett-Packard Company Chemically synthesized and assembled electronics devices
US7030408B1 (en) * 1999-03-29 2006-04-18 Hewlett-Packard Development Company, L.P. Molecular wire transistor (MWT)
US6256767B1 (en) 1999-03-29 2001-07-03 Hewlett-Packard Company Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
US6314019B1 (en) 1999-03-29 2001-11-06 Hewlett-Packard Company Molecular-wire crossbar interconnect (MWCI) for signal routing and communications
US6128214A (en) 1999-03-29 2000-10-03 Hewlett-Packard Molecular wire crossbar memory
US6270074B1 (en) * 1999-04-14 2001-08-07 Hewlett-Packard Company Print media vacuum holddown
US7112315B2 (en) 1999-04-14 2006-09-26 The Regents Of The University Of California Molecular nanowires from single walled carbon nanotubes
AUPP976499A0 (en) 1999-04-16 1999-05-06 Commonwealth Scientific And Industrial Research Organisation Multilayer carbon nanotube films
US20030124509A1 (en) * 1999-06-03 2003-07-03 Kenis Paul J.A. Laminar flow patterning and articles made thereby
US6313015B1 (en) * 1999-06-08 2001-11-06 City University Of Hong Kong Growth method for silicon nanowires and nanoparticle chains from silicon monoxide
US6361861B2 (en) * 1999-06-14 2002-03-26 Battelle Memorial Institute Carbon nanotubes on a substrate
US6536106B1 (en) * 1999-06-30 2003-03-25 The Penn State Research Foundation Electric field assisted assembly process
AU782000B2 (en) 1999-07-02 2005-06-23 President And Fellows Of Harvard College Nanoscopic wire-based devices, arrays, and methods of their manufacture
US6322713B1 (en) 1999-07-15 2001-11-27 Agere Systems Guardian Corp. Nanoscale conductive connectors and method for making same
US6538367B1 (en) * 1999-07-15 2003-03-25 Agere Systems Inc. Field emitting device comprising field-concentrating nanoconductor assembly and method for making the same
US6465132B1 (en) 1999-07-22 2002-10-15 Agere Systems Guardian Corp. Article comprising small diameter nanowires and method for making the same
US6286226B1 (en) * 1999-09-24 2001-09-11 Agere Systems Guardian Corp. Tactile sensor comprising nanowires and method for making the same
US6340822B1 (en) * 1999-10-05 2002-01-22 Agere Systems Guardian Corp. Article comprising vertically nano-interconnected circuit devices and method for making the same
US6741019B1 (en) * 1999-10-18 2004-05-25 Agere Systems, Inc. Article comprising aligned nanowires
US6437329B1 (en) * 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Use of carbon nanotubes as chemical sensors by incorporation of fluorescent molecules within the tube
US20050037374A1 (en) * 1999-11-08 2005-02-17 Melker Richard J. Combined nanotechnology and sensor technologies for simultaneous diagnosis and treatment
US6974706B1 (en) 2003-01-16 2005-12-13 University Of Florida Research Foundation, Inc. Application of biosensors for diagnosis and treatment of disease
US6248674B1 (en) * 2000-02-02 2001-06-19 Hewlett-Packard Company Method of aligning nanowires
EP1263887A1 (en) * 2000-02-04 2002-12-11 Massachusetts Institute Of Technology Insulated nanoscopic pathways, compositions and devices of the same
US7335603B2 (en) * 2000-02-07 2008-02-26 Vladimir Mancevski System and method for fabricating logic devices comprising carbon nanotube transistors
US6503375B1 (en) * 2000-02-11 2003-01-07 Applied Materials, Inc Electroplating apparatus using a perforated phosphorus doped consumable anode
US6294450B1 (en) 2000-03-01 2001-09-25 Hewlett-Packard Company Nanoscale patterning for the formation of extensive wires
CA2404296A1 (en) * 2000-03-22 2001-09-27 University Of Massachusetts Nanocylinder arrays
US6720240B2 (en) * 2000-03-29 2004-04-13 Georgia Tech Research Corporation Silicon based nanospheres and nanowires
JP4089122B2 (en) 2000-03-31 2008-05-28 株式会社リコー Contact charger manufacturing method, contact charger obtained by the method, charging method and image recording apparatus
US6479028B1 (en) 2000-04-03 2002-11-12 The Regents Of The University Of California Rapid synthesis of carbon nanotubes and carbon encapsulated metal nanoparticles by a displacement reaction
US7323143B2 (en) * 2000-05-25 2008-01-29 President And Fellows Of Harvard College Microfluidic systems including three-dimensionally arrayed channel networks
US6440637B1 (en) 2000-06-28 2002-08-27 The Aerospace Corporation Electron beam lithography method forming nanocrystal shadowmasks and nanometer etch masks
EP1170799A3 (en) 2000-07-04 2009-04-01 Infineon Technologies AG Electronic device and method of manufacture of an electronic device
US6468677B1 (en) 2000-08-01 2002-10-22 Premark Rwp Holdings Inc. Electroluminescent high pressure laminate
US20060175601A1 (en) * 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
JP5013650B2 (en) 2000-08-22 2012-08-29 プレジデント・アンド・フェローズ・オブ・ハーバード・カレッジ Doped elongated semiconductors, growth of such semiconductors, devices containing such semiconductors, and the manufacture of such devices
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
WO2002022889A2 (en) 2000-09-11 2002-03-21 President And Fellows Of Harvard College Direct haplotyping using carbon nanotube probes
WO2002022499A1 (en) * 2000-09-18 2002-03-21 President And Fellows Of Harvard College Fabrication of nanotube microscopy tips
US6743408B2 (en) * 2000-09-29 2004-06-01 President And Fellows Of Harvard College Direct growth of nanotubes, and their use in nanotweezers
CA2425412A1 (en) 2000-10-10 2002-04-18 Bioforce Nanosciences, Inc. Nanoscale sensor
JP3811004B2 (en) * 2000-11-26 2006-08-16 喜萬 中山 Conductive scanning microscope probe
EP1342075B1 (en) * 2000-12-11 2008-09-10 President And Fellows Of Harvard College Device contaning nanosensors for detecting an analyte and its method of manufacture
WO2002048768A2 (en) * 2000-12-12 2002-06-20 Corning Incorporated Optical fiber with very high negative dispersion slope
US20020084502A1 (en) * 2000-12-29 2002-07-04 Jin Jang Carbon nanotip and fabricating method thereof
US6958216B2 (en) 2001-01-10 2005-10-25 The Trustees Of Boston College DNA-bridged carbon nanotube arrays
US6586095B2 (en) * 2001-01-12 2003-07-01 Georgia Tech Research Corp. Semiconducting oxide nanostructures
WO2002093738A2 (en) * 2001-01-19 2002-11-21 California Institute Of Technology Carbon nanobimorph actuator and sensor
JP2004527905A (en) 2001-03-14 2004-09-09 ユニバーシティー オブ マサチューセッツ Nano manufacturing
WO2002095099A1 (en) * 2001-03-29 2002-11-28 Stanford University Noncovalent sidewall functionalization of carbon nanotubes
WO2002080360A1 (en) 2001-03-30 2002-10-10 California Institute Of Technology Pattern-aligned carbon nanotube growth and tunable resonator apparatus
JP2004532133A (en) * 2001-03-30 2004-10-21 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・カリフォルニア Method for assembling nanostructures and nanowires and device assembled therefrom
US7459312B2 (en) 2001-04-18 2008-12-02 The Board Of Trustees Of The Leland Stanford Junior University Photodesorption in carbon nanotubes
US7232460B2 (en) * 2001-04-25 2007-06-19 Xillus, Inc. Nanodevices, microdevices and sensors on in-vivo structures and method for the same
US6902720B2 (en) * 2001-05-10 2005-06-07 Worcester Polytechnic Institute Cyclic peptide structures for molecular scale electronic and photonic devices
US7132275B2 (en) 2001-05-14 2006-11-07 The John Hopkins University Multifunctional magnetic nanowires
CA2447728A1 (en) 2001-05-18 2003-01-16 President And Fellows Of Harvard College Nanoscale wires and related devices
US20030048619A1 (en) * 2001-06-15 2003-03-13 Kaler Eric W. Dielectrophoretic assembling of electrically functional microwires
US6846565B2 (en) * 2001-07-02 2005-01-25 Board Of Regents, The University Of Texas System Light-emitting nanoparticles and method of making same
US20030113940A1 (en) * 2001-07-16 2003-06-19 Erlanger Bernard F. Antibodies specific for nanotubes and related methods and compositions
KR20040047777A (en) 2001-07-20 2004-06-05 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 Transition metal oxide nanowires, and devices incorporating them
KR100455284B1 (en) 2001-08-14 2004-11-12 삼성전자주식회사 High-throughput sensor for detecting biomolecules using carbon nanotubes
WO2003023360A2 (en) * 2001-09-10 2003-03-20 Meso Scale Technologies, Llc Methods and apparatus for conducting multiple measurements on a sample
US7482168B2 (en) * 2001-09-15 2009-01-27 The Regents Of The University Of California Photoluminescent polymetalloles as chemical sensors
US20030073071A1 (en) * 2001-10-12 2003-04-17 Jurgen Fritz Solid state sensing system and method for measuring the binding or hybridization of biomolecules
US20050072213A1 (en) * 2001-11-26 2005-04-07 Isabelle Besnard Use of id semiconductor materials as chemical sensing materials, produced and operated close to room temperature
US20030124717A1 (en) * 2001-11-26 2003-07-03 Yuji Awano Method of manufacturing carbon cylindrical structures and biopolymer detection device
US7385262B2 (en) * 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
WO2003054931A1 (en) 2001-12-12 2003-07-03 Jorma Virtanen Method and apparatus for nano-sensing
US6882767B2 (en) * 2001-12-27 2005-04-19 The Regents Of The University Of California Nanowire optoelectric switching device and method
US20030134433A1 (en) * 2002-01-16 2003-07-17 Nanomix, Inc. Electronic sensing of chemical and biological agents using functionalized nanostructures
EP1468423A2 (en) * 2002-01-18 2004-10-20 California Institute Of Technology Array-based architecture for molecular electronics
CN1444259A (en) 2002-03-12 2003-09-24 株式会社东芝 Method for mfg. semiconductor device
US20040026684A1 (en) * 2002-04-02 2004-02-12 Nanosys, Inc. Nanowire heterostructures for encoding information
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US20030189202A1 (en) 2002-04-05 2003-10-09 Jun Li Nanowire devices and methods of fabrication
US20040067530A1 (en) * 2002-05-08 2004-04-08 The Regents Of The University Of California Electronic sensing of biomolecular processes
AU2003258969A1 (en) * 2002-06-27 2004-01-19 Nanosys Inc. Planar nanowire based sensor elements, devices, systems and methods for using and making same
US7335908B2 (en) * 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
AU2003261205A1 (en) 2002-07-19 2004-02-09 President And Fellows Of Harvard College Nanoscale coherent optical components
DE60313462T2 (en) * 2002-07-25 2008-01-03 California Institute Of Technology, Pasadena SUBLITHOGRAPHIC NANO AREA STORE ARCHITECTURE
US7662313B2 (en) * 2002-09-05 2010-02-16 Nanosys, Inc. Oriented nanostructures and methods of preparing
AU2003279708A1 (en) 2002-09-05 2004-03-29 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
US7572393B2 (en) * 2002-09-05 2009-08-11 Nanosys Inc. Organic species that facilitate charge transfer to or from nanostructures
EP1537445B1 (en) * 2002-09-05 2012-08-01 Nanosys, Inc. Nanocomposites
US7135728B2 (en) * 2002-09-30 2006-11-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
AU2003283973B2 (en) 2002-09-30 2008-10-30 Oned Material Llc Large-area nanoenabled macroelectronic substrates and uses therefor
US7067867B2 (en) * 2002-09-30 2006-06-27 Nanosys, Inc. Large-area nonenabled macroelectronic substrates and uses therefor
US7051945B2 (en) * 2002-09-30 2006-05-30 Nanosys, Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
CA2499944A1 (en) 2002-09-30 2004-04-15 Nanosys, Inc. Integrated displays using nanowire transistors
AU2003282548A1 (en) 2002-10-10 2004-05-04 Nanosys, Inc. Nano-chem-fet based biosensors
US7163659B2 (en) * 2002-12-03 2007-01-16 Hewlett-Packard Development Company, L.P. Free-standing nanowire sensor and method for detecting an analyte in a fluid
US6815706B2 (en) 2002-12-17 2004-11-09 Hewlett-Packard Development Company, L.P. Nano optical sensors via molecular self-assembly
US20040191517A1 (en) * 2003-03-26 2004-09-30 Industrial Technology Research Institute Self-assembling nanowires
US7274208B2 (en) * 2003-06-02 2007-09-25 California Institute Of Technology Nanoscale wire-based sublithographic programmable logic arrays
EP1652218A2 (en) * 2003-08-04 2006-05-03 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US7067328B2 (en) * 2003-09-25 2006-06-27 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
US20050253137A1 (en) 2003-11-20 2005-11-17 President And Fellows Of Harvard College Nanoscale arrays, robust nanostructures, and related devices
US7662706B2 (en) * 2003-11-26 2010-02-16 Qunano Ab Nanostructures formed of branched nanowhiskers and methods of producing the same
WO2005093831A1 (en) 2004-02-13 2005-10-06 President And Fellows Of Harvard College Nanostructures containing metal-semiconductor compounds
US20090227107A9 (en) * 2004-02-13 2009-09-10 President And Fellows Of Havard College Nanostructures Containing Metal Semiconductor Compounds
EP1723676A4 (en) 2004-03-10 2009-04-15 Nanosys Inc Nano-enabled memory devices and anisotropic charge carrying arrays
US7595528B2 (en) 2004-03-10 2009-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US20050202615A1 (en) 2004-03-10 2005-09-15 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
US7115971B2 (en) 2004-03-23 2006-10-03 Nanosys, Inc. Nanowire varactor diode and methods of making same
EP1747577A2 (en) 2004-04-30 2007-01-31 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
CA2565765A1 (en) 2004-05-13 2005-12-01 The Regents Of The University Of California Nanowires and nanoribbons as subwavelength optical waveguides and their use as components in photonic circuits and devices
US7129154B2 (en) 2004-05-28 2006-10-31 Agilent Technologies, Inc Method of growing semiconductor nanowires with uniform cross-sectional area using chemical vapor deposition
CN102064102B (en) 2004-06-08 2013-10-30 桑迪士克公司 Methods and devices for forming nanostructure monolayers and devices including such monolayers
CA2572798A1 (en) * 2004-07-07 2006-07-27 Nanosys, Inc. Systems and methods for harvesting and integrating nanowires
US8072005B2 (en) * 2005-02-04 2011-12-06 Brown University Research Foundation Apparatus, method and computer program product providing radial addressing of nanowires
US20070048482A1 (en) * 2005-03-21 2007-03-01 Kadlec Gary F Disposable protective sheeting for decks and floors
US20060269927A1 (en) 2005-05-25 2006-11-30 Lieber Charles M Nanoscale sensors
WO2006132659A2 (en) 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures
US7481930B2 (en) * 2005-07-29 2009-01-27 Rg Delaware, Inc. Filter having a filter layer that forms a protective barrier to prevent clogging of a gravel-less underdrain and method of making the same
EP2013611A2 (en) 2006-03-15 2009-01-14 The President and Fellows of Harvard College Nanobioelectronics
WO2007145701A2 (en) 2006-04-07 2007-12-21 President And Fellows Of Harvard College Nanoscale wire methods and devices
WO2008033303A2 (en) 2006-09-11 2008-03-20 President And Fellows Of Harvard College Branched nanoscale wires
WO2008123869A2 (en) 2006-11-21 2008-10-16 President And Fellows Of Harvard College Millimeter-long nanowires
US8575663B2 (en) 2006-11-22 2013-11-05 President And Fellows Of Harvard College High-sensitivity nanoscale wire sensors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A. MORALES; C. LIEBER: "A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires", SCIENCE, vol. 279, 1998, pages 208 - 211

Cited By (180)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7172953B2 (en) 1999-07-02 2007-02-06 President And Fellows Of Harvard College Methods of forming nanoscopic wire-based devices and arrays
US7399691B2 (en) 1999-07-02 2008-07-15 President And Fellows Of Harvard College Methods of forming nanoscopic wire-based devices and arrays
US8471298B2 (en) 1999-07-02 2013-06-25 President And Fellows Of Harvard College Nanoscopic wire-based devices and arrays
US8178907B2 (en) 1999-07-02 2012-05-15 President And Fellows Of Harvard College Nanoscopic wire-based electrical crossbar memory-devices and arrays
US6781166B2 (en) 1999-07-02 2004-08-24 President & Fellows Of Harvard College Nanoscopic wire-based devices and arrays
US7915151B2 (en) 2000-08-22 2011-03-29 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
US7666708B2 (en) 2000-08-22 2010-02-23 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
US8153470B2 (en) 2000-08-22 2012-04-10 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
US8399339B2 (en) 2000-12-11 2013-03-19 President And Fellows Of Harvard College Nanosensors
US7956427B2 (en) 2000-12-11 2011-06-07 President And Fellows Of Harvard College Nanosensors
US7911009B2 (en) 2000-12-11 2011-03-22 President And Fellows Of Harvard College Nanosensors
WO2003005450A2 (en) 2001-05-18 2003-01-16 President And Fellows Of Harvard College Nanoscale wires and related devices
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US7422980B1 (en) 2002-04-02 2008-09-09 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US7164209B1 (en) 2002-04-02 2007-01-16 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
EP2253583A2 (en) 2002-04-02 2010-11-24 Nanosys, Inc. Method of harvesting nanostructures from a substrate
US7651944B2 (en) 2002-04-02 2010-01-26 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US7151209B2 (en) 2002-04-02 2006-12-19 Nanosys, Inc. Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices
US6962823B2 (en) 2002-04-02 2005-11-08 Nanosys, Inc. Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices
US6914279B2 (en) 2002-06-06 2005-07-05 Rutgers, The State University Of New Jersey Multifunctional biosensor based on ZnO nanostructures
WO2003104789A1 (en) * 2002-06-06 2003-12-18 Rutgers, The State University Of New Jersey MULTIFUNCTIONAL BIOSENSOR BASED ON ZnO NANOSTRUCTURES
US8377683B2 (en) 2002-06-06 2013-02-19 Rutgers, The State University Of New Jersey Zinc oxide-based nanostructure modified QCM for dynamic monitoring of cell adhesion and proliferation
US7272511B2 (en) 2002-06-20 2007-09-18 Stmicroelectronics, S.R.L. Molecular memory obtained using DNA strand molecular switches and carbon nanotubes, and method for manufacturing the same
EP1376606A1 (en) * 2002-06-20 2004-01-02 STMicroelectronics S.r.l. A molecular memory obtained using DNA strand molecular switches and carbon nanotubes, and manufacturing method thereof
US7335908B2 (en) 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
US8450717B1 (en) 2002-07-08 2013-05-28 Qunano Ab Nanostructures and methods for manufacturing the same
US8772626B2 (en) 2002-07-08 2014-07-08 Qunano Ab Nanostructures and methods for manufacturing the same
US7682943B2 (en) 2002-07-08 2010-03-23 Qunano Ab Nanostructures and methods for manufacturing the same
US9680039B2 (en) 2002-07-08 2017-06-13 Qunano Ab Nanostructures and methods for manufacturing the same
US7745813B2 (en) 2002-07-08 2010-06-29 Qunano Ab Nanostructures and methods for manufacturing the same
WO2004038767A2 (en) * 2002-07-16 2004-05-06 President And Fellows Of Harvard College Doped nanoscale wires and method of manufacture
WO2004038767A3 (en) * 2002-07-16 2004-08-19 Harvard College Doped nanoscale wires and method of manufacture
WO2004010552A1 (en) * 2002-07-19 2004-01-29 President And Fellows Of Harvard College Nanoscale coherent optical components
US7750235B2 (en) 2002-09-05 2010-07-06 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
US6949206B2 (en) 2002-09-05 2005-09-27 Nanosys, Inc. Organic species that facilitate charge transfer to or from nanostructures
US7662313B2 (en) 2002-09-05 2010-02-16 Nanosys, Inc. Oriented nanostructures and methods of preparing
US7572393B2 (en) 2002-09-05 2009-08-11 Nanosys Inc. Organic species that facilitate charge transfer to or from nanostructures
US7572395B2 (en) 2002-09-05 2009-08-11 Nanosys, Inc Organic species that facilitate charge transfer to or from nanostructures
US7438833B2 (en) 2002-09-05 2008-10-21 Nanosys, Inc. Organic species that facilitate charge transfer to or from nanostructures
US7087833B2 (en) 2002-09-05 2006-08-08 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
US7087832B2 (en) 2002-09-05 2006-08-08 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
US6878871B2 (en) 2002-09-05 2005-04-12 Nanosys, Inc. Nanostructure and nanocomposite based compositions and photovoltaic devices
US8562867B2 (en) 2002-09-05 2013-10-22 Nanosys, Inc. Organic species that facilitate charge transfer to or from nanostructures
US7943064B2 (en) 2002-09-05 2011-05-17 Nanosys, Inc. Organic species that facilitate charge transfer to or from nanostructures
US7102605B2 (en) 2002-09-30 2006-09-05 Nanosys, Inc. Integrated displays using nanowire transistors
US7701428B2 (en) 2002-09-30 2010-04-20 Nanosys, Inc. Integrated displays using nanowire transistors
JP2006501689A (en) * 2002-09-30 2006-01-12 ナノシス・インコーポレイテッド Integrated display using nanowire transistors
EP2218681A2 (en) 2002-09-30 2010-08-18 Nanosys, Inc. Et AL. Applications of Nano-Enabled Large Area Macroelectronic Substrates Incorporating Nanowires and Nanowire Composites
JP2006507692A (en) * 2002-09-30 2006-03-02 ナノシス・インコーポレイテッド Large area nano-capable macroelectronic substrate and its use
EP1547139A2 (en) * 2002-09-30 2005-06-29 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
US8030186B2 (en) 2002-09-30 2011-10-04 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP1563555A2 (en) * 2002-09-30 2005-08-17 Nanosys, Inc. Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US8293624B2 (en) 2002-09-30 2012-10-23 Nanosys, Inc. Large area nanoenabled macroelectronic substrates and uses therefor
EP1563555A4 (en) * 2002-09-30 2009-08-26 Nanosys Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US7851841B2 (en) 2002-09-30 2010-12-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP2194026A1 (en) 2002-09-30 2010-06-09 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP2261174A2 (en) 2002-09-30 2010-12-15 Nanosys, Inc. Et AL. RFID tag using nanowire transistors
US7932511B2 (en) 2002-09-30 2011-04-26 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP1547139A4 (en) * 2002-09-30 2009-08-26 Nanosys Inc Large-area nanoenabled macroelectronic substrates and uses therefor
WO2004042830A1 (en) * 2002-11-05 2004-05-21 Koninklijke Philips Electronics N.V. Nanostructure, electronic device having such nanostructure and method of preparing nanostructure
CN100459181C (en) * 2002-11-05 2009-02-04 皇家飞利浦电子股份有限公司 Nanostructure, electronic device having such nanostructure and method of preparing nanostructure
JP2007329500A (en) * 2002-11-15 2007-12-20 Samsung Electronics Co Ltd Nonvolatile memory device using vertical nanotubes
US8790462B2 (en) 2003-04-04 2014-07-29 Qunano Ab Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
US7344617B2 (en) 2003-04-17 2008-03-18 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US7056409B2 (en) 2003-04-17 2006-06-06 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US7074294B2 (en) 2003-04-17 2006-07-11 Nanosys, Inc. Structures, systems and methods for joining articles and materials and uses therefor
US7910064B2 (en) 2003-06-03 2011-03-22 Nanosys, Inc. Nanowire-based sensor configurations
US7795125B2 (en) 2003-08-04 2010-09-14 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US7468315B2 (en) 2003-08-04 2008-12-23 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US7091120B2 (en) 2003-08-04 2006-08-15 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US7067328B2 (en) 2003-09-25 2006-06-27 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
US7754524B2 (en) 2003-09-25 2010-07-13 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
US7829351B2 (en) 2003-09-25 2010-11-09 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
WO2005054869A1 (en) * 2003-12-08 2005-06-16 Postech Foundation Biosensor comprising zinc oxide-based nanorod and preparation thereof
US7112525B1 (en) * 2003-12-22 2006-09-26 University Of South Florida Method for the assembly of nanowire interconnects
US8025960B2 (en) 2004-02-02 2011-09-27 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US10279341B2 (en) 2004-02-02 2019-05-07 Oned Material Llc Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
JP2005244240A (en) * 2004-02-26 2005-09-08 Samsung Sdi Co Ltd Thin-film transistor, flat plate display device equipped with the same, manufacturing methods of the thin-film transistor, flat plate display device, and manufacturing method of donor sheet
JP2005260221A (en) * 2004-02-26 2005-09-22 Samsung Sdi Co Ltd Donor sheet, method of manufacturing the donor sheet, method of manufacturing thin film transistors using the donor sheet and method of manufacturing flat panel display device using the donor sheet
US7595528B2 (en) 2004-03-10 2009-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
WO2005089165A2 (en) 2004-03-10 2005-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US7382017B2 (en) 2004-03-10 2008-06-03 Nanosys, Inc Nano-enabled memory devices and anisotropic charge carrying arrays
US7295419B2 (en) 2004-03-18 2007-11-13 Nanosys, Inc. Nanofiber surface based capacitors
US7466533B2 (en) 2004-03-18 2008-12-16 Nanosys, Inc Nanofiber surface based capacitors
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
USRE43868E1 (en) 2004-03-18 2012-12-25 Nanosys, Inc. Nanofiber surface based capacitors
US7116546B2 (en) 2004-03-18 2006-10-03 Nanosys, Inc. Nanofiber surface based capacitors
US7115971B2 (en) 2004-03-23 2006-10-03 Nanosys, Inc. Nanowire varactor diode and methods of making same
US7667296B2 (en) 2004-03-23 2010-02-23 Nanosys, Inc. Nanowire capacitor and methods of making same
US7985454B2 (en) 2004-04-30 2011-07-26 Nanosys, Inc. Systems and methods for nanowire growth and manufacturing
US7105428B2 (en) 2004-04-30 2006-09-12 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
US7273732B2 (en) 2004-04-30 2007-09-25 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
CN102351169B (en) * 2004-04-30 2013-11-27 纳米系统公司 Systems and methods for nanowire growth and harvesting
US7666791B2 (en) 2004-04-30 2010-02-23 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
US11088268B2 (en) 2004-06-04 2021-08-10 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US10374072B2 (en) 2004-06-04 2019-08-06 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US7968273B2 (en) 2004-06-08 2011-06-28 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7776758B2 (en) 2004-06-08 2010-08-17 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7501315B2 (en) 2004-06-08 2009-03-10 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7585564B2 (en) 2004-06-08 2009-09-08 Nanosys, Inc. Post-deposition encapsulation of nanostructures: compositions, devices and systems incorporating same
US7267875B2 (en) 2004-06-08 2007-09-11 Nanosys, Inc. Post-deposition encapsulation of nanostructures: compositions, devices and systems incorporating same
US8143703B2 (en) 2004-06-08 2012-03-27 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US8357954B2 (en) 2004-06-25 2013-01-22 Qunano Ab Formation of nanowhiskers on a substrate of dissimilar material
US7960260B2 (en) 2004-06-25 2011-06-14 Qunano Ab Formation of nanowhiskers on a substrate of dissimilar material
US7528002B2 (en) 2004-06-25 2009-05-05 Qunano Ab Formation of nanowhiskers on a substrate of dissimilar material
US7767102B2 (en) 2004-07-07 2010-08-03 Nanosys, Inc. Systems and methods for harvesting and integrating nanowires
US7339184B2 (en) 2004-07-07 2008-03-04 Nanosys, Inc Systems and methods for harvesting and integrating nanowires
US7344961B2 (en) 2004-07-07 2008-03-18 Nanosys, Inc. Methods for nanowire growth
US7365395B2 (en) 2004-09-16 2008-04-29 Nanosys, Inc. Artificial dielectrics using nanostructures
US8558311B2 (en) 2004-09-16 2013-10-15 Nanosys, Inc. Dielectrics using substantially longitudinally oriented insulated conductive wires
US7586130B2 (en) 2004-10-04 2009-09-08 Panasonic Corporation Vertical field effect transistor using linear structure as a channel region and method for fabricating the same
US7345307B2 (en) 2004-10-12 2008-03-18 Nanosys, Inc. Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
US7871870B2 (en) 2004-10-15 2011-01-18 Nanosys, Inc. Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices
US7473943B2 (en) 2004-10-15 2009-01-06 Nanosys, Inc. Gate configuration for nanowire electronic devices
US7701014B2 (en) 2004-10-15 2010-04-20 Nanosys, Inc. Gating configurations and improved contacts in nanowire-based electronic devices
US7569503B2 (en) 2004-11-24 2009-08-04 Nanosys, Inc. Contact doping and annealing systems and processes for nanowire thin films
US7560366B1 (en) 2004-12-02 2009-07-14 Nanosys, Inc. Nanowire horizontal growth and substrate removal
US8154002B2 (en) 2004-12-06 2012-04-10 President And Fellows Of Harvard College Nanoscale wire-based data storage
US7772543B2 (en) 2005-01-12 2010-08-10 New York University System and method for processing nanowires with holographic optical tweezers
WO2007084114A2 (en) * 2005-01-12 2007-07-26 New York University System and method for processing nanowires with holographic optical tweezers
WO2007084114A3 (en) * 2005-01-12 2007-12-13 Univ New York System and method for processing nanowires with holographic optical tweezers
US7772125B2 (en) 2005-02-10 2010-08-10 Panasonic Corporation Structure in which cylindrical microstructure is maintained in anisotropic groove, method for fabricating the same, and semiconductor device, TFT driving circuit, panel, display and sensor using the structure in which cylindrical microstructure is maintained in anisotropic groove
KR100661696B1 (en) * 2005-02-22 2006-12-26 삼성전자주식회사 Semiconductor Nanowire of Heterostructure and Method for Producing the same
EP1696473A2 (en) * 2005-02-25 2006-08-30 Samsung Electronics Co.,Ltd. Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires
EP1696473A3 (en) * 2005-02-25 2009-06-10 Samsung Electronics Co.,Ltd. Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires
WO2007078304A2 (en) 2005-03-24 2007-07-12 Nanosys, Inc. Medical device applications of nanostructured surfaces
US8232584B2 (en) 2005-05-25 2012-07-31 President And Fellows Of Harvard College Nanoscale sensors
US7858965B2 (en) 2005-06-06 2010-12-28 President And Fellows Of Harvard College Nanowire heterostructures
KR101386268B1 (en) 2005-08-26 2014-04-17 스몰텍 에이비 Interconnects and heat dissipators based on nanostructures
WO2007038164A2 (en) 2005-09-23 2007-04-05 Nanosys, Inc. Methods for nanostructure doping
EP2378597A1 (en) 2005-11-21 2011-10-19 Nanosys, Inc. Nanowire structures comprising carbon
WO2007133271A2 (en) 2005-12-29 2007-11-22 Nanosys, Inc. Methods for oriented growth of nanowires on patterned substrates
US7566435B2 (en) * 2005-12-30 2009-07-28 Industrial Technology Research Institute Nanowires and method for making the same
US7893513B2 (en) 2006-02-02 2011-02-22 William Marsh Rice University Nanoparticle/nanotube-based nanoelectronic devices and chemically-directed assembly thereof
WO2008060640A2 (en) * 2006-02-02 2008-05-22 William Marsh Rice University Nanoparticle / nanotube-based nanoelectronic devices and chemically-directed assembly thereof
WO2008060640A3 (en) * 2006-02-02 2008-07-17 Univ Rice William M Nanoparticle / nanotube-based nanoelectronic devices and chemically-directed assembly thereof
US7826336B2 (en) 2006-02-23 2010-11-02 Qunano Ab Data storage nanostructures
US9903862B2 (en) 2006-06-12 2018-02-27 President And Fellows Of Harvard College Nanosensors and related technologies
US9102521B2 (en) 2006-06-12 2015-08-11 President And Fellows Of Harvard College Nanosensors and related technologies
US8323789B2 (en) 2006-08-31 2012-12-04 Cambridge Enterprise Limited Nanomaterial polymer compositions and uses thereof
US8058640B2 (en) 2006-09-11 2011-11-15 President And Fellows Of Harvard College Branched nanoscale wires
US8591952B2 (en) 2006-10-10 2013-11-26 Massachusetts Institute Of Technology Absorbant superhydrophobic materials, and methods of preparation and use thereof
US7776760B2 (en) 2006-11-07 2010-08-17 Nanosys, Inc. Systems and methods for nanowire growth
US7847238B2 (en) 2006-11-07 2010-12-07 New York University Holographic microfabrication and characterization system for soft matter and biological systems
US8431884B2 (en) 2006-11-07 2013-04-30 New York University Holographic microfabrication and characterization system for soft matter and biological systems
US8575663B2 (en) 2006-11-22 2013-11-05 President And Fellows Of Harvard College High-sensitivity nanoscale wire sensors
US9535063B2 (en) 2006-11-22 2017-01-03 President And Fellows Of Harvard College High-sensitivity nanoscale wire sensors
US10263149B2 (en) 2006-12-22 2019-04-16 Qunano Ab Nanostructured LED array with collimating reflectors
US8067299B2 (en) 2006-12-22 2011-11-29 Qunano Ab Nanoelectronic structure and method of producing such
US8455857B2 (en) 2006-12-22 2013-06-04 Qunano Ab Nanoelectronic structure and method of producing such
US8183587B2 (en) 2006-12-22 2012-05-22 Qunano Ab LED with upstanding nanowire structure and method of producing such
US8796119B2 (en) 2006-12-22 2014-08-05 Qunano Ab Nanoelectronic structure and method of producing such
US8049203B2 (en) 2006-12-22 2011-11-01 Qunano Ab Nanoelectronic structure and method of producing such
US9096429B2 (en) 2006-12-22 2015-08-04 Qunano Ab Nanoelectronic structure and method of producing such
US8030141B2 (en) 2007-04-25 2011-10-04 Lg Display Co., Ltd. Thin film transistor and method for fabricating the same, and liquid crystal display device and method for manufacturing the same
US7892610B2 (en) 2007-05-07 2011-02-22 Nanosys, Inc. Method and system for printing aligned nanowires and other electrical devices
US8174742B2 (en) 2008-03-14 2012-05-08 New York University System for applying optical forces from phase gradients
US8414957B2 (en) 2008-04-30 2013-04-09 Nanosys, Inc. Non-fouling surfaces for reflective spheres
US8486532B2 (en) 2008-04-30 2013-07-16 Nanosys, Inc. Non-fouling surfaces for reflective spheres
US8364243B2 (en) 2008-04-30 2013-01-29 Nanosys, Inc. Non-fouling surfaces for reflective spheres
US9006133B2 (en) 2008-10-24 2015-04-14 Oned Material Llc Electrochemical catalysts for fuel cells
US8540889B1 (en) 2008-11-19 2013-09-24 Nanosys, Inc. Methods of generating liquidphobic surfaces
US9040208B2 (en) 2009-05-04 2015-05-26 Oned Material Llc Catalyst layer for fuel cell membrane electrode assembly, fuel cell membrane electrode assembly using the catalyst layer, fuel cell, and method for producing the catalyst layer
US10490817B2 (en) 2009-05-19 2019-11-26 Oned Material Llc Nanostructured materials for battery applications
EP3859830A1 (en) 2009-05-19 2021-08-04 OneD Material, Inc. Nanostructured materials for battery applications
US11600821B2 (en) 2009-05-19 2023-03-07 Oned Material, Inc. Nanostructured materials for battery applications
EP4068914A2 (en) 2009-05-19 2022-10-05 OneD Material, Inc. Nanostructured materials for battery applications
US11233240B2 (en) 2009-05-19 2022-01-25 Oned Material, Inc. Nanostructured materials for battery applications
US9390951B2 (en) 2009-05-26 2016-07-12 Sharp Kabushiki Kaisha Methods and systems for electric field deposition of nanowires and other devices
US9297796B2 (en) 2009-09-24 2016-03-29 President And Fellows Of Harvard College Bent nanowires and related probing of species
WO2011072787A1 (en) 2009-12-17 2011-06-23 Merck Patent Gmbh Deposition of nanoparticles
US8390066B2 (en) 2010-03-15 2013-03-05 Kabushiki Kaisha Toshiba Semiconductor nanowire memory device
US10049871B2 (en) 2013-02-06 2018-08-14 President And Fellows Of Harvard College Anisotropic deposition in nanoscale wires
CN103840080A (en) * 2013-12-05 2014-06-04 南昌大学 Voltage control storage based on one-dimensional cadmium doping zinc oxide nanowire and preparing method of voltage control storage
CN103840080B (en) * 2013-12-05 2016-08-17 南昌大学 Control of Voltage memorizer based on one-dimensional cadmium doped zinc oxide nano-wire and preparation method
US10435817B2 (en) 2014-05-07 2019-10-08 President And Fellows Of Harvard College Controlled growth of nanoscale wires
US10986465B2 (en) 2015-02-20 2021-04-20 Medidata Solutions, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
US10567152B2 (en) 2016-02-22 2020-02-18 Mc10, Inc. System, devices, and method for on-body data and power transmission
CN111477560A (en) * 2020-05-14 2020-07-31 包头美科硅能源有限公司 Rapid detection method for distinguishing gallium-boron-doped single crystal silicon rods for solar cell
CN111477560B (en) * 2020-05-14 2023-03-03 包头美科硅能源有限公司 Rapid detection method for distinguishing gallium-boron-doped single crystal silicon rods for solar cell

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