WO2002025727A3 - Method of forming conductive interconnections on an integrated circuit device - Google Patents

Method of forming conductive interconnections on an integrated circuit device Download PDF

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Publication number
WO2002025727A3
WO2002025727A3 PCT/US2001/023579 US0123579W WO0225727A3 WO 2002025727 A3 WO2002025727 A3 WO 2002025727A3 US 0123579 W US0123579 W US 0123579W WO 0225727 A3 WO0225727 A3 WO 0225727A3
Authority
WO
WIPO (PCT)
Prior art keywords
opening
tungsten
forming
integrated circuit
circuit device
Prior art date
Application number
PCT/US2001/023579
Other languages
French (fr)
Other versions
WO2002025727A2 (en
Inventor
Clive Martin Jones
Tim Z Hossain
Amiya R Ghatak-Roy
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU7802901A priority Critical patent/AU7802901A/en
Publication of WO2002025727A2 publication Critical patent/WO2002025727A2/en
Publication of WO2002025727A3 publication Critical patent/WO2002025727A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers

Abstract

A method of forming conductive interconnections is disclosed herein. In one illustrative embodiment, the method comprises forming an opening (68) in a layer insulation material (62), forming a first plurality of silicon seed atoms (51) in the opening (68), and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms (53) in the opening (68) above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms (53) to further form tungsten material in the opening (68).
PCT/US2001/023579 2000-09-18 2001-07-26 Method of forming conductive interconnections on an integrated circuit device WO2002025727A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU7802901A AU7802901A (en) 2000-09-18 2001-07-26 Method of forming conductive interconnections on an integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/664,238 US6579788B1 (en) 2000-09-18 2000-09-18 Method of forming conductive interconnections on an integrated circuit device
US09/664,238 2000-09-18

Publications (2)

Publication Number Publication Date
WO2002025727A2 WO2002025727A2 (en) 2002-03-28
WO2002025727A3 true WO2002025727A3 (en) 2002-07-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/023579 WO2002025727A2 (en) 2000-09-18 2001-07-26 Method of forming conductive interconnections on an integrated circuit device

Country Status (4)

Country Link
US (1) US6579788B1 (en)
AU (1) AU7802901A (en)
TW (1) TW506071B (en)
WO (1) WO2002025727A2 (en)

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Publication number Priority date Publication date Assignee Title
KR100688055B1 (en) * 2004-05-10 2007-02-28 주식회사 하이닉스반도체 Method for manufacturing metal-interconnect using barrier metal formed low temperature
US9252050B2 (en) 2012-09-11 2016-02-02 International Business Machines Corporation Method to improve semiconductor surfaces and polishing
US20150200355A1 (en) * 2014-01-15 2015-07-16 Allegro Microsystems, Llc Fabricating a via
CN110137153B (en) * 2018-02-09 2021-03-30 联华电子股份有限公司 Semiconductor device and method of forming the same
US10847367B2 (en) 2018-12-28 2020-11-24 Micron Technology, Inc. Methods of forming tungsten structures
US10916438B2 (en) 2019-05-09 2021-02-09 Allegro Microsystems, Llc Method of multiple gate oxide forming with hard mask
US11244903B2 (en) * 2019-12-30 2022-02-08 Micron Technology, Inc. Tungsten structures and methods of forming the structures

Citations (1)

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Publication number Priority date Publication date Assignee Title
US5686355A (en) * 1994-10-27 1997-11-11 Sony Corporation Method for forming film of refractory metal

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JP2946978B2 (en) * 1991-11-29 1999-09-13 ソニー株式会社 Wiring formation method
US6140228A (en) * 1997-11-13 2000-10-31 Cypress Semiconductor Corporation Low temperature metallization process
US6271129B1 (en) * 1997-12-03 2001-08-07 Applied Materials, Inc. Method for forming a gap filling refractory metal layer having reduced stress
US6215186B1 (en) * 1998-01-12 2001-04-10 Texas Instruments Incorporated System and method of forming a tungstein plug
JP2937998B1 (en) * 1998-03-16 1999-08-23 山形日本電気株式会社 Wiring manufacturing method
US6475912B1 (en) * 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
US6297147B1 (en) * 1998-06-05 2001-10-02 Applied Materials, Inc. Plasma treatment for ex-situ contact fill
US6331483B1 (en) * 1998-12-18 2001-12-18 Tokyo Electron Limited Method of film-forming of tungsten
US6245654B1 (en) * 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6174795B1 (en) * 1999-03-31 2001-01-16 Taiwan Semiconductor Manufacturing Co., Ltd Method for preventing tungsten contact plug loss after a backside pressure fault
JP2000306997A (en) * 1999-04-20 2000-11-02 Nec Corp Semiconductor device having barrier metal layer and fabrication thereof
US6524956B1 (en) * 1999-09-24 2003-02-25 Novelius Systems, Inc. Method for controlling the grain size of tungsten films
US6326297B1 (en) * 1999-09-30 2001-12-04 Novellus Systems, Inc. Method of making a tungsten nitride barrier layer with improved adhesion and stability using a silicon layer
US6399440B1 (en) * 1999-11-22 2002-06-04 Vanguard International Semiconductor Corporation Method to reduce the node contact resistance
US6403465B1 (en) * 1999-12-28 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to improve copper barrier properties
KR100330163B1 (en) * 2000-01-06 2002-03-28 윤종용 A Method of Forming Tungsten Contact Plug in A Semiconductor Devices
US6410383B1 (en) * 2000-03-16 2002-06-25 Sharp Laboratories Of America, Inc. Method of forming conducting diffusion barriers
US6403466B1 (en) * 2001-03-13 2002-06-11 Advanced Micro Devices, Inc. Post-CMP-Cu deposition and CMP to eliminate surface voids

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5686355A (en) * 1994-10-27 1997-11-11 Sony Corporation Method for forming film of refractory metal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TSAI N S ET AL: "Layer tungsten and its applications for VLSI interconnects", INTERNATIONAL ELECTRON DEVICES MEETING. TECHNICAL DIGEST (IEEE CAT. NO.88CH2528-8), SAN FRANCISCO, CA, USA, 11-14 DEC. 1988, 1988, New York, NY, USA, IEEE, USA, pages 462 - 465, XP010070817 *

Also Published As

Publication number Publication date
WO2002025727A2 (en) 2002-03-28
TW506071B (en) 2002-10-11
US6579788B1 (en) 2003-06-17
AU7802901A (en) 2002-04-02

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