WO2002031658A3 - Speicherkonfiguration mit i/o-unterstützung - Google Patents

Speicherkonfiguration mit i/o-unterstützung Download PDF

Info

Publication number
WO2002031658A3
WO2002031658A3 PCT/DE2001/003916 DE0103916W WO0231658A3 WO 2002031658 A3 WO2002031658 A3 WO 2002031658A3 DE 0103916 W DE0103916 W DE 0103916W WO 0231658 A3 WO0231658 A3 WO 0231658A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
unit
support
memory configuration
write
Prior art date
Application number
PCT/DE2001/003916
Other languages
English (en)
French (fr)
Other versions
WO2002031658A2 (de
Inventor
Wolfram Drescher
Volker Aue
Original Assignee
Systemonic Ag
Wolfram Drescher
Volker Aue
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Systemonic Ag, Wolfram Drescher, Volker Aue filed Critical Systemonic Ag
Priority to US10/399,073 priority Critical patent/US7143211B2/en
Priority to AU2002218137A priority patent/AU2002218137A1/en
Priority to KR1020037005204A priority patent/KR100777497B1/ko
Priority to DE50106472T priority patent/DE50106472D1/de
Priority to JP2002534979A priority patent/JP2004511851A/ja
Priority to EP01986784A priority patent/EP1328862B1/de
Publication of WO2002031658A2 publication Critical patent/WO2002031658A2/de
Publication of WO2002031658A3 publication Critical patent/WO2002031658A3/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Abstract

Der Erfindung, die ein Verfahren zur Speicherkonfiguration mit I/O-Unterstützung betrifft, liegt die Aufgabe zugrunde mit geringem programmtechnischen Aufwand den unter zeitkritischen Bedingungen arbeitenden Prozessor- und I/O-Funktionseinheiten entsprechenden Vorrang beim Datenzugriff zu sichern. Dies wird dadurch gelöst, dass in dem Prozessor-Speicher ein Input-Speicher-Bereich vereinbart ist, in den die I/O-Einheit nur schreiben und aus dem die Prozessor-Einheit nur lesen kann und dass ein Output-Speicherbereich vereinbart ist, aus dem die I/O-Einheit nur lesen kann und in den die Prozessor-Einheit nur schreiben kann.
PCT/DE2001/003916 2000-10-13 2001-10-15 Speicherkonfiguration mit i/o-unterstützung WO2002031658A2 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US10/399,073 US7143211B2 (en) 2000-10-13 2001-10-15 Memory configuration with I/O support
AU2002218137A AU2002218137A1 (en) 2000-10-13 2001-10-15 Memory configuration with i/o support
KR1020037005204A KR100777497B1 (ko) 2000-10-13 2001-10-15 프로세서 메모리 내에서의 데이터 입/출력 방법 및 상기 방법을 수행하기 위한 장치
DE50106472T DE50106472D1 (de) 2000-10-13 2001-10-15 Speicherkonfiguration mit i/o-unterstützung
JP2002534979A JP2004511851A (ja) 2000-10-13 2001-10-15 Ｉ／ｏサポートを有するメモリ構造
EP01986784A EP1328862B1 (de) 2000-10-13 2001-10-15 Speicherkonfiguration mit i/o-unterstützung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10050980A DE10050980A1 (de) 2000-10-13 2000-10-13 Speicherkonfiguration mit I/O-Unterstützung
DE10050980.0 2000-10-13

Publications (2)

Publication Number Publication Date
WO2002031658A2 WO2002031658A2 (de) 2002-04-18
WO2002031658A3 true WO2002031658A3 (de) 2003-02-27

Family

ID=7659799

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/003916 WO2002031658A2 (de) 2000-10-13 2001-10-15 Speicherkonfiguration mit i/o-unterstützung

Country Status (8)

Country Link
US (1) US7143211B2 (de)
EP (1) EP1328862B1 (de)
JP (1) JP2004511851A (de)
KR (1) KR100777497B1 (de)
CN (1) CN1256661C (de)
AU (1) AU2002218137A1 (de)
DE (2) DE10050980A1 (de)
WO (1) WO2002031658A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101275628B1 (ko) * 2011-09-29 2013-06-17 전자부품연구원 듀얼 포트 메모리 기반의 영역 크기 가변이 가능한 ｔｃｍ 메모리 구조의 전자칩
DK3562451T3 (da) * 2016-12-30 2022-02-07 Euromed Inc Klæbeplaster med forbedret skillelagsystem

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241129A2 (de) * 1986-03-06 1987-10-14 Advanced Micro Devices, Inc. Adressieranordnung für RAM-Puffer-Steuereinrichtung
DE19526798C1 (de) * 1995-07-14 1997-05-15 Hartmann & Braun Ag Anordnung zur Steuerung der bidirektionalen, asynchronen und seriellen Übertragung von Datenpaketen

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571671A (en) 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
JPS60129865A (ja) * 1983-12-19 1985-07-11 Matsushita Electric Ind Co Ltd 通信装置
JPS61118847A (ja) * 1984-11-15 1986-06-06 Nec Corp メモリの同時アクセス制御方式
JPS6292050A (ja) * 1985-10-18 1987-04-27 Canon Inc 入出力制御装置
JPH0193846A (ja) * 1987-10-05 1989-04-12 Fuji Xerox Co Ltd デュアル・ポート・メモリー制御装置
JPH0333952A (ja) * 1989-06-29 1991-02-14 Shikoku Nippon Denki Software Kk 画像メモリ書込装置
US5224213A (en) * 1989-09-05 1993-06-29 International Business Machines Corporation Ping-pong data buffer for transferring data from one data bus to another data bus
DE69031948T2 (de) * 1990-11-02 1998-04-23 St Microelectronics Srl System zur Speicherung von Daten auf FIFO-Basis
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
JPH05334230A (ja) * 1992-05-29 1993-12-17 Matsushita Electric Ind Co Ltd デュアルポートメモリアクセス制御回路
WO1994007200A1 (en) * 1992-09-21 1994-03-31 Unisys Corporation Multiported buffer memory system for disk drive complex
FR2702322B1 (fr) * 1993-03-01 1995-06-02 Texas Instruments France Mémoire à points d'interconnexion notamment pour la mise en communication de terminaux de télécommunication fonctionnant à des fréquences différentes.
JPH07182849A (ja) * 1993-12-21 1995-07-21 Kawasaki Steel Corp Ｆｉｆｏメモリ
US5487049A (en) * 1994-11-23 1996-01-23 Samsung Semiconductor, Inc. Page-in, burst-out FIFO
JPH08328994A (ja) * 1995-05-30 1996-12-13 Toshiba Corp 情報処理装置
JPH09319693A (ja) * 1996-05-28 1997-12-12 Hitachi Ltd データ転送装置および並列コンピュータシステム
DE19713178A1 (de) * 1997-03-27 1998-10-01 Siemens Ag Schaltungsanordnung mit einem Prozessor und einem Datenspeicher
JPH10301839A (ja) * 1997-04-25 1998-11-13 Matsushita Electric Ind Co Ltd メモリ制御方式および半導体装置
US6067595A (en) * 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
JP3263362B2 (ja) * 1998-06-05 2002-03-04 三菱電機株式会社 データ処理装置
US6166963A (en) * 1998-09-17 2000-12-26 National Semiconductor Corporation Dual port memory with synchronized read and write pointers
JP3226886B2 (ja) * 1999-01-29 2001-11-05 エヌイーシーマイクロシステム株式会社 半導体記憶装置とその制御方法
JP2000268573A (ja) * 1999-03-18 2000-09-29 Mitsubishi Electric Corp 半導体記憶装置
US6907480B2 (en) * 2001-07-11 2005-06-14 Seiko Epson Corporation Data processing apparatus and data input/output apparatus and data input/output method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241129A2 (de) * 1986-03-06 1987-10-14 Advanced Micro Devices, Inc. Adressieranordnung für RAM-Puffer-Steuereinrichtung
DE19526798C1 (de) * 1995-07-14 1997-05-15 Hartmann & Braun Ag Anordnung zur Steuerung der bidirektionalen, asynchronen und seriellen Übertragung von Datenpaketen

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HALL J: "NEW FIFO ARCHITECTURE FOR HIGH PERFORMANCE APPLICATIONS", WESCON TECHNICAL PAPERS, WESTERN PERIODICALS CO. NORTH HOLLYWOOD, US, vol. 33, 1 November 1989 (1989-11-01), pages 141 - 145, XP000115996 *
LIN J S: "BIDIRECTIONAL FIFO IN THE PROCESSOR-TO-PERIPHERAL COMMUNICATIONS", WESCON TECHNICAL PAPERS, WESTERN PERIODICALS CO. NORTH HOLLYWOOD, US, vol. 33, 1 November 1989 (1989-11-01), pages 131 - 136, XP000115994 *

Also Published As

Publication number Publication date
JP2004511851A (ja) 2004-04-15
KR100777497B1 (ko) 2007-11-20
US7143211B2 (en) 2006-11-28
AU2002218137A1 (en) 2002-04-22
DE10050980A1 (de) 2002-05-02
CN1256661C (zh) 2006-05-17
US20040054856A1 (en) 2004-03-18
KR20030064405A (ko) 2003-07-31
CN1470016A (zh) 2004-01-21
EP1328862B1 (de) 2005-06-08
WO2002031658A2 (de) 2002-04-18
EP1328862A2 (de) 2003-07-23
DE50106472D1 (de) 2005-07-14

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