WO2002039587A3 - Module, dispositif et procede de decodage a haut debit, d'un code concatene - Google Patents

Module, dispositif et procede de decodage a haut debit, d'un code concatene Download PDF

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Publication number
WO2002039587A3
WO2002039587A3 PCT/FR2001/003509 FR0103509W WO0239587A3 WO 2002039587 A3 WO2002039587 A3 WO 2002039587A3 FR 0103509 W FR0103509 W FR 0103509W WO 0239587 A3 WO0239587 A3 WO 0239587A3
Authority
WO
WIPO (PCT)
Prior art keywords
decoding
elementary
concatenated code
speed module
codes
Prior art date
Application number
PCT/FR2001/003509
Other languages
English (en)
Other versions
WO2002039587A2 (fr
Inventor
Patrick Adde
Ramesh Pyndiah
Original Assignee
France Telecom
Groupe Ecoles Telecomm
Patrick Adde
Ramesh Pyndiah
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom, Groupe Ecoles Telecomm, Patrick Adde, Ramesh Pyndiah filed Critical France Telecom
Priority to JP2002541794A priority Critical patent/JP3898129B2/ja
Priority to EP01993977A priority patent/EP1332557B1/fr
Priority to US10/416,484 priority patent/US7219291B2/en
Priority to DE60108892T priority patent/DE60108892T2/de
Priority to KR1020037006392A priority patent/KR100822463B1/ko
Publication of WO2002039587A2 publication Critical patent/WO2002039587A2/fr
Publication of WO2002039587A3 publication Critical patent/WO2002039587A3/fr
Priority to HK04104852A priority patent/HK1061937A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H03M13/2963—Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions

Abstract

L'invention concerne un module de décodage d'un code concaténé, correspondant à au moins deux codes élémentaires C1 et C2, du type mettant en oeuvre des moyens de mémorisation (81, 83, 90, 111, 113) dans lesquels sont stockés des échantillons de données à décoder, comprenant au moins deux décodeurs élémentaires (821, 822, .. 82m) d'au moins un des codes élémentaires, les décodeurs élémentaires associés à l'un des codes élémentaires traitant simultanément, en parallèle, des mots de code distincts contenus dans les moyens de mémorisation.
PCT/FR2001/003509 2000-11-10 2001-11-09 Module, dispositif et procede de decodage a haut debit, d'un code concatene WO2002039587A2 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002541794A JP3898129B2 (ja) 2000-11-10 2001-11-09 連接符号を復号するための高速のモジュール、デバイス及び方法
EP01993977A EP1332557B1 (fr) 2000-11-10 2001-11-09 Module, dispositif et procede de decodage a haut debit, d'un code concatene
US10/416,484 US7219291B2 (en) 2000-11-10 2001-11-09 High-speed module, device and method for decoding a concatenated code
DE60108892T DE60108892T2 (de) 2000-11-10 2001-11-09 Modul, vorrichtung und verfahren zum hochbitratigen dekodieren eines verketteten codes
KR1020037006392A KR100822463B1 (ko) 2000-11-10 2001-11-09 연결코드 디코딩을 위한 고속 모듈, 장치 및 방법
HK04104852A HK1061937A1 (en) 2000-11-10 2004-07-06 High-speed module, device and method for decoding of a concatenated code

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0014521A FR2816773B1 (fr) 2000-11-10 2000-11-10 Module, dispositif et procede de decodage a haut debit, d'un code concatene
FR00/14521 2000-11-10

Publications (2)

Publication Number Publication Date
WO2002039587A2 WO2002039587A2 (fr) 2002-05-16
WO2002039587A3 true WO2002039587A3 (fr) 2002-07-25

Family

ID=8856342

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2001/003509 WO2002039587A2 (fr) 2000-11-10 2001-11-09 Module, dispositif et procede de decodage a haut debit, d'un code concatene

Country Status (10)

Country Link
US (1) US7219291B2 (fr)
EP (1) EP1332557B1 (fr)
JP (1) JP3898129B2 (fr)
KR (1) KR100822463B1 (fr)
CN (1) CN1320771C (fr)
DE (1) DE60108892T2 (fr)
ES (1) ES2236354T3 (fr)
FR (1) FR2816773B1 (fr)
HK (1) HK1061937A1 (fr)
WO (1) WO2002039587A2 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9100457B2 (en) 2001-03-28 2015-08-04 Qualcomm Incorporated Method and apparatus for transmission framing in a wireless communication system
US7352868B2 (en) 2001-10-09 2008-04-01 Philip Hawkes Method and apparatus for security in a data processing system
US7649829B2 (en) 2001-10-12 2010-01-19 Qualcomm Incorporated Method and system for reduction of decoding complexity in a communication system
US7587659B2 (en) 2002-05-31 2009-09-08 Broadcom Corporation Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders
US7409628B2 (en) * 2002-08-15 2008-08-05 Broadcom Corporation Efficient design to implement LDPC (Low Density Parity Check) decoder
US7395487B2 (en) 2002-08-15 2008-07-01 Broadcom Corporation Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder
US7599655B2 (en) 2003-01-02 2009-10-06 Qualcomm Incorporated Method and apparatus for broadcast services in a communication system
FR2853164A1 (fr) * 2003-03-31 2004-10-01 France Telecom Procede de codage correcteur d'erreur utilisant au moins deux fois un meme code elementaire, procede de codage, dispositifs de codage et de decodage correspondants
US8718279B2 (en) 2003-07-08 2014-05-06 Qualcomm Incorporated Apparatus and method for a secure broadcast system
US8724803B2 (en) 2003-09-02 2014-05-13 Qualcomm Incorporated Method and apparatus for providing authenticated challenges for broadcast-multicast communications in a communication system
US20050180332A1 (en) * 2004-02-13 2005-08-18 Broadcom Corporation Low latency interleaving and deinterleaving
CN1822509B (zh) * 2004-10-04 2011-06-08 美国博通公司 低密度奇偶校验解码器及其解码方法
KR100594043B1 (ko) * 2004-11-08 2006-06-30 삼성전자주식회사 고속 터보 디코더에서 병행방식의 디 래이트 매칭을수행하는 입력 버퍼 장치
US20070194945A1 (en) * 2004-12-07 2007-08-23 Paul Atkinson Mobile Device for Selectively Activating a Target and Method of Using Same
FR2888062A1 (fr) * 2005-07-04 2007-01-05 Groupe Ecoles Telecomm Codeur et turbo decodeur de code produit
US20070266293A1 (en) * 2006-05-10 2007-11-15 Samsung Electronics Co., Ltd. Apparatus and method for high speed data transceiving, and apparatus and method for error-correction processing for the same
US8719670B1 (en) * 2008-05-07 2014-05-06 Sk Hynix Memory Solutions Inc. Coding architecture for multi-level NAND flash memory with stuck cells
FR2955001A1 (fr) * 2010-01-06 2011-07-08 St Microelectronics Grenoble 2 Procede et dispositif d'entrelacement en ligne et en colonne pour blocs de taille variable
US20110202819A1 (en) * 2010-02-12 2011-08-18 Yuan Lin Configurable Error Correction Encoding and Decoding
US9065483B2 (en) * 2013-01-21 2015-06-23 Micron Technology, Inc. Determining soft data using a classification code
KR102147514B1 (ko) 2013-11-27 2020-08-25 씨이비티 주식회사 피에조를 이용한 마이크로 스테이지
US9837245B2 (en) 2015-03-13 2017-12-05 Cebt Co., Ltd. Micro stage for particle beam column using piezo elements as actuator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065147A (en) * 1996-08-28 2000-05-16 France Telecom Process for transmitting information bits with error correction coding, coder and decoder for the implementation of this process
EP1024601A1 (fr) * 1999-01-26 2000-08-02 TRW Inc. Architecture pipeline pour le décodage de codes à concaténation parallèle ou série (turbo codes)
EP1030457A2 (fr) * 1999-02-18 2000-08-23 Interuniversitair Microelektronica Centrum Vzw Méthodes et architectures de système pour décodage Turbo

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5857781B2 (ja) * 1978-01-17 1983-12-21 三菱電機株式会社 符号化復号化方式
US4453251A (en) * 1981-10-13 1984-06-05 Burroughs Corporation Error-correcting memory with low storage overhead and fast correction mechanism
US4547882A (en) * 1983-03-01 1985-10-15 The Board Of Trustees Of The Leland Stanford Jr. University Error detecting and correcting memories
US5559506A (en) * 1994-05-04 1996-09-24 Motorola, Inc. Method and apparatus for encoding and decoding a digital radio signal
FR2778040B1 (fr) * 1998-04-28 2000-05-26 Alsthom Cge Alcatel Procede et dispositif de codage correcteur d'erreur pour des transmissions de donnees numeriques a debit eleve, et procede et dispositif de decodage correspondant
US6252917B1 (en) * 1998-07-17 2001-06-26 Nortel Networks Limited Statistically multiplexed turbo code decoder
US6434203B1 (en) * 1999-02-26 2002-08-13 Qualcomm, Incorporated Memory architecture for map decoder
US6526538B1 (en) * 1998-09-28 2003-02-25 Comtech Telecommunications Corp. Turbo product code decoder
US6292918B1 (en) * 1998-11-05 2001-09-18 Qualcomm Incorporated Efficient iterative decoding
US6678843B2 (en) * 1999-02-18 2004-01-13 Interuniversitair Microelektronics Centrum (Imec) Method and apparatus for interleaving, deinterleaving and combined interleaving-deinterleaving
US6754290B1 (en) * 1999-03-31 2004-06-22 Qualcomm Incorporated Highly parallel map decoder
US6715120B1 (en) * 1999-04-30 2004-03-30 General Electric Company Turbo decoder with modified input for increased code word length and data rate
JP3549788B2 (ja) * 1999-11-05 2004-08-04 三菱電機株式会社 多段符号化方法、多段復号方法、多段符号化装置、多段復号装置およびこれらを用いた情報伝送システム
US6775800B2 (en) * 2000-01-03 2004-08-10 Icoding Technology, Inc. System and method for high speed processing of turbo codes
EP1198894A2 (fr) * 2000-02-10 2002-04-24 Hughes Electronics Corporation Systeme et procede utilisant un decodeur modulaire pour decoder des codes turbo et de type turbo dans un reseau de communication
US6738942B1 (en) * 2000-06-02 2004-05-18 Vitesse Semiconductor Corporation Product code based forward error correction system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065147A (en) * 1996-08-28 2000-05-16 France Telecom Process for transmitting information bits with error correction coding, coder and decoder for the implementation of this process
EP1024601A1 (fr) * 1999-01-26 2000-08-02 TRW Inc. Architecture pipeline pour le décodage de codes à concaténation parallèle ou série (turbo codes)
EP1030457A2 (fr) * 1999-02-18 2000-08-23 Interuniversitair Microelektronica Centrum Vzw Méthodes et architectures de système pour décodage Turbo

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
OKUDA T ET AL: "A FOUR-LEVEL STORAGE 4-GB DRAM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 32, no. 11, 1 November 1997 (1997-11-01), pages 1743 - 1747, XP000752885, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
KR20030063376A (ko) 2003-07-28
CN1479975A (zh) 2004-03-03
EP1332557B1 (fr) 2005-02-09
ES2236354T3 (es) 2005-07-16
FR2816773A1 (fr) 2002-05-17
FR2816773B1 (fr) 2004-11-26
US20040054954A1 (en) 2004-03-18
JP2004523936A (ja) 2004-08-05
KR100822463B1 (ko) 2008-04-16
US7219291B2 (en) 2007-05-15
DE60108892D1 (de) 2005-03-17
DE60108892T2 (de) 2006-04-06
JP3898129B2 (ja) 2007-03-28
CN1320771C (zh) 2007-06-06
WO2002039587A2 (fr) 2002-05-16
EP1332557A2 (fr) 2003-08-06
HK1061937A1 (en) 2004-10-08

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