WO2002043152A3 - Poly fuse rom - Google Patents

Poly fuse rom Download PDF

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Publication number
WO2002043152A3
WO2002043152A3 PCT/EP2001/013467 EP0113467W WO0243152A3 WO 2002043152 A3 WO2002043152 A3 WO 2002043152A3 EP 0113467 W EP0113467 W EP 0113467W WO 0243152 A3 WO0243152 A3 WO 0243152A3
Authority
WO
WIPO (PCT)
Prior art keywords
fuse element
gate
terminal
surrounds
fuse
Prior art date
Application number
PCT/EP2001/013467
Other languages
French (fr)
Other versions
WO2002043152A2 (en
Inventor
Elie G Khoury
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Priority to JP2002544786A priority Critical patent/JP2004515061A/en
Priority to EP01997848A priority patent/EP1340262A2/en
Publication of WO2002043152A2 publication Critical patent/WO2002043152A2/en
Publication of WO2002043152A3 publication Critical patent/WO2002043152A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors

Abstract

A one-time programmable (OTP) structure is implemented using a self-aligned silicided (SALICIDE) poly-silicon fuse. In an example embodiment, the OTP structure is laid out as a fuse element having a first terminal and a second terminal. A switching transistor having a drain, source, and a gate surrounds the fuse element. The drain is coupled to the second terminal of the fuse element surrounds the fuse element. The gate surrounds the drain. The source surrounds the gate. To build transistor with sufficient drive capability for programming the fuse element, the geometry of the gate is laid out in a serpentine or an equivalent pattern increase the effective W/L. A feature of this layout is that OTP cells may be abutted to one-another to form an array. Metallization is arranged so that row lines connect to the first terminal of the fuse element and column lines connect to the gate of the switching transistor. The arrangement enables the placing of read and write circuits at opposite sides of the array. All of the gates in a column may be read simultaneously while providing write current to program one fuse at a time.
PCT/EP2001/013467 2000-11-27 2001-11-19 Poly fuse rom WO2002043152A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002544786A JP2004515061A (en) 2000-11-27 2001-11-19 Poly-fuse ROM having cell structure based on MOS device and method of reading and writing the same
EP01997848A EP1340262A2 (en) 2000-11-27 2001-11-19 Poly fuse rom with mos device based cell structure and the method for read and write therefore

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72341300A 2000-11-27 2000-11-27
US09/723,413 2000-11-27

Publications (2)

Publication Number Publication Date
WO2002043152A2 WO2002043152A2 (en) 2002-05-30
WO2002043152A3 true WO2002043152A3 (en) 2002-09-19

Family

ID=24906158

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/013467 WO2002043152A2 (en) 2000-11-27 2001-11-19 Poly fuse rom

Country Status (4)

Country Link
EP (1) EP1340262A2 (en)
JP (1) JP2004515061A (en)
TW (1) TWI268603B (en)
WO (1) WO2002043152A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101780828B1 (en) 2012-02-06 2017-09-22 매그나칩 반도체 유한회사 Nonvolatile memory device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004051668A1 (en) 2002-12-05 2004-06-17 Koninklijke Philips Electronics N.V. Programmable non-volatile semiconductor memory device
US7136322B2 (en) * 2004-08-05 2006-11-14 Analog Devices, Inc. Programmable semi-fusible link read only memory and method of margin testing same
GB0516423D0 (en) * 2005-08-10 2005-09-14 Cavendish Kinetics Ltd Fuse cell, array and circuit therefor
EP1920441A4 (en) * 2005-08-31 2009-04-29 Ibm Random access electrically programmable-e-fuse rom
US20140027778A1 (en) * 2012-07-25 2014-01-30 International Rectifier Corporation Robust Fused Transistor
US9922720B2 (en) * 2013-03-07 2018-03-20 Intel Corporation Random fuse sensing
EP3382712B1 (en) 2017-03-31 2020-11-04 Nxp B.V. Memory system
FR3087290B1 (en) 2018-10-16 2020-11-06 St Microelectronics Sa MEMORY POINT

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517583A (en) * 1981-03-03 1985-05-14 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit including a fuse element
US5748025A (en) * 1996-03-29 1998-05-05 Intel Corporation Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
WO1998035387A1 (en) * 1997-02-11 1998-08-13 Actel Corporation Antifuse programmed prom cell

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
JPS5863147A (en) * 1981-10-09 1983-04-14 Toshiba Corp Semiconductor device
JPS58197874A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device and manufacture thereof
JP3158738B2 (en) * 1992-08-17 2001-04-23 富士電機株式会社 High breakdown voltage MIS field-effect transistor and semiconductor integrated circuit
US5412593A (en) * 1994-01-12 1995-05-02 Texas Instruments Incorporated Fuse and antifuse reprogrammable link for integrated circuits
US5976943A (en) * 1996-12-27 1999-11-02 Vlsi Technology, Inc. Method for bi-layer programmable resistor
JPH1187696A (en) * 1997-09-12 1999-03-30 Matsushita Electric Works Ltd High breakdown strength semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517583A (en) * 1981-03-03 1985-05-14 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit including a fuse element
US5748025A (en) * 1996-03-29 1998-05-05 Intel Corporation Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
WO1998035387A1 (en) * 1997-02-11 1998-08-13 Actel Corporation Antifuse programmed prom cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101780828B1 (en) 2012-02-06 2017-09-22 매그나칩 반도체 유한회사 Nonvolatile memory device

Also Published As

Publication number Publication date
EP1340262A2 (en) 2003-09-03
JP2004515061A (en) 2004-05-20
WO2002043152A2 (en) 2002-05-30
TWI268603B (en) 2006-12-11

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