WO2002044895A9 - Branch handling for single instruction multiple datapath processor architectures - Google Patents

Branch handling for single instruction multiple datapath processor architectures

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Publication number
WO2002044895A9
WO2002044895A9 PCT/US2001/049903 US0149903W WO0244895A9 WO 2002044895 A9 WO2002044895 A9 WO 2002044895A9 US 0149903 W US0149903 W US 0149903W WO 0244895 A9 WO0244895 A9 WO 0244895A9
Authority
WO
WIPO (PCT)
Prior art keywords
datapaths
states
disabled
deterministic
conditional processing
Prior art date
Application number
PCT/US2001/049903
Other languages
French (fr)
Other versions
WO2002044895A1 (en
Inventor
John L Redford
Original Assignee
Chipwrights Design Inc
John L Redford
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipwrights Design Inc, John L Redford filed Critical Chipwrights Design Inc
Priority to EP01991508A priority Critical patent/EP1348160A1/en
Priority to AU2002231232A priority patent/AU2002231232A1/en
Priority to DE0001348160T priority patent/DE01991508T1/en
Publication of WO2002044895A1 publication Critical patent/WO2002044895A1/en
Publication of WO2002044895A9 publication Critical patent/WO2002044895A9/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions

Definitions

  • This invention relates to handling conditional processing in a single instruction multiple datapath (SIMD) processor architecture.
  • SIMD single instruction multiple datapath
  • a SIMD processor is a parallel processor arcay architecture wherein multiple datapaths are controlled by a single instruction. Each datapath handles one data item at a given time. In a simple example, in a SIMD processor having four datapaths, each data item in a four data item array would be processed in a respective one of the four datapaths.
  • multiple datapaths may be enabled prior to encountering a conditional processing block, such as an if-then-else- processing block.
  • the processor enable (PE) states of each of the datapaths i.e., whether they are enabled or disabled, must be saved in case any of the datapath PE states is changed during execution of the conditional processing block. Further, upon exiting the conditional processing block, the PE states of the datapaths must be restored to the states that existed prior to entry of the conditional processing block.
  • the invention features a method of determining whether datapaths executing a computer program should execute conditional processing in the computer program.
  • the method includes determining whether PE states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Instructions are also provided for performing the determining and the branching.
  • branching is not performed if the program is determined to be deterministic.
  • the determination of whether the PE states of all of the datapaths are disabled includes evaluating a processor enable bit associated with each one of the datapaths.
  • the processor enable bit is enabled if it is a value of one.
  • the processor enable bit is disabled if it is a value of zero.
  • the determination of whether the computer program is deterministic includes evaluating a deterministic bit.
  • the deterministic bit is a first value to indicate that the computer program is deterministic, and is a second value to indicate that the computer program is non-deterministic.
  • the invention features instructions that combine the branching with operations that maintain the PE states during the conditional processing.
  • One such instruction causes the datapaths to establish a state of the datapaths' PE states for the conditional processing, determine whether the established PE states are all disabled, and branch around the conditional processing if the established PE states of all of the datapaths are disabled.
  • conditional processing is, e.g., an if-processing block, and in this case the instructions also cause the datapaths to save a current state of the PE states prior to establishing them for the conditional processing.
  • conditional processing may also include an else-processing block.
  • Embodiments of various aspects of the invention may have one or more of the following advantages. If all datapaths are disabled prior to entering an if-processing block or an else- processing block, there is no work to be accomplished in these blocks. Therefore, branching around the work allows the program to run faster. Combining the branching operation with operations that maintain the PE states during conditional processing provides faster, more efficient program execution, and simpler programming. Testing a deterministic indicator provides a manner of overriding the branching in program code that must meet real time deadlines.
  • FIG. 1 is a block diagram of a single instruction multiple datapath (SIMD) processor.
  • SIMD single instruction multiple datapath
  • FIG. 2 is a block diagram of a program having branch processes for skipping conditional processing in some situations.
  • a single instruction multiple datapath (SIMD) processor 10 includes an instruction cache 12, control logic 14, a serial datapath 16, and a number of parallel datapaths labeled 18a, 18b, 18c, 18, ... 18n.
  • the parallel datapaths 18 write to a memory 20.
  • Each of the datapaths 18 has an associated processor enable (PE) bit 22 that represents the PE state of that datapath.
  • PE processor enable
  • parallel datapath 18a is associated with a PE bit 22a
  • parallel datapath 18b is associated with a PE bit 22b, and so forth.
  • PE bit 22a For example, if PE bit 22a is enabled, data items may be written by parallel datapath 18a; if PE bit 22b is enabled, data items may be written by parallel datapath 18b. If PE bit 22n is enabled, data items may be written by parallel datapath 18n. When a PE bit is disabled, its associated parallel datapath is disabled and data items may not be written by that parallel datapath.
  • the control logic 14 fetches an instruction from the instruction cache 12. The instruction is fed to the serial datapath 16 that provides the instruction to the datapaths 18. Each of the datapaths 18 is read together and written together unless the processor enable bit is disabled for a particular datapath.
  • conditional processing block within the program code (e.g., a processing block that includes one or more if-then-else processing statements)
  • the current PE state of each of the datapaths must be accounted for, so that if any of the PE states of the datapaths are altered during execution of the conditional processing block, the PE states can be restored upon the completion of the conditional processing block.
  • a conditional processing block contains multiple conditional processing operations, some of which may be executed during (i.e., nested within) the processing of other conditional processing operations.
  • the PE state of each datapath must be saved prior to entering each nested conditional operation, and the saved PE state must be restored upon completing the conditional operation.
  • Conditional processing block 42 is an if-then-else processing block in this example, and thus includes an if-processing block 44 followed by an else- processing block 46. It will be understood that program code 40 may contain many other conditional processing blocks 42, and indeed, conditional processing block may include additional if-processing blocks 44 and/or else-processing blocks 46 nested within it. A single conditional processing block with one if-processing block 44 and one else-processing block 46 is shown merely for simplicity in describing an embodiment of the invention.
  • if-processing block 44 the current PE states of datapaths 18 are saved, and an if-processing statement is executed.
  • Branch process 50 is inserted in program code 40 at the start of if-processing block 44.
  • branch process 60 branches 62 around else-processing block 46 to, in this example, the end 64 of conditional processing block 40.
  • the execution of program 40 is deterministic. That is, for one reason or another (such as to meet real-time deadlines), it is desirable to execute program 40 in the same amount of time regardless of whether any work in the program (such as if-processing block 44 and/or else-processing block 46) could be skipped. If so, a deterministic bit (DET, Fig. 1) is set by the programmer in a control register of SLMD processor 10. Branch processes 50, 60 test the state (0 or 1) of the DET bit and do not branch 52, 62 if the DET bit is set.
  • Branch processes 50, 60 combine the branching determination with the PE state setting and maintaining operations, to provide instructions that respectively handle all of the work needed for an if-processing statement and an else-processing statement.
  • a datapath's PE state is, under some conditions, inverted (i.e., from 0 to 1 or 1 to 0) prior to an else-processing block.
  • the instruction for doing so is called a "FLIP" instruction in the copending application.
  • Branch process 60 combines the FLIP instruction with the branching operation, and is of the following form: if(FLIP_PE (Px)) go to Y Branch process 60 will invert the appropriate PE bits (according to the rules described in the copending application) and will branch to destination Y (i.e., the end 64 of else- processing block 46) if none of the PE bits are set.
  • Other embodiments are within the scope of the following claims.
  • branch processes 50, 60 may be used with other instructions that save and manipulate PE states during conditional processing.
  • Another branch process may be inserted at the start of conditional processing block 42 to determine whether the current PE states of all datapaths 18 (i.e. the PE states prior to performing any conditional processing statement) are disabled. If all PE states are disabled, none of datapaths 18 will perform either if-processing block 44 or else-processing block 46. Accordingly, this branch process will branch around the entire conditional processing block 42. As with branch processes 50, 60, branching is not performed if the deterministic bet DET is set.

Abstract

A method of determining whether datapaths (18a-18d) executing in a computer program (40) should execute conditional processing block (42) includes determining whether processor enable (PE) states (22a-22d) of all of the datapaths (18a-18d) are disabled and branching around the conditional processing (42, 44, 46) if the PE states (22a-22d) of all of the datapaths (18a-18d) are disabled. Branching is not performed, even if the PE states (22a-22d) of all of the datapaths (18a-18d) are disabled, if the program (40) is determined to be deterministic. That determination is made by evaluating the state of a deterministic bit (DET, Fig. 1). Instructions are also provided for carrying out the determining and branching operations. The instructions may also be combined with operations that maintain the PE states (22a-22d) during conditional processing.

Description

BRANCH HANDLING FOR SINGLE INSTRUCTION MULTIPLE DATAPATH PROCESSOR ARCHITECTURES
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to a copending application entitled HANDLING CONDITIONAL PROCESSING IN A SINGLE INSTRUCTION MULTIPLE
DATAPATH PROCESSOR ARCHITECTURE, which was filed on the same day as this application and is incorporated herein by reference.
TECHNICAL FIELD
This invention relates to handling conditional processing in a single instruction multiple datapath (SIMD) processor architecture.
BACKGROUND
Parallel processing is an efficient way of processing an array of data items. A SIMD processor is a parallel processor arcay architecture wherein multiple datapaths are controlled by a single instruction. Each datapath handles one data item at a given time. In a simple example, in a SIMD processor having four datapaths, each data item in a four data item array would be processed in a respective one of the four datapaths. During program execution in the SIMD processor, multiple datapaths may be enabled prior to encountering a conditional processing block, such as an if-then-else- processing block. Before executing the conditional processing block, the processor enable (PE) states of each of the datapaths, i.e., whether they are enabled or disabled, must be saved in case any of the datapath PE states is changed during execution of the conditional processing block. Further, upon exiting the conditional processing block, the PE states of the datapaths must be restored to the states that existed prior to entry of the conditional processing block.
SUMMARY
In a general aspect, the invention features a method of determining whether datapaths executing a computer program should execute conditional processing in the computer program. The method includes determining whether PE states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Instructions are also provided for performing the determining and the branching.
In a preferred embodiment, branching is not performed if the program is determined to be deterministic. The determination of whether the PE states of all of the datapaths are disabled includes evaluating a processor enable bit associated with each one of the datapaths. The processor enable bit is enabled if it is a value of one. The processor enable bit is disabled if it is a value of zero.
The determination of whether the computer program is deterministic includes evaluating a deterministic bit. The deterministic bit is a first value to indicate that the computer program is deterministic, and is a second value to indicate that the computer program is non-deterministic.
In another aspect, the invention features instructions that combine the branching with operations that maintain the PE states during the conditional processing. One such instruction causes the datapaths to establish a state of the datapaths' PE states for the conditional processing, determine whether the established PE states are all disabled, and branch around the conditional processing if the established PE states of all of the datapaths are disabled.
The conditional processing is, e.g., an if-processing block, and in this case the instructions also cause the datapaths to save a current state of the PE states prior to establishing them for the conditional processing. The conditional processing may also include an else-processing block.
Embodiments of various aspects of the invention may have one or more of the following advantages. If all datapaths are disabled prior to entering an if-processing block or an else- processing block, there is no work to be accomplished in these blocks. Therefore, branching around the work allows the program to run faster. Combining the branching operation with operations that maintain the PE states during conditional processing provides faster, more efficient program execution, and simpler programming. Testing a deterministic indicator provides a manner of overriding the branching in program code that must meet real time deadlines.
Other features and advantages of the invention will be apparent from the description and drawings, and from the claims. DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram of a single instruction multiple datapath (SIMD) processor.
FIG. 2 is a block diagram of a program having branch processes for skipping conditional processing in some situations.
Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTION
Referring to FIG. 1, a single instruction multiple datapath (SIMD) processor 10 includes an instruction cache 12, control logic 14, a serial datapath 16, and a number of parallel datapaths labeled 18a, 18b, 18c, 18, ... 18n. The parallel datapaths 18 write to a memory 20. Each of the datapaths 18 has an associated processor enable (PE) bit 22 that represents the PE state of that datapath. Specifically, parallel datapath 18a is associated with a PE bit 22a, parallel datapath 18b is associated with a PE bit 22b, and so forth. When a PE bit is enabled, its associated parallel datapath is enabled and data items may be written by that parallel datapath. For example, if PE bit 22a is enabled, data items may be written by parallel datapath 18a; if PE bit 22b is enabled, data items may be written by parallel datapath 18b. If PE bit 22n is enabled, data items may be written by parallel datapath 18n. When a PE bit is disabled, its associated parallel datapath is disabled and data items may not be written by that parallel datapath. In operation, the control logic 14 fetches an instruction from the instruction cache 12. The instruction is fed to the serial datapath 16 that provides the instruction to the datapaths 18. Each of the datapaths 18 is read together and written together unless the processor enable bit is disabled for a particular datapath.
When an instruction causes the SIMD processor 10 to execute a conditional processing block within the program code (e.g., a processing block that includes one or more if-then-else processing statements), the current PE state of each of the datapaths must be accounted for, so that if any of the PE states of the datapaths are altered during execution of the conditional processing block, the PE states can be restored upon the completion of the conditional processing block. Often, a conditional processing block contains multiple conditional processing operations, some of which may be executed during (i.e., nested within) the processing of other conditional processing operations. In order to assure proper operation, the PE state of each datapath must be saved prior to entering each nested conditional operation, and the saved PE state must be restored upon completing the conditional operation.
Referring to Fig. 2, program code 40 that contains a conditional processing block 42 is shown. Conditional processing block 42 is an if-then-else processing block in this example, and thus includes an if-processing block 44 followed by an else- processing block 46. It will be understood that program code 40 may contain many other conditional processing blocks 42, and indeed, conditional processing block may include additional if-processing blocks 44 and/or else-processing blocks 46 nested within it. A single conditional processing block with one if-processing block 44 and one else-processing block 46 is shown merely for simplicity in describing an embodiment of the invention.
At the start of if-processing block 44, the current PE states of datapaths 18 are saved, and an if-processing statement is executed. The PE states of datapaths 18 are then set to either the enable state (PE=1) or the disable state (PE=0) according to the results of the if-processing statement. Only those datapaths having an enabled PE state will perform subsequent processing in if-processing block 44. Accordingly, if all datapaths 18 are set to the disabled PE state, no processing work will be performed within if-processing block 44.
Branch process 50 is inserted in program code 40 at the start of if-processing block 44. Branch process 50 tests the PE states of datapaths 18 upon the execution of the if-processing statement. If all datapaths are disabled (i.e., PE=0), the processing operation in if-processing block 44 may be skipped without affecting the computational results of program 40. Accordingly, branch process 50 branches 52 around if- processing block 44 to else-processing block 46. The PE states of datapaths 18 are also tested at the start of else-processing block
46. If all datapaths 18 are disabled (i.e., PE=0), no processing work will be performed within else-processing block 46. Accordingly, branch process 60 branches 62 around else-processing block 46 to, in this example, the end 64 of conditional processing block 40. In some cases, the execution of program 40 is deterministic. That is, for one reason or another (such as to meet real-time deadlines), it is desirable to execute program 40 in the same amount of time regardless of whether any work in the program (such as if-processing block 44 and/or else-processing block 46) could be skipped. If so, a deterministic bit (DET, Fig. 1) is set by the programmer in a control register of SLMD processor 10. Branch processes 50, 60 test the state (0 or 1) of the DET bit and do not branch 52, 62 if the DET bit is set.
The copending application describes methods of saving and maintaining the PE states of datapaths 18 during conditional processing, such as if-then-else processing. Branch processes 50, 60 combine the branching determination with the PE state setting and maintaining operations, to provide instructions that respectively handle all of the work needed for an if-processing statement and an else-processing statement.
Branch process 50 combines the PE state saving operation with the branching operation, and is of the following form: if (SANEJPE (Px), PE = Pn =0) go to X Branch process 50 saves the PE state of the datapaths in register Px, and then sets the PE state equal to the contents of register Pn. If those contents are 0 (i.e., if none of the datapaths' PE bits are set), branch process 50 branches 52 to destination X (e.g., the subsequent else-processing block 46).
As described in the copending application, a datapath's PE state is, under some conditions, inverted (i.e., from 0 to 1 or 1 to 0) prior to an else-processing block. The instruction for doing so is called a "FLIP" instruction in the copending application. Branch process 60 combines the FLIP instruction with the branching operation, and is of the following form: if(FLIP_PE (Px)) go to Y Branch process 60 will invert the appropriate PE bits (according to the rules described in the copending application) and will branch to destination Y (i.e., the end 64 of else- processing block 46) if none of the PE bits are set. Other embodiments are within the scope of the following claims.
For example, branch processes 50, 60 may be used with other instructions that save and manipulate PE states during conditional processing.
Another branch process may be inserted at the start of conditional processing block 42 to determine whether the current PE states of all datapaths 18 (i.e. the PE states prior to performing any conditional processing statement) are disabled. If all PE states are disabled, none of datapaths 18 will perform either if-processing block 44 or else-processing block 46. Accordingly, this branch process will branch around the entire conditional processing block 42. As with branch processes 50, 60, branching is not performed if the deterministic bet DET is set.
Embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:
1. A method of determining whether a plurality of datapaths executing a computer program should execute conditional processing in the computer program, comprising: determining whether PE states of all of the datapaths are disabled; determining whether the computer program is deterministic; and branching around the conditional processing if the PE states of all of the datapaths are disabled and the computer program is non-deterministic.
2. The method of claim 1 wherein determining whether the PE states of all of the plurality of datapaths are disabled comprises: evaluating a processor enable bit associated with each one of the plurality of datapaths.
3. The method of claim 2 wherein the processor enable bit is enabled if it is1 a value of one.
4. The method of claim 2 wherein the processor enable bit is disabled if it is a value of zero.
5. The method of claim 1 wherein the determining of whether the computer program is deterministic comprises evaluating a deteraiinistic bit.
6. The method of claim 5 wherein the deterministic bit contains a first value indicating the computer program is deterministic.
7. The method of claim 5 wherein the deterministic bit contains a second value indicating the computer program is non-deterministic.
8. A method of determining whether a plurality of datapaths executing in a program should execute a conditional processing block in the program comprising: determining whether all PE states of the datapaths are disabled; and branching around the conditional processing block if the PE states of all the datapaths are disabled.
9. The method of claim 8 wherein determining further comprises: determining whether the program is non-deterministic.
10. The method of claim 9 wherein the branching further comprises: branching if the PE states of all of the datapaths are disabled and the program is non-deterministic .
11. The method of claim 9 further comprising not branching if the program is deterministic.
12. An instruction set executed by datapaths during conditional processing, comprising an instruction that causes the datapaths to deteraiine whether PE states of all of the datapaths are disabled, and branch around the conditional processing if the PE states of all of the datapaths are disabled.
13. The instruction set of claim 12 wherein the branching is not performed if the program is deterministic.
14. An instruction set executed by datapaths during conditional processing, comprising an instruction that causes the datapaths to establish a state of PE states of the datapaths for the conditional processing, determine whether the established PE states of all of the datapaths are disabled, and branch around the conditional processing if the established PE states of all of the datapaths are disabled.
15. The instruction set of claim 14 wherein the conditional processing includes an if-processing block.
16. The instruction set of claim 15 wherein the instruction further causes the datapaths to save a current state of the PE states prior to the establishing
17. The instruction set of claim 14 wherein the conditional processing includes an else-processing block.
18. The instruction set of claim 14 wherein the branching is not performed if the program is detenninistic.
PCT/US2001/049903 2000-11-28 2001-11-09 Branch handling for single instruction multiple datapath processor architectures WO2002044895A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP01991508A EP1348160A1 (en) 2000-11-28 2001-11-09 Branch handling for single instruction multiple datapath processor architectures
AU2002231232A AU2002231232A1 (en) 2000-11-28 2001-11-09 Branch handling for single instruction multiple datapath processor architectures
DE0001348160T DE01991508T1 (en) 2000-11-28 2001-11-09 BRANCH DEVELOPMENT FOR PROCESSOR ARCHITECTURE WITH ONE COMMAND AND MULTIPLE DATA WAYS

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US09/724,196 2000-11-28
US09/724,196 US6931518B1 (en) 2000-11-28 2000-11-28 Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9244689B2 (en) 2004-02-04 2016-01-26 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction
US9582650B2 (en) 2003-11-17 2017-02-28 Bluerisc, Inc. Security of program executables and microprocessors based on compiler-architecture interaction

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US7428014B2 (en) * 2002-11-14 2008-09-23 Koninklijke Philips Electronics N.V. Device for parallel data processing as well as a camera system comprising such a device
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
WO2006057949A2 (en) * 2004-11-23 2006-06-01 Efficient Memory Technology Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US8312254B2 (en) 2008-03-24 2012-11-13 Nvidia Corporation Indirect function call instructions in a synchronous parallel thread processor
CN108703996A (en) * 2018-08-23 2018-10-26 杨飞 It is a kind of to have effects that enhance the pure plant group liquid separation of memory

Family Cites Families (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101960A (en) 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4138720A (en) 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
US4181942A (en) 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
JPS5616248A (en) 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
US4435758A (en) 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4434461A (en) 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
SE8104981L (en) 1981-08-21 1982-07-26 Ibm Svenska Ab METHOD AND DEVICE FOR ADDRESSING A MEMORY
US4604695A (en) 1983-09-30 1986-08-05 Honeywell Information Systems Inc. Nibble and word addressable memory arrangement
DE3479356D1 (en) 1983-12-23 1989-09-14 Hitachi Ltd A data processor with control of the significant bit lenghts of general purpose registers
GB2177526B (en) 1985-06-24 1990-02-14 Pixar Selective operation of processing elements in a single instruction, multiple data stream (simd)computer system
US5045995A (en) 1985-06-24 1991-09-03 Vicom Systems, Inc. Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system
US4896258A (en) 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
US4773038A (en) 1986-02-24 1988-09-20 Thinking Machines Corporation Method of simulating additional processors in a SIMD parallel processor array
US4985832A (en) 1986-09-18 1991-01-15 Digital Equipment Corporation SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors
US5230079A (en) 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
GB2211638A (en) 1987-10-27 1989-07-05 Ibm Simd array processor
US4873626A (en) * 1986-12-17 1989-10-10 Massachusetts Institute Of Technology Parallel processing system with processor array having memory system included in system memory
GB2201015B (en) 1987-02-10 1990-10-10 Univ Southampton Parallel processor array and array element
JPS63245529A (en) 1987-03-31 1988-10-12 Toshiba Corp Register saving and restoring device
US5111389A (en) 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5121498A (en) 1988-05-11 1992-06-09 Massachusetts Institute Of Technology Translator for translating source code for selective unrolling of loops in the source code
US5038282A (en) 1988-05-11 1991-08-06 Massachusetts Institute Of Technology Synchronous processor with simultaneous instruction processing and data transfer
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5224214A (en) 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5157785A (en) 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
CA2045790A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5361363A (en) 1990-10-03 1994-11-01 Thinking Machines Corporation Input/output system for parallel computer for performing parallel file transfers between selected number of input/output devices and another selected number of processing nodes
JPH06500655A (en) 1990-10-03 1994-01-20 スィンキング　マシンズ　コーポレーション parallel computer system
JPH04293135A (en) 1991-03-20 1992-10-16 Yokogawa Hewlett Packard Ltd Memory access system
US5361367A (en) 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
WO1993008525A2 (en) 1991-10-24 1993-04-29 Intel Corporation Data processing system
US5659778A (en) 1992-02-03 1997-08-19 Tm Patents, L.P. System and method of mapping an array to processing elements
US5551039A (en) 1992-02-03 1996-08-27 Thinking Machines Corporation Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements
JP2642039B2 (en) 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション Array processor
AU4804493A (en) 1992-08-07 1994-03-03 Thinking Machines Corporation Massively parallel computer including auxiliary vector processor
US5479624A (en) 1992-10-14 1995-12-26 Lee Research, Inc. High-performance interleaved memory system comprising a prime number of memory modules
US5542074A (en) 1992-10-22 1996-07-30 Maspar Computer Corporation Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
JPH06162228A (en) 1992-11-26 1994-06-10 Sharp Corp Data flow processor device
US5696958A (en) 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
EP0615190A1 (en) 1993-03-11 1994-09-14 Data General Corporation Expandable memory for a digital computer
JPH0756892A (en) 1993-08-10 1995-03-03 Fujitsu Ltd Computer having vector arithmetic unit with mask
JP3415693B2 (en) 1993-12-23 2003-06-09 ノキア モービル フォーンズ リミテッド Interleaving process
US5524223A (en) 1994-01-31 1996-06-04 Motorola, Inc. Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
EP0671685B1 (en) 1994-03-08 1998-11-04 Digital Equipment Corporation Method and apparatus for detecting and executing cross-domain calls in a computer system
US5590352A (en) 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
DE69519449T2 (en) 1994-05-05 2001-06-21 Conexant Systems Inc Space pointer data path
US5590356A (en) 1994-08-23 1996-12-31 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5608886A (en) 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5758176A (en) 1994-09-28 1998-05-26 International Business Machines Corporation Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
WO1996012228A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. Redundant mapping tables
JPH08249306A (en) 1995-03-09 1996-09-27 Sharp Corp Data driven type information processor
US5737572A (en) 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5638533A (en) 1995-10-12 1997-06-10 Lsi Logic Corporation Method and apparatus for providing data to a parallel processing array
US6292879B1 (en) 1995-10-25 2001-09-18 Anthony S. Fong Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer
US5822606A (en) 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5924117A (en) 1996-12-16 1999-07-13 International Business Machines Corporation Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto
US5946222A (en) 1996-12-20 1999-08-31 Oak Technology, Inc. Method and apparatus for performing a masked byte addition operation
US5870581A (en) 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
JPH10254839A (en) 1997-03-11 1998-09-25 Sony Corp Simd controlling parallel processor and arithmetic method
WO1998043168A1 (en) 1997-03-21 1998-10-01 International Business Machines Corporation Address mapping for system memory
JPH10289305A (en) 1997-04-11 1998-10-27 Mitsubishi Electric Corp Image processing device and its method
US6049330A (en) 1997-08-28 2000-04-11 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
WO1999014685A1 (en) 1997-09-16 1999-03-25 Hitachi, Ltd. Data processor and data processing system
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
JPH11272546A (en) 1998-03-23 1999-10-08 Nec Corp Variable length register device
US6067609A (en) 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6121905A (en) 1998-05-11 2000-09-19 Oak Technology, Inc. Method and apparatus for decoding JPEG symbols
US6130631A (en) 1998-05-11 2000-10-10 Oak Technology, Inc. Method and apparatus utilizing a simplified content-addressable memory for JPEG decoding
US6052703A (en) 1998-05-12 2000-04-18 Oak Technology, Inc. Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
US6175892B1 (en) 1998-06-19 2001-01-16 Hitachi America. Ltd. Registers and methods for accessing registers for use in a single instruction multiple data system
US6282628B1 (en) 1999-02-24 2001-08-28 International Business Machines Corporation Method and system for a result code for a single-instruction multiple-data predicate compare operation
WO2001035224A1 (en) 1999-10-26 2001-05-17 Arthur D. Little, Inc. Bit-serial memory access with wide processing elements for simd arrays
US6452864B1 (en) 2000-01-31 2002-09-17 Stmicroelectonics S.R.L. Interleaved memory device for sequential access synchronous reading with simplified address counters
US6282623B1 (en) 2000-02-04 2001-08-28 Motorola Inc. Method for digital signal processing, DSP, mobile communication and audi o-device
DE60011035T2 (en) 2000-03-02 2004-09-16 Stmicroelectronics S.R.L., Agrate Brianza Method for the logical division of a non-volatile memory matrix
JP2002007359A (en) 2000-06-21 2002-01-11 Sony Corp Method and device for parallel processing simd control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9582650B2 (en) 2003-11-17 2017-02-28 Bluerisc, Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US9244689B2 (en) 2004-02-04 2016-01-26 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction

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