WO2002045176B1 - Self-aligned non-volatile memory cell - Google Patents

Self-aligned non-volatile memory cell

Info

Publication number
WO2002045176B1
WO2002045176B1 PCT/US2001/032157 US0132157W WO0245176B1 WO 2002045176 B1 WO2002045176 B1 WO 2002045176B1 US 0132157 W US0132157 W US 0132157W WO 0245176 B1 WO0245176 B1 WO 0245176B1
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
forming
sidewall spacer
region
insulating
Prior art date
Application number
PCT/US2001/032157
Other languages
French (fr)
Other versions
WO2002045176A1 (en
Inventor
Bohumil Lojek
Alan L Renninger
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to KR10-2003-7007086A priority Critical patent/KR20030057560A/en
Priority to JP2002547238A priority patent/JP2004519094A/en
Priority to EP01983134A priority patent/EP1340264A1/en
Priority to AU2002214585A priority patent/AU2002214585A1/en
Priority to CA002427232A priority patent/CA2427232A1/en
Publication of WO2002045176A1 publication Critical patent/WO2002045176A1/en
Publication of WO2002045176B1 publication Critical patent/WO2002045176B1/en
Priority to NO20032188A priority patent/NO20032188L/en
Priority to HK04102566A priority patent/HK1059683A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

Disclosed is a self-aligned non-volatile memory cell (200) comprising a small sidewall spacer (239) electrically coupled and being located next to a main floating gate region (212). Both the small sidewall spacer (239) and the main floating gate region (212) are formed on a substrate (204) and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer (232) which is thinner (260) between the small sidewall spacer (239) and the substrate (204); and is thicker (263) between the main floating gate region (212) and the substrate (204). The small sidewall spacer (239) can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Claims

AMENDED CLAIMS[received by the International Bureau on 19 June 2002 (19.06.02); claims 1, 4, 9, 11, 12 and 13 amended; claims 2, 3 and 6 deleted]
1. A non-volatile memory cell comprising: a semiconductor substrate, with a drain and a source in said substrate; a floating gate formed on said substrate, said floating gate including a main floating gate region and a small sidewall spacer electrically coupled together; a first insulating layer separating said floating gate from said substrate, said first insulating layer including a first insulating portion and a second insulating portion, said first insulating portion separating said small sidewall spacer from said substrate, said second insulating portion separating said main floating gate region from said substrate, wherein, said first insulating portion is thinner than said second insulating portion, and wherein said floating gate further comprises a connecting layer for electrically connecting said small sidewall spacer and said main floating gate region, said connecting layer being formed over and in contact with both said small sidewall spacer and said main floating gate region, and said email sidewall spacer residing along a side and on top of said main floating gate region? a control gate formed over said floating gate; and a second insulating layer separating said control gate and said floating gate.
(cancelled)
3. (cancelled)
4. The non-volatile memory cell of claim 1 wherein said first insulating portion is over said drain. 15
5. The non-volatile memory cell of claim 4 wherein said drain and source are self-aligned with the opposing sides of said main floating gate region.
(cancelled)
7. The non-volatile memory cell of claim 1 wherein said first insulating portion is over said drain.
S. The non-volatile memory cel/X of claim 1 wherein said drain and source are sel -aligned with the opposing sides of said main floating gate region.
9. A method of fabricating a non-volatile memory cell on a semiconductor substrate, said method comprising the steps of: forming a first insulating layer over said substrate; forming a main floating gate region on said first insulating layer; modifying a first portion of said first insulating layer next to a side of said main loating gate region to form a thin insulating region, said thin insulating region being thinner than a second portion of said first insulating layer under said main floating gate region; forming a small sidewall spacer over said thin insulating region; removing a portion of said thin insulating region over said main loating gate region to expose a surface on top of said main floating gate region; forming a thin connecting layer over and in physical contact with both said small sidewall spacer and said main floating gate region, said thin connecting 16
layer contacting said main floating gate region via said surface, whereby said small sidewall spacer is electrically connected to said main floating gate region, and whereby said main floating gate region, said small sidewall spacer and said thin connecting layer form a floating gate of said non-volatile memory cell; forming a second insulating layer over at least said floating gate; and forming a control gate over said second insulating layer and above at least said floating gate.
10. The method of claim 9 wherein said modifying a first portion of said first insulating layer comprises the steps of: removing said irst portion of said irst insulating layer? and forming said thin insulating region where said first portion of said first insulating layer once was.
11. The method of claim 9 wherein said forming said thin insulating region comprises the step of forming a thin insulating layer at least over the place where said f rst portion of said first insulating layer once was and over said main floating gate region.
12. The method of claim 9 wherein said removing a portion of said thin insulating layer over said main floating gate region comprises using photoresist masks and wet-etch to help remove said portion of said thin insulating layer. 17
13. The method of claim 9 wherein said removing a portion of said thin insulating layer over said main floating gate region comprises using a chemical mechanical polishing process to remove said portion of said thin insulating layer.
14. The method of claim 11 wherein said forming a small sidewall spacer comprises the steps of; forming a conducting layer over at least said thin insulating region; and etching said conducting layer to form said small sidewall spacer.
15. The method of claim 14 wherein said etching conducting layer comprises anisot o ically etching.
16. The method of claim 15 wherein said forming a second insulating layer comprises forming an oxide/Nitride/Oxide (ONO) layer.
17. The method of claim 10 wherein said forming a small sidewall spacer comprises the steps oft forming a conducting layer over at least said thin insulating region; and etching said conducting layer to form said small sidewall spacer.
18. The method of claim 17 wherein said etching conducting layer comprises anisotropically etching. 18
19. The method of claim 9 wherein said forming a small sidewall spacer comprises the steps of: forming a conducting layer over at least said thin insulating region; and etching said conducting layer to form said small sidewall spacer.
20. The method of claim 19 wherein said etching conducting layer comprises anisotropically etching.
PCT/US2001/032157 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell WO2002045176A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR10-2003-7007086A KR20030057560A (en) 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell
JP2002547238A JP2004519094A (en) 2000-11-30 2001-10-15 Self-aligned nonvolatile memory cell
EP01983134A EP1340264A1 (en) 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell
AU2002214585A AU2002214585A1 (en) 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell
CA002427232A CA2427232A1 (en) 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell
NO20032188A NO20032188L (en) 2000-11-30 2003-05-14 A self-adjusting non-volatile memory cell
HK04102566A HK1059683A1 (en) 2000-11-30 2004-04-13 Self-aligned non-volatile memory cell

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/727,571 US6479351B1 (en) 2000-11-30 2000-11-30 Method of fabricating a self-aligned non-volatile memory cell
US09/727,571 2000-11-30

Publications (2)

Publication Number Publication Date
WO2002045176A1 WO2002045176A1 (en) 2002-06-06
WO2002045176B1 true WO2002045176B1 (en) 2002-08-22

Family

ID=24923175

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/032157 WO2002045176A1 (en) 2000-11-30 2001-10-15 Self-aligned non-volatile memory cell

Country Status (11)

Country Link
US (3) US6479351B1 (en)
EP (1) EP1340264A1 (en)
JP (1) JP2004519094A (en)
KR (1) KR20030057560A (en)
CN (1) CN1220274C (en)
AU (1) AU2002214585A1 (en)
CA (1) CA2427232A1 (en)
HK (1) HK1059683A1 (en)
NO (1) NO20032188L (en)
TW (1) TW515051B (en)
WO (1) WO2002045176A1 (en)

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Also Published As

Publication number Publication date
CA2427232A1 (en) 2002-06-06
TW515051B (en) 2002-12-21
NO20032188L (en) 2003-07-17
JP2004519094A (en) 2004-06-24
KR20030057560A (en) 2003-07-04
CN1478303A (en) 2004-02-25
US6479351B1 (en) 2002-11-12
AU2002214585A1 (en) 2002-06-11
CN1220274C (en) 2005-09-21
USRE40486E1 (en) 2008-09-09
WO2002045176A1 (en) 2002-06-06
US20020063278A1 (en) 2002-05-30
NO20032188D0 (en) 2003-05-14
HK1059683A1 (en) 2004-07-09
EP1340264A1 (en) 2003-09-03
US6841823B2 (en) 2005-01-11

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