WO2002057717A2 - Sensor signal convertor - Google Patents
Sensor signal convertor Download PDFInfo
- Publication number
- WO2002057717A2 WO2002057717A2 PCT/US2001/050881 US0150881W WO02057717A2 WO 2002057717 A2 WO2002057717 A2 WO 2002057717A2 US 0150881 W US0150881 W US 0150881W WO 02057717 A2 WO02057717 A2 WO 02057717A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- input
- block
- sensing
- output signal
- Prior art date
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
- G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
- G01D5/241—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
- G01D5/2417—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes by varying separation
Definitions
- This invention relates generally to converting sensed signals, such as acceleration and pressure, to a desirable form of electrical signals.
- Sensors such as impact sensors, may be used in a variety of applications, such as automotive airbag systems to protect passengers during collisions.
- Impact sensors may employ a variety of sense elements, such as dual capacitive sense elements or single capacitive sense elements.
- Sensing circuits that interface with dual capacitive sense elements may be less vulnerable to noise such as electromagnetic interference noise or power supply noise, partly because of the differential nature of the sensing circuits. While such differential sensing circuits may be less susceptible to noise, they tend to be rather expensive .
- a more cost efficient approach may be to use single- ended circuits, which typically interface with single capacitive- sense elements.
- single-ended circuits generally tend to be more susceptible to noise.
- Figure 1 is a stylized block diagram of a restraint system in accordance with one embodiment of the present invention
- Figure 2 is a schematic diagram of a sensing circuit that may be implemented in the restraint system of Figure 1, in one embodiment
- FIG 3 is a timing diagram showing clock signals used in the sensing circuit of Figure 2, in accordance with one embodiment of the present invention.
- Figure 4 is a graphical illustration of voltages and transitions of selected nodes of the sensing circuit of Figure 2, in accordance with one embodiment of the present invention.
- the restraint system 10 may be employed in an automobile, for example, to protect passengers during collisions. In one embodiment, the restraint system 10 may automatically deploy an airbag in the event of an activation worthy impact event.
- the restraint system 10 may include a control unit 15, a sensing circuit 20 and a deployment block 25.
- the control unit 15 may be a processor, in one embodiment.
- the sensing block 20 may, in one embodiment, provide a pulse density signal that may be indicative of a sudden acceleration or deceleration, for example.
- the deployment block 25 may determine, in one embodiment, whether an activation worthy impact event has occurred that may require action, such as deployment of airbags . If an activation worthy impact event occurs, the deployment block 25 may provide an activation signal on line 30, in one embodiment.
- sensing circuit 20 may not be limited to the restraint system 10; rather, the sensing circuit 20 may be employed in any one of a variety of applications where converting sensed signals to other forms of electrical signals (e.g., digital signals) may be useful or desirable.
- the sensing circuit 20 includes an input block 217, a sensing block 220, and a converting block 225. As described in more detail below, the sensing circuit 20 converts an output signal from the sensing block 220 to a digital signal when pre-selected voltages are applied to the sensing block 220 and other nodes of the sensing circuit 20, in accordance with one embodiment of the present invention.
- two non-overlapping clocks are used to clock the sensing circuit 20, as shown in Figure 3.
- selected nodes of the sensing circuit 20 are set to a predefined level, such as to a V C M voltage level, as shown in Figure 3.
- the sensing circuit 20 is clocked starting with the UN clock.
- Figure 3 illustrates an output signal, OUT, which is the output of the sensing circuit 20, as described below in more detail.
- the sensing block 220 includes two capacitors, C A and C B , connected at a common node.
- the upward arrow through capacitor C A indicates that the C A capacitance may increase in response to an input, which, in one embodiment, may represent acceleration.
- the term "acceleration,” as utilized herein, may include deceleration, in one embodiment.
- the downward arrow through capacitor C B indicates that the C B capacitance may decrease in response to an input signal.
- the sensing block 220 upon sensing acceleration, provides an output signal to the converting block 225.
- the sensing block 220 in one embodiment, has an input terminal 222 and two output terminals 224, 226.
- the input terminal 222 in one embodiment, is a common node to the C A and C B capacitors.
- the converting block 225 includes an integrator 228 coupled to a comparator 231, which may be further coupled to a latch 234.
- a differential operational amplifier (opamp) 237 along with feedback capacitors, C FN and C FP , forms the integrator 228, in the illustrated embodiment.
- an applied direct current (DC) voltage, Vcu r to the opamp 237 sets a common-mode level of the integrator 228.
- the V CM voltage may be one-fourth or one-third of the supply voltage, which, for example, may be 5 volts.
- integrator 228 is configured in a manner such that input terminals 238, 241 of the integrator 228 are held essentially constant at the V CM voltage level.
- output terminals 246, 248 of the integrator 228 are held essentially constant at the V CM voltage level, during the UN clock cycle.
- the input terminals 238, 241 of the integrator 228, in one embodiment, are coupled to the respective output terminals 224, 226 of the sensing block 220.
- one or more bond wires may be used to connect the sensing block 220 to the integrator 228 of the converting block 225.
- the feedback capacitor, C FN may be coupled between the output terminal 246 and the input terminal 238 of the integrator 228.
- the feedback capacitor, C FP may be coupled between the output terminal 248 and the input terminal 241 of the integrator 228.
- the switch 252 is in the "INT” (i.e., up) position, and during the UN phase, the switch 252 is in the "UN” (i.e., down) position, in one embodiment.
- the switch 253 is in the "INT” position, and during the UN phase, the switch 253 is in the "UN” position, in one embodiment.
- the output terminals 246, 248 of the integrator 228 are coupled to respective input terminals of the comparator 231.
- the comparator 23 in one embodiment, provides an output signal that is a digital "1” if the voltage difference between the output terminals 246, 248 of the integrator 228 is positive, and a digital "0" if it is negative.
- the differential output voltage (i.e., the voltage at the output terminal 246 minus the voltage at the output terminal 248) of the integrator 228 is denoted herein as V 0D .
- the output of the comparator 231 is provided to the latch 234, in one embodiment.
- the latch 234 transfers a "0" or “1” at its input terminal to its output terminal on each falling edge of the INT clock phase (see Figure 3) , in one embodiment.
- the output signal (OUT) of the latch 234 may be a digital bit stream that is fed back into the switches (discussed below) of the input block 217.
- the output of the latch 234 is the output of the sensing circuit 20.
- the density of l's in the OUT signal may be an indication of the magnitude of the amplitude of the input signal to the sensing block 220. That is, if the
- OUT signal contains no l's, for example, the input signal
- the sensing block 220 may be at the low end of its range. If, on the other hand, the OUT signal contains all l's, the input signal of the sensing block 220 may be at a high end of its range. An OUT signal containing l's on roughly 50% of the clock cycles, for example, may represent that the input signal to the sensing block 220 may be in the middle of the range.
- V REF2 may be substantially equal to the supply voltage (not shown) of the sensing circuit 20.
- the supply voltage for example, may be 5 volts in one instance.
- V REFI in one embodiment may be approximately twenty percent of V REF2 , thus, if V REF2 is 5 volts, then V REFi may be 1 volt, for example.
- the sensing circuit 20, in one embodiment, may be calibrated with calibration voltages, V CAL1 and V C A 2 - In some instances, it may be difficult to fabricate the sensing block 220 with tight tolerances.
- the sensing circuit 20 may be calibrated by adjusting the V CAL ⁇ and V CA 2 voltages during a calibration operation after the sensing circuit 20 is assembled.
- V CALI and V CAL2 voltages may be set to values that bring the sensitivity and offset calibration parameters of the sensing circuit 20 within a desirable specification range.
- the Vc A Li and V CM , 2 voltages may remain fixed for the lifetime of the sensing circuit 20.
- a storage unit 235 of the sensing circuit 20 may store the voltages V CALI and V CAL2 in digital form.
- the storage unit 235 may be a non-volatile programmable memory, such as electrically erasable programmable read-only memory (EEPROM) , fuse-blowing memory, or zener-zapping memory.
- EEPROM electrically erasable programmable read-only memory
- fuse-blowing memory fuse-blowing memory
- zener-zapping memory zener-zapping memory
- the input block 217 in the illustrated embodiment includes seven switches 270-276 that are operated by the UN, INT, and OUT digital signals, as shown in Figure 2.
- the switches 270-274 are connected to the node labeled "UN” when the UN signal is high (see Figure 3) , and to the node labeled "INT” when the INT signal is high, in one embodiment.
- the switch 270 may receive V caill and V REF ⁇ voltages, respectively.
- An output terminal of the switch 270 is coupled to a first input terminal of the switch 275, in one embodiment.
- the switch 271 may receive V REFX and CAL2 voltages, respectively.
- an output terminal of the switch 271 is coupled to a second input terminal of the switch 275.
- An output terminal of the switch 275 is coupled to a node 240 of the sensing circuit 20, in one embodiment.
- the switch 273 may receive V REF ⁇ and V CA I voltages, respectively. An output terminal of the switch 273 is coupled to a first input terminal of the switch 276, in one embodiment.
- the switch 274 may receive V CAL2 and V EF ⁇ voltages, respectively. An output terminal of the switch 274 is coupled to a second input terminal of the switch 276, in one embodiment. An output terminal of the switch 276 may be coupled to a node 242 of the sensing circuit 20.
- the switch 272 may be coupled to GROUND and V REF2 , respectively.
- the input terminal 222 of the sensing block 220 is coupled to GROUND, in one embodiment.
- the V REF2 voltage is applied, in one embodiment, to the input terminal 222 of the sensing block 220.
- the same input signal e.g., V REF2 or GROUND voltage level
- the common input terminal 222 of the C ⁇ and C B capacitors of the sensing block 220 is applied to the common input terminal 222 of the C ⁇ and C B capacitors of the sensing block 220.
- an input capacitor C N is coupled between the node 240 and the input terminal 238 of the integrator 228, and an input capacitor Cp is coupled between the node 242 and the input terminal 241 of the integrator 228.
- the input capacitors, C N and C P , and the capacitors C a and C B , of the sensing block 220 deliver charge to (or extract charge from) the feedback capacitors, C FN and C FP , of the integrator 228 during the INT clock phases, in response to the voltage changes at the nodes 240, 242 and at the input terminal 222 of the sensing block 220.
- the switches 270-274 may cause the voltage changes at the nodes 240, 242 and the input terminal 222 of the sensing block 220, when the switches 270-274 change from the UN position to INT position, for example.
- the opamp 237 is switched into unity-gain feedback configuration, which means that the voltages at input terminals 238, 242 and output terminals 246, 248 of the opamp 237 are at the level of the common- mode voltage, V C M in one embodiment. Also, in one embodiment, during the UN phase, the voltages on the nodes 240, 242 and the input terminal 222 of the sensing block 220 are driven to levels determined by the value of the OUT signal. The value of the OUT signal, in one embodiment, depends on the polarity of V 0D (the integrator's differential output voltage) at the end of the previous INT phase.
- the UN phase should be of an adequate duration to allow the voltage levels in the sensing circuit 20 to settle to a static level. In one embodiment, the duration may be one microsecond.
- the switches 270-274 and 252-253 open, and then close to the INT phase connections, in one embodiment.
- the feedback capacitors C FN and C FP are connected around the opamp 237. In one embodiment, the C FN and C FP feedback capacitors may still have a stored voltage as a result of the integrated charge from previous INT phases .
- both the input capacitors (C N and Cp) and the sense element capacitors (C & and C B ) may deliver charge to (or extract charge from) the feedback capacitors (C FN and C FP ) in response to the change in position of the switches 270-274.
- the value of V 0D may have changed to a new value. If this new value is positive, then the OUT signal may be a "1" for the next clock cycle. If the new value is negative, then the OUT signal may be a "0" for the next clock cycle.
- V 0 D the output voltage of the integrator 228 to change (on the INT phase) in a direction that tends to cause the OUT signal to change states (e.g., from zero to one, or vice- versa), in one embodiment.
- V 0D on a given clock cycle is positive, then on the next clock cycle it may be either less positive or negative.
- V 0D on a given clock cycle is negative, then on the next clock cycle it may be either less negative or positive.
- the value of (C a - C B ) which is the response of the sensing block differential capacitance to the input excitation, may affect the size of the charge packets delivered to the integrator 228 on each clock cycle, and ultimately affect the fraction of the OUT signal clock cycles that deliver l's.
- This fractional pulse density (FPD) is the value of the output signal of the sensing circuit 20, in one embodiment.
- the FPD in one embodiment, is defined as the number of clock periods per second having a high output value, divided by the clock frequency.
- the output of the sensing circuit 20 may be a series of alternating ones and zeros .
- a triggering event e.g., existence of sudden acceleration
- This differential capacitance (C a -C B ) may cause the sensing circuit 20 to output more ones than zeros for a selected time interval.
- a graphical illustration of the voltage levels and transitions that may be applied to various nodes of the sensing circuit 20 is shown in one embodiment, for both values of the OUT signal.
- the OUT signal when the OUT signal is a "0," it is an indication that the value of the differential output voltage at the end of the previous INT phase (e.g., Vo D [n-1] ) of the integrator 228 was less than zero.
- the tails of the arrows represent voltage levels during the UN phase, while the arrowheads represent voltage levels during INT phase.
- the actual voltage transitions may occur during the INT clock phase; voltages applied during the UN phase may be viewed, in one embodiment, as starting points for the voltage transitions.
- the voltage on the node 242 may be driven to the level of V REF ⁇ during the unity (UN) clock phase, and then may be driven to the level of V C I (line 410) during the integrate (INT) clock phase.
- the voltage on the node 240 may transition from V CA ⁇ to V REF ⁇
- the voltage at the input terminal 222 of the sensing element 220 transitions from ground to V REF2 (lines 442, 445) on every clock cycle independent of the value of the OUT signal.
- applying the above described selected voltages to the sensing circuit 20 may result in a desirable FPD transfer function, as shown in more detail below.
- the FPD of the sensing circuit 20 may be derived as follows:
- V DIF represents the difference between the two calibration voltages (i . e. , V CAL2 - V CA I ) and V DG /2 represents the difference between the average of the two calibration
- V-,, voltages and V REF ⁇ i.e., . ⁇ CALl " * " "cAL2
- ⁇ V 0DL is the change in the integrator output voltage when the OUT signal is low.
- equation (3) becomes:
- the output of the integrator 228 may be similarly determined, as shown in equation (5) below:
- the fractional pulse density may be related to the above output voltage changes by equation (6) :
- Equation (8) The FPD, based on equation (7) , may be generalized as shown in Equation (8) below:
- the equations (7) and (8) illustrate how the sensing circuit 20 may be calibrated.
- the sensitivity calibration value may be adjusted by altering V DG , which may entail raising or lowering both of the calibration voltages together, in one embodiment. Adjusting V DG may increase or decrease "G" in equation (8) .
- the offset calibration value may be adjusted by changing D IF ⁇ which may entail raising or lowering the calibration voltages in opposite directions, in one embodiment. Altering D ⁇ F may increase or decrease "B" in equation (8).
- One or more embodiments of the present invention may be cost efficient to produce and may also be less susceptible to noise. The cost savings may result since the sensing circuit 20 in one or more embodiments may employ a single sense element, which may be less expensive than dual sense elements. Additionally, one or more embodiments of the present invention may require fewer bondpads and/or wirebonds during manufacturing. In one embodiment, coarse calibration may be performed on the sensing circuit 20 by adjusting the input capacitors, C P and C N , with a metal mask.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002557752A JP2005500511A (en) | 2000-12-29 | 2001-10-29 | Conversion of sensing signal |
AU2002246894A AU2002246894A1 (en) | 2000-12-29 | 2001-10-29 | Sensor signal convertor |
KR1020037008653A KR100546961B1 (en) | 2000-12-29 | 2001-10-29 | Converting sensed signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/751,993 | 2000-12-29 | ||
US09/751,993 US6879056B2 (en) | 2000-12-29 | 2000-12-29 | Converting sensed signals |
Publications (2)
Publication Number | Publication Date |
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WO2002057717A2 true WO2002057717A2 (en) | 2002-07-25 |
WO2002057717A3 WO2002057717A3 (en) | 2003-06-05 |
Family
ID=25024384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/050881 WO2002057717A2 (en) | 2000-12-29 | 2001-10-29 | Sensor signal convertor |
Country Status (7)
Country | Link |
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US (1) | US6879056B2 (en) |
JP (1) | JP2005500511A (en) |
KR (1) | KR100546961B1 (en) |
CN (1) | CN1278103C (en) |
AU (1) | AU2002246894A1 (en) |
TW (1) | TW577985B (en) |
WO (1) | WO2002057717A2 (en) |
Cited By (1)
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EP1784916A1 (en) * | 2004-06-25 | 2007-05-16 | Analog Devices, Inc. | Variable capacitance switched capacitor input system and method |
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US6504750B1 (en) * | 2001-08-27 | 2003-01-07 | Micron Technology, Inc. | Resistive memory element sensing using averaging |
US6826102B2 (en) * | 2002-05-16 | 2004-11-30 | Micron Technology, Inc. | Noise resistant small signal sensing circuit for a memory device |
US6813208B2 (en) | 2002-07-09 | 2004-11-02 | Micron Technology, Inc. | System and method for sensing data stored in a resistive memory element using one bit of a digital count |
JP2008507221A (en) * | 2004-07-17 | 2008-03-06 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Sigma delta modulator |
US7235983B2 (en) * | 2005-03-09 | 2007-06-26 | Analog Devices, Inc. | One terminal capacitor interface circuit |
JP4752417B2 (en) * | 2005-09-16 | 2011-08-17 | パナソニック電工株式会社 | Sensor device |
EP1811309B1 (en) * | 2006-01-20 | 2009-10-07 | STMicroelectronics S.r.l. | Free fall detector device and free fall detection method |
US7528755B2 (en) * | 2007-09-06 | 2009-05-05 | Infineon Technologies Ag | Sigma-delta modulator for operating sensors |
TWI407700B (en) * | 2009-11-04 | 2013-09-01 | Ind Tech Res Inst | Calibration apparatus and method for capacitive sensing devices |
GB2515787B (en) * | 2013-07-04 | 2018-04-18 | Silicon Sensing Systems Ltd | Pickoff transducer wire bond bit detection |
JP6500522B2 (en) * | 2015-03-16 | 2019-04-17 | セイコーエプソン株式会社 | Circuit device, physical quantity detection device, electronic device and moving body |
KR102599059B1 (en) * | 2018-10-11 | 2023-11-08 | 삼성디스플레이 주식회사 | Transition detector and clock data recovery unit including the same |
TWI682182B (en) * | 2019-03-07 | 2020-01-11 | 緯創資通股份有限公司 | Detection equipment and detecting method thereof |
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-
2001
- 2001-10-29 WO PCT/US2001/050881 patent/WO2002057717A2/en active IP Right Grant
- 2001-10-29 AU AU2002246894A patent/AU2002246894A1/en not_active Abandoned
- 2001-10-29 CN CNB018228518A patent/CN1278103C/en not_active Expired - Fee Related
- 2001-10-29 KR KR1020037008653A patent/KR100546961B1/en active IP Right Grant
- 2001-10-29 JP JP2002557752A patent/JP2005500511A/en active Pending
- 2001-11-07 TW TW090127654A patent/TW577985B/en not_active IP Right Cessation
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EP1784916A4 (en) * | 2004-06-25 | 2007-11-14 | Analog Devices Inc | Variable capacitance switched capacitor input system and method |
Also Published As
Publication number | Publication date |
---|---|
TW577985B (en) | 2004-03-01 |
US20020117895A1 (en) | 2002-08-29 |
KR20030074682A (en) | 2003-09-19 |
KR100546961B1 (en) | 2006-01-26 |
WO2002057717A3 (en) | 2003-06-05 |
AU2002246894A1 (en) | 2002-07-30 |
CN1278103C (en) | 2006-10-04 |
CN1492990A (en) | 2004-04-28 |
JP2005500511A (en) | 2005-01-06 |
US6879056B2 (en) | 2005-04-12 |
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