WO2002058073A3 - Method of reducing disturbs in non-volatile memory - Google Patents

Method of reducing disturbs in non-volatile memory Download PDF

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Publication number
WO2002058073A3
WO2002058073A3 PCT/US2001/050168 US0150168W WO02058073A3 WO 2002058073 A3 WO2002058073 A3 WO 2002058073A3 US 0150168 W US0150168 W US 0150168W WO 02058073 A3 WO02058073 A3 WO 02058073A3
Authority
WO
WIPO (PCT)
Prior art keywords
units
programmed
volatile memory
rate
planes
Prior art date
Application number
PCT/US2001/050168
Other languages
French (fr)
Other versions
WO2002058073A2 (en
Inventor
John S Mangan
Daniel C Guterman
George Samachisa
Brian Murphy
Chi-Ming Wang
Khandker N Quader
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/703,083 external-priority patent/US6570785B1/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Priority to KR1020037006026A priority Critical patent/KR100895216B1/en
Priority to AU2002251705A priority patent/AU2002251705A1/en
Priority to JP2002558274A priority patent/JP3976682B2/en
Publication of WO2002058073A2 publication Critical patent/WO2002058073A2/en
Publication of WO2002058073A3 publication Critical patent/WO2002058073A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control

Abstract

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in distrubs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selected the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drives change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
PCT/US2001/050168 2000-10-31 2001-10-26 Method of reducing disturbs in non-volatile memory WO2002058073A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020037006026A KR100895216B1 (en) 2000-10-31 2001-10-26 Method of reducing disturbs in non-volatile memory
AU2002251705A AU2002251705A1 (en) 2000-10-31 2001-10-26 Method of reducing disturbs in non-volatile memory
JP2002558274A JP3976682B2 (en) 2000-10-31 2001-10-26 Method for reducing interference in non-volatile memory

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/703,083 2000-10-31
US09/703,083 US6570785B1 (en) 2000-10-31 2000-10-31 Method of reducing disturbs in non-volatile memory
US09/759,835 US6717851B2 (en) 2000-10-31 2001-01-10 Method of reducing disturbs in non-volatile memory
US09/759,835 2001-01-10

Publications (2)

Publication Number Publication Date
WO2002058073A2 WO2002058073A2 (en) 2002-07-25
WO2002058073A3 true WO2002058073A3 (en) 2003-12-04

Family

ID=27107071

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/050168 WO2002058073A2 (en) 2000-10-31 2001-10-26 Method of reducing disturbs in non-volatile memory

Country Status (6)

Country Link
US (5) US6717851B2 (en)
JP (2) JP3976682B2 (en)
KR (1) KR100895216B1 (en)
AU (1) AU2002251705A1 (en)
TW (1) TW540054B (en)
WO (1) WO2002058073A2 (en)

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Also Published As

Publication number Publication date
US20020051383A1 (en) 2002-05-02
US20040027865A1 (en) 2004-02-12
AU2002251705A1 (en) 2002-07-30
KR100895216B1 (en) 2009-05-06
JP2004524638A (en) 2004-08-12
KR20030048103A (en) 2003-06-18
TW540054B (en) 2003-07-01
US7145804B2 (en) 2006-12-05
US20050146933A1 (en) 2005-07-07
JP4533871B2 (en) 2010-09-01
JP3976682B2 (en) 2007-09-19
US6888752B2 (en) 2005-05-03
US6977844B2 (en) 2005-12-20
JP2006351192A (en) 2006-12-28
US6717851B2 (en) 2004-04-06
US20070076510A1 (en) 2007-04-05
US7468915B2 (en) 2008-12-23
US20060023507A1 (en) 2006-02-02
WO2002058073A2 (en) 2002-07-25

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