WO2002058317A3 - Pll/dll dual loop data synchronization - Google Patents

Pll/dll dual loop data synchronization Download PDF

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Publication number
WO2002058317A3
WO2002058317A3 PCT/US2001/049775 US0149775W WO02058317A3 WO 2002058317 A3 WO2002058317 A3 WO 2002058317A3 US 0149775 W US0149775 W US 0149775W WO 02058317 A3 WO02058317 A3 WO 02058317A3
Authority
WO
WIPO (PCT)
Prior art keywords
dll
pll
loop
dual loop
serializer
Prior art date
Application number
PCT/US2001/049775
Other languages
French (fr)
Other versions
WO2002058317A2 (en
Inventor
Benjamin Tang
Scott Southwell
Nicholas Steffen
Original Assignee
Primarion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Primarion Inc filed Critical Primarion Inc
Priority to AU2002251700A priority Critical patent/AU2002251700A1/en
Publication of WO2002058317A2 publication Critical patent/WO2002058317A2/en
Publication of WO2002058317A3 publication Critical patent/WO2002058317A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path at the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
PCT/US2001/049775 2000-12-20 2001-12-20 Pll/dll dual loop data synchronization WO2002058317A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002251700A AU2002251700A1 (en) 2000-12-20 2001-12-20 Pll/dll dual loop data synchronization

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25704400P 2000-12-20 2000-12-20
US60/257,044 2000-12-20

Publications (2)

Publication Number Publication Date
WO2002058317A2 WO2002058317A2 (en) 2002-07-25
WO2002058317A3 true WO2002058317A3 (en) 2003-12-31

Family

ID=22974665

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/049775 WO2002058317A2 (en) 2000-12-20 2001-12-20 Pll/dll dual loop data synchronization

Country Status (3)

Country Link
US (3) US20020075981A1 (en)
AU (1) AU2002251700A1 (en)
WO (1) WO2002058317A2 (en)

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Also Published As

Publication number Publication date
US20100166132A1 (en) 2010-07-01
US7743168B2 (en) 2010-06-22
US8239579B2 (en) 2012-08-07
US20080212730A1 (en) 2008-09-04
WO2002058317A2 (en) 2002-07-25
US20020075981A1 (en) 2002-06-20
AU2002251700A1 (en) 2002-07-30

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