WO2002059967A3 - Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations - Google Patents

Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations Download PDF

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Publication number
WO2002059967A3
WO2002059967A3 PCT/US2002/000121 US0200121W WO02059967A3 WO 2002059967 A3 WO2002059967 A3 WO 2002059967A3 US 0200121 W US0200121 W US 0200121W WO 02059967 A3 WO02059967 A3 WO 02059967A3
Authority
WO
WIPO (PCT)
Prior art keywords
fabricating
integrated circuits
vias
reverse engineering
same
Prior art date
Application number
PCT/US2002/000121
Other languages
French (fr)
Other versions
WO2002059967A2 (en
Inventor
Lap-Wai Chow
James P Baukas
William M Clark Jr
Original Assignee
Hrl Lab Llc
Lap-Wai Chow
James P Baukas
William M Clark Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hrl Lab Llc, Lap-Wai Chow, James P Baukas, William M Clark Jr filed Critical Hrl Lab Llc
Priority to AU2002234201A priority Critical patent/AU2002234201A1/en
Publication of WO2002059967A2 publication Critical patent/WO2002059967A2/en
Publication of WO2002059967A3 publication Critical patent/WO2002059967A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization

Abstract

A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such 'trick' via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
PCT/US2002/000121 2001-01-24 2002-01-03 Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations WO2002059967A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002234201A AU2002234201A1 (en) 2001-01-24 2002-01-03 Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/768,911 US6791191B2 (en) 2001-01-24 2001-01-24 Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US09/768,911 2001-01-24

Publications (2)

Publication Number Publication Date
WO2002059967A2 WO2002059967A2 (en) 2002-08-01
WO2002059967A3 true WO2002059967A3 (en) 2003-02-20

Family

ID=25083849

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/000121 WO2002059967A2 (en) 2001-01-24 2002-01-03 Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations

Country Status (4)

Country Link
US (1) US6791191B2 (en)
AU (1) AU2002234201A1 (en)
TW (1) TW577138B (en)
WO (1) WO2002059967A2 (en)

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US8510700B2 (en) 2009-02-24 2013-08-13 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
US9735781B2 (en) 2009-02-24 2017-08-15 Syphermedia International, Inc. Physically unclonable camouflage structure and methods for fabricating same
US10691860B2 (en) 2009-02-24 2020-06-23 Rambus Inc. Secure logic locking and configuration with camouflaged programmable micro netlists
US8418091B2 (en) * 2009-02-24 2013-04-09 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit
US8111089B2 (en) * 2009-05-28 2012-02-07 Syphermedia International, Inc. Building block for a secure CMOS logic cell library
DE102012219661A1 (en) 2012-10-26 2014-04-30 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Individualized power supply of integrated circuit devices as protection against side channel attacks
US9343411B2 (en) * 2013-01-29 2016-05-17 Intel Corporation Techniques for enhancing fracture resistance of interconnects
DE102013224060B4 (en) 2013-11-26 2020-04-02 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Difficulty of optical reverse engineering
US9479176B1 (en) 2013-12-09 2016-10-25 Rambus Inc. Methods and circuits for protecting integrated circuits from reverse engineering
FR3059145B1 (en) 2016-11-22 2019-07-19 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT
FR3059146A1 (en) 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
FR3059144B1 (en) 2016-11-22 2019-05-31 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDING ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT
US10568202B2 (en) 2017-07-25 2020-02-18 International Business Machines Corporation Tamper-respondent assembly with interconnect characteristic(s) obscuring circuit layout
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same
FR3108781B1 (en) 2020-03-30 2022-03-18 Commissariat Energie Atomique Method for producing on a plate a plurality of chips each comprising an individualization zone

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Also Published As

Publication number Publication date
AU2002234201A1 (en) 2002-08-06
WO2002059967A2 (en) 2002-08-01
TW577138B (en) 2004-02-21
US20020096777A1 (en) 2002-07-25
US6791191B2 (en) 2004-09-14

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