WO2002069238A2 - Managing coherence via put/get windows - Google Patents

Managing coherence via put/get windows Download PDF

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Publication number
WO2002069238A2
WO2002069238A2 PCT/US2002/005587 US0205587W WO02069238A2 WO 2002069238 A2 WO2002069238 A2 WO 2002069238A2 US 0205587 W US0205587 W US 0205587W WO 02069238 A2 WO02069238 A2 WO 02069238A2
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WO
WIPO (PCT)
Prior art keywords
cache
processor
data
memory
activities
Prior art date
Application number
PCT/US2002/005587
Other languages
French (fr)
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WO2002069238A3 (en
Inventor
Matthias A. Blumrich
Dong Chen
Paul W. Coteus
Alan G. Gara
Mark E. Giampapa
Philip Heidelberger
Dirk Hoenicke
Martin Ohmacht
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International Business Machines Corporation
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Publication date
Priority to US10/468,995 priority Critical patent/US7870343B2/en
Priority to AU2002245518A priority patent/AU2002245518A1/en
Priority to KR1020037010817A priority patent/KR100615411B1/en
Priority to DE60233055T priority patent/DE60233055D1/en
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to PCT/US2002/005587 priority patent/WO2002069238A2/en
Priority to AT02713681T priority patent/ATE437402T1/en
Priority to IL15751702A priority patent/IL157517A0/en
Priority to CNB028054318A priority patent/CN1286016C/en
Priority to CA002437663A priority patent/CA2437663A1/en
Priority to JP2002568284A priority patent/JP3954969B2/en
Priority to EP02713681A priority patent/EP1410216B1/en
Publication of WO2002069238A2 publication Critical patent/WO2002069238A2/en
Publication of WO2002069238A3 publication Critical patent/WO2002069238A3/en
Priority to US12/543,890 priority patent/US8122197B2/en
Priority to US12/953,770 priority patent/US8161248B2/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/20709—Modifications to facilitate cooling, ventilating, or heating for server racks or cabinets; for data centers, e.g. 19-inch computer racks
    • H05K7/20836—Thermal management, e.g. server temperature control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04D—NON-POSITIVE-DISPLACEMENT PUMPS
    • F04D25/00—Pumping installations or systems
    • F04D25/16—Combinations of two or more pumps ; Producing two or more separate gas flows
    • F04D25/166—Combinations of two or more pumps ; Producing two or more separate gas flows using fans
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04D—NON-POSITIVE-DISPLACEMENT PUMPS
    • F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
    • F04D27/004—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids by varying driving speed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F24—HEATING; RANGES; VENTILATING
    • F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
    • F24F11/00—Control or safety arrangements
    • F24F11/70—Control systems characterised by their outputs; Constructional details thereof
    • F24F11/72—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure
    • F24F11/74—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure for controlling air flow rate or air velocity
    • F24F11/77—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure for controlling air flow rate or air velocity by controlling the speed of ventilators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B30/00—Energy efficient heating, ventilation or air conditioning [HVAC]
    • Y02B30/70—Efficient control or regulation technologies, e.g. for control of refrigerant flow, motor or heating

Definitions

  • This invention relates to the field of distributed-memory message-passing parallel computer design and system software, as applied for example to computation in the field of life sciences.
  • Each processing node of the supercomputer architecture is a semiconductor device that includes two electronic processors (among other components).
  • One of these processors is designated the “Compute Processor” and, in the common made operation, is dedicated to application computation.
  • the other processor is the “I/O Processor,” which, in the common mode of operation, is a service processor dedicated to performing activities in support of message-passing communication.
  • Each of these processors contains a separate first-level cache (LI) which may contain a copy of data stored in a common memory accessed by both processors. If one processor changes its LI copy of a memory location, and the other processor has a copy of the same location, the two copies become "coherent” if they are made to be the same.
  • LI first-level cache
  • Message passing is a commonly-known form of computer communication wherein processors explicitly copy data from their own memory to that of another node.
  • the I/O Processor is principally used to facilitate message passing between the common memory of a node and the common memory of other nodes. Therefore, it both produces data (when a message is received) that is consumed by the Compute Processor, and consumes data (in order to send a message) that is produced by the Compute Processor.
  • both processors it is very common for both processors to have a copy of the same memory location in their Lls. If the messages passed are small and many, then the problem is exacerbated. Thus, there is a clear need to find a way to make the Lls of each processor coherent, without extensive circuitry, and with minimal impact on performance.
  • One-sided communication uses a
  • put/get message-passing paradigm, where messages carry the source (for get) or the destination (for put) memory address.
  • puts and gets are typically assembled in batches and issued together. This keeps the independently operating processors in rough synchronization, maximizing performance.
  • the time during which puts and gets occur is termed the put/get window. This window extends both in time (when it occurs) and in memory (over the range of memory addresses carried by the put or get messages).
  • Figure 2 shows a put/get window 30 having a number of distinct messages.
  • Put/get windows extend the concept of coherence to processors on different processing nodes of the massively parallel supercomputer. Implementations of put/get windows must insure that all messages put to a window during the time it is open are received into the memory of the window before the window is closed. Similarly, a get on the memory of the window is only allowed during the time the window is open. Therefore, put/get windows are simply a mechanism for a node to synchronize with remote processors operating on its memory.
  • the management of a put/get window is currently accomplished by either buffering the put/get messages or by using explicit synchronization messages. Buffering the messages consumes memory, which is always in limited supply. Explicit synchronization for each window suffers from the long latency of round-trip messages between all the nodes accessing the window. Therefore, on large-scale machines such as the one described in copending patent application no.
  • An object of this invention is to provide an improved procedure for managing coherence in a parallel processing computer system.
  • Another object of the present invention is to achieve coherency between the first- level caches of the processors of a multi-processor node without extensive circuitry and with minimal impact on the performance of each processor.
  • a further object of the invention is to provide a method and apparatus, working in conjunction with software algorithms, to accomplish efficient high speed message- passing communications between processors or a direct memory access (DMA) device, which maintains coherence without significantly reducing performance.
  • DMA direct memory access
  • the invention provides a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing massively parallel supercomputer (such as the one described in copending patent application no. (attorney Docket
  • the invention provides a mechanism to ensure that the data being "put" (sent) is not in the cache of either processor, and that the data being "gotten” (received) is also not in the cache of either processor.
  • the invention reduces the total amount of work required to achieve coherence and allow that work to be amortized over a large number of individual messages.
  • both processing elements within a node must perform this work, the invention enables this to happen concurrently. Further, when required, these activities can be coordinated over a large number of independent nodes in the massively parallel machine by employing the Global Barrier Network described in copending patent application no. (attorney Docket 15275).
  • the invention provides a hardware apparatus that assists the above-described cache coherence software algorithm, and limits the total time (or latency) required to achieve cache coherence over the Put/Get Window.
  • This apparatus is a simple extension to the hardware address decoder that creates, in the physical memory address space of the node, an area of memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
  • This further speeds the coherence activities because it allows garbage data (which the processor will never use) to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance. The performance is faster because this garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
  • data cache block flush and invalidate may be used to write data from the memory area of the first processor into the shared memory area, while at the same time, preventing the first processor from using data the data written in its memory area.
  • data cache block zero may be used to write data from the memory area of the first processor into the shared memory.
  • Figure 1 shows a two processor node embodying this invention.
  • Figure 2 illustrates a put/get window that may be used in the practice of this invention.
  • the present invention relates to a method and apparatus for managing coherence of a multi-processor computer system.
  • Figure 1 illustrates a node 10 that may embody this invention.
  • Each of the processors 12, 14 of node 10 has a respective cache memory area 16, 20, and the two processors share a third memory area 22.
  • the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache memory coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm.
  • the software algorithm uses the opening and closing of put/get windows to coordinate the activities required to achieve cache coherence.
  • the hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of physical memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
  • this invention utilizes a principal referred to as "put/get" data transfer.
  • put/get data transfer
  • typical application messaging traffic involves an increasing number of messages, where each such message contains a piece of work performed by other nodes in the multi -computer.
  • one node scatters locally produced work items to numerous other nodes (a "put"), while assembling numerous remotely produced work items into its local memory (a "get”).
  • put locally produced work items
  • get assembling numerous remotely produced work items into its local memory
  • One-Sided Communication uses a "put/get" message-passing paradigm, where messages carry the source (for "get”) or destination (for "put") memory address.
  • put/get window This time during which puts and gets occur is termed the put/get window. This window extends both in time (when it occurs) and in memory (over which range of memory addresses does the data in the put or get reside).
  • FIG. 2 shows a put/get window 30 having a number of distinct messages.
  • algorithms often proceed as a series of steps, where each step consists of a computation phase followed by a communication phase.
  • the nodes exchange data produced by the computation phase and required for the next step of the algorithm.
  • the phases are usually tightly synchronized, sot that the communication happens all at once over the entire machine. Therefore, the cost of managing the synchronization of put/get windows can be amortized over a large number of nodes at the start and end of each communication phase.
  • a global operation can be used to open many put/get windows at the start of a communication.
  • the present invention utilizes this put/get window to provide a simple means to manage memory coherence.
  • a software algorithm is provided that simplifies and significantly speeds the management of cache coherence in a message passing massively parallel supercomputer (such as the one described in copending patent application no. (attorney Docket
  • this algorithm uses the opening and closing of "Put/Get Windows" to coordinate the activities required to achieve memory coherence.
  • this invention provides a mechanism to ensure that the data being "put" (sent) is not in the cache of either processor, and that the data being "gotten” (received) is also not in the cache of either processor.
  • this invention reduces the total amount of work required to achieve coherence and allow that work to be amortized over a large number of individual messages. Also, since both processing elements within a node must perform this work, this invention enables this to happen concurrently. Further, when required, these activities can be coordinated over a large number of independent nodes in the massively parallel machine by employing the Global Barrier Network described in copending patent application no. (attorney Docket 1527).
  • a novel hardware apparatus that assists the above-described cache coherence algorithm, and limits the total time (or latency) required to achieve cache coherence over the Put/Get Window.
  • This apparatus is a simple extension to the hardware address decoder that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
  • This further speeds the coherence activities because it allows garbage data (which the processor will never use) to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance. The performance is faster because this garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
  • the first embodiment may be preferred if the size of the message being received is smaller than the size of LI, while the second embodiment may be preferred if the size of the message received is larger than LI .
  • DCBF data cache block flush and invalidate
  • the software then allows the computer processor to continue to process instructions, and closes the put/get window using a global synchronization operation such as the global barrier described in copending application copending application D#15272 Global Interrupt and Barrier Networks.
  • Second embodiment If the size of the message received is larger than the size of LI.
  • the invention makes use of an instruction termed "data cache block zero" (DCBZ), on a reserved contiguous physical address range equal in size to LI .
  • DCBZ creates a new cache line with contents of zero. If a new cache line is not available, then another cache line in LI (for example, the least recently used line), has its data written back to the common memory, and is then zero'ed with the address given by the DCBZ instruction.
  • DCBZ is a PowerPC BookE instruction; similar instructions exist for other processors.
  • the software executes DCBZ to each line of the reserved area consecutively, where a line of the reserved area is equal in size to a cache line and like-aligned. This causes all lines in the LI to be flushed, i.e., all modified lines are written back to common memory, because the entire contents of LI is replaced quickly from the reserved area.
  • the software then allows the compute processor to continue to process instructions, and closes the put/get window using a global synchronization operation such as the global barrier described in copending application copending application D#l 5272 Global Interrupt and Barrier Networks.
  • DCBF instructions are slower than DCBZ, then the operating system may use the DCBZ instruction for messages smaller then LI and vice-versa.
  • the I/O Processor need not flush its cache at all if the communication memory space is marked write-through to its LI cache.
  • the making of the above-mentioned global "and" in a short interval of time, which allows the put/get window to be made temporarily narrow, is discussed in detail in related patent application no. (Attorney Docket: 15258 ).

Abstract

A method and apparatus for managing coherence between two processors (12, 14) of a two processor node (10) of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node (10), an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

Description

MANAGING COHERENCE VIA PUT/GET WINDOWS
CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention claims the benefit of commonly-owned, co-pending United
States Provisional Patent Application Serial Number 60/271,124 filed February 24,
2001 entitled MASSIVELY PARALLEL SUPERCOMPUTER, the whole contents and disclosure of which is expressly incorporated by reference herein as if fully set forth herein. This patent application is additionally related to the following commonly-owned, co-pending United States Patent Applications filed on even date herewith, the entire contents and disclosure of each of which is expressly incorporated by reference herein as if fully set forth herein. U.S. patent application
Serial No. (YOR920020027US1, YOR920020044US1 (15270)), for "Class Networking Routing"; U.S. patent application Serial No. (YOR920020028US 1 (15271)), for "A Global Tree Network for Computing Structures"; U.S. patent application Serial No. (YOR920020029US1 (15272)), for 'Global Interrupt and Barrier Networks"; U.S. patent application Serial No. (YOR920020030US1 (15273)), for Optimized Scalable Network Switch"; U.S. patent application Serial No. (YOR920020031US1, YOR920020032US1 (15258)), for "Arithmetic Functions in Torus and Tree Networks'; U.S. patent application Serial No. (YOR920020033US1, YOR920020034US1 (15259)), for 'Data Capture Technique for High Speed Signaling"; U.S. patent application Serial No. (YOR920020035US1 (15260)), for 'Managing Coherence Via Put/Get Windows'; U.S. patent application Serial No. (YOR920020036US1, YOR920020037US1 (15261)), for "Low Latency Memory Access And Synchronization"; U.S. patent application Serial No. (YOR920020038US1 (15276), for 'Twin-Tailed Fail-Over for Fileservers Maintaining Full Performance in the Presence of Failure"; U.S. patent application Serial No. (YOR920020039US1 (15277)), for "Fault Isolation Through No- Overhead Link Level Checksums'; U.S. patent application Serial No.
(YOR920020040US1 (15278)), for "Ethernet Addressing Via Physical Location for Massively Parallel Systems"; U.S. patent application Serial No. (YOR920020041US1 (15274)), for "Fault Tolerance in a Supercomputer Through Dynamic Repartitioning"; U.S. patent application Serial No. (YOR920020042US 1 (15279)), for "Checkpointing Filesystem"; U.S. patent application Serial No. (YOR920020043US1 (15262)), for "Efficient Implementation of Multidimensional Fast Fourier Transform on a Distributed-Memory Parallel Multi-Node Computer"; U.S. patent application Serial No. (YOR9-20010211US2 (15275)), for "A Novel Massively Parallel Supercomputer"; and U.S. patent application Serial No. (YOR920020045US1 (15263)), for "Smart Fan Modules and System".
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates to the field of distributed-memory message-passing parallel computer design and system software, as applied for example to computation in the field of life sciences.
2. BACKGROUND ART
In provisional patent application no. 60/271,124 titled "A Novel Massively Parallel Supercomputer," therein is described a massively parallel supercomputer architecture in the form of a three-dimensional torus designed to deliver processing power on the order of teraOPS (trillion operations per second) for a wide range of applications. The architecture comprises 65,536 processing nodes organized as a 64x32x32 three-dimensional torus, with each processing node connected to six (6) neighboring nodes.
Each processing node of the supercomputer architecture is a semiconductor device that includes two electronic processors (among other components). One of these processors is designated the "Compute Processor" and, in the common made operation, is dedicated to application computation. The other processor is the "I/O Processor," which, in the common mode of operation, is a service processor dedicated to performing activities in support of message-passing communication. Each of these processors contains a separate first-level cache (LI) which may contain a copy of data stored in a common memory accessed by both processors. If one processor changes its LI copy of a memory location, and the other processor has a copy of the same location, the two copies become "coherent" if they are made to be the same. Message passing is a commonly-known form of computer communication wherein processors explicitly copy data from their own memory to that of another node. In the dual-processor node disclosed in the above-identified provisional patent application no. 60/271,124, the I/O Processor is principally used to facilitate message passing between the common memory of a node and the common memory of other nodes. Therefore, it both produces data (when a message is received) that is consumed by the Compute Processor, and consumes data (in order to send a message) that is produced by the Compute Processor. As a result, it is very common for both processors to have a copy of the same memory location in their Lls. If the messages passed are small and many, then the problem is exacerbated. Thus, there is a clear need to find a way to make the Lls of each processor coherent, without extensive circuitry, and with minimal impact on performance.
As massively parallel computers are scaled to thousands of processing nodes, typical application messaging traffic involves an increasing number of messages, where each such message contains information communicated by other nodes in the computer. Generally, one node scatters locally-produced messages to some number of other nodes, while receiving some number of remotely produced messages into its local memory. Overall performance for these large-scale computers is often limited by the message-passing performance of the system.
For such data transfers, a common message-passing interface, described in the literature (see for example http://www.mpi-forum.org/docs/docs.html, under MPI-2), is known as "one-sided communication." One-sided communication uses a
"put/get" message-passing paradigm, where messages carry the source (for get) or the destination (for put) memory address. In parallel supercomputers operating on a common problem, puts and gets are typically assembled in batches and issued together. This keeps the independently operating processors in rough synchronization, maximizing performance. The time during which puts and gets occur is termed the put/get window. This window extends both in time (when it occurs) and in memory (over the range of memory addresses carried by the put or get messages). Figure 2 shows a put/get window 30 having a number of distinct messages.
Put/get windows extend the concept of coherence to processors on different processing nodes of the massively parallel supercomputer. Implementations of put/get windows must insure that all messages put to a window during the time it is open are received into the memory of the window before the window is closed. Similarly, a get on the memory of the window is only allowed during the time the window is open. Therefore, put/get windows are simply a mechanism for a node to synchronize with remote processors operating on its memory.
The management of a put/get window is currently accomplished by either buffering the put/get messages or by using explicit synchronization messages. Buffering the messages consumes memory, which is always in limited supply. Explicit synchronization for each window suffers from the long latency of round-trip messages between all the nodes accessing the window. Therefore, on large-scale machines such as the one described in copending patent application no.
(attorney Docket 15275), these approaches do not scale well because of limited memory for buffering, and because the number of nodes accessing any particular window often scales along with the number of processing nodes in the computer.
A long-standing problem in the field of computer design, is how to keep these LI caches coherent. Typical solutions employ techniques known as "snooping" the memory bus of the other processor, which can be slow and reduce the performance of each processor. Alternatively, the processor that contains an old copy in LI of the data in the common memory, can request a new copy, or mark the old copy obsolete, but this requires knowledge of when the copy became invalid. Sometime this knowledge is incomplete, forcing unnecessary memory operations, further reducing performance. Other computers make use of "interlocks," whereby one processor is granted permission to use certain data while the other processor cannot, but this permission involves interactions between the two processors, which usually requires additional complex circuitry in the semiconductor device, reducing the performance of the two processors. Still other solutions in common practice disable all caching for areas of memory intended to be shared. This practice penalizes all memory accesses to these areas, not just those to the shared data.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved procedure for managing coherence in a parallel processing computer system.
Another object of the present invention is to achieve coherency between the first- level caches of the processors of a multi-processor node without extensive circuitry and with minimal impact on the performance of each processor.
A further object of the invention is to provide a method and apparatus, working in conjunction with software algorithms, to accomplish efficient high speed message- passing communications between processors or a direct memory access (DMA) device, which maintains coherence without significantly reducing performance.
These and other objectives are attained with the method and apparatus of the present invention. In accordance with a first aspect, the invention provides a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing massively parallel supercomputer (such as the one described in copending patent application no. (attorney Docket
15275)) containing two or more non-coherent processing elements (or even a DMA controller) where one processing element is primarily performing calculations, while the other element is performing message passing activities. In such a massively parallel supercomputer, algorithms often proceed as a series of steps, where each step consists of a computation phase followed by a communication phase. In the communication phase, the nodes exchange data produced by the computation phase and required for the next step of the algorithm. Because of the nature of the algorithms, the phases are usually tightly synchronized, so that the communication happens all at once over the entire machine. Therefore, the cost of managing the synchronization of put/get windows can be amortized over a large number of nodes at the start and end of each communication phase. Briefly, a global operation can be used to open many put get windows at the start of a communication phase, and a second global operation can be used to close the windows at the end of the communication phase.
Because the I/O Processor cannot actually send or receive the messages until after cache coherence has been guaranteed, the invention provides a mechanism to ensure that the data being "put" (sent) is not in the cache of either processor, and that the data being "gotten" (received) is also not in the cache of either processor. By coordinating these activities upon opening and closing the "Put/Get Window", the invention reduces the total amount of work required to achieve coherence and allow that work to be amortized over a large number of individual messages. Also, since both processing elements within a node must perform this work, the invention enables this to happen concurrently. Further, when required, these activities can be coordinated over a large number of independent nodes in the massively parallel machine by employing the Global Barrier Network described in copending patent application no. (attorney Docket 15275).
In accordance with a second aspect, the invention provides a hardware apparatus that assists the above-described cache coherence software algorithm, and limits the total time (or latency) required to achieve cache coherence over the Put/Get Window. This apparatus is a simple extension to the hardware address decoder that creates, in the physical memory address space of the node, an area of memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements. This further speeds the coherence activities because it allows garbage data (which the processor will never use) to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance. The performance is faster because this garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
The performance is also faster because only modified data is written to memory from cache, while clean data is simply instantly discarded. Further, for the case where the total size of the "Put/Get Window" exceeds, perhaps greatly, the size of the processor's cache, cleaning the cache in this manner provides an upper bound on the total amount of work that is required to ensure that no data from the communication area remains in the cache. It may be noted that, independent of the above-described software algorithms, this hardware device is useful for computer systems in general which employ a Least Recently Used cache replacement policy.
Also, two specific software instructions may be used in the preferred implementation of the invention. One instruction, termed "data cache block flush and invalidate", may be used to write data from the memory area of the first processor into the shared memory area, while at the same time, preventing the first processor from using data the data written in its memory area. A second software instruction, termed "data cache block zero", may be used to write data from the memory area of the first processor into the shared memory. By using these, or similar software instructions, the method and apparatus of the invention, working in conjunction with software algorithms, achieve high speed message passing communications between nodes, while maintaining coherence without significantly reducing performance.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a two processor node embodying this invention.
Figure 2 illustrates a put/get window that may be used in the practice of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention relates to a method and apparatus for managing coherence of a multi-processor computer system. Figure 1 illustrates a node 10 that may embody this invention. Each of the processors 12, 14 of node 10 has a respective cache memory area 16, 20, and the two processors share a third memory area 22. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache memory coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activities required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of physical memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
As indicated above, this invention utilizes a principal referred to as "put/get" data transfer. As parallel multi-computers are scaled to increasing numbers of nodes, typical application messaging traffic involves an increasing number of messages, where each such message contains a piece of work performed by other nodes in the multi -computer. Generally, one node scatters locally produced work items to numerous other nodes (a "put"), while assembling numerous remotely produced work items into its local memory (a "get"). Overall performance for these multi- computers is often gated by the message passing performance of the system.
For such data transfers, a particularly efficient message-passing interface, described in the literature (see for example http://www.mpi-forum.org/docs/docs.html, under MPI-2), is known as One-Sided Communication. One-Sided Communication uses a "put/get" message-passing paradigm, where messages carry the source (for "get") or destination (for "put") memory address. In parallel supercomputers operating on a common problem, typically puts and gets are assembled in batches and issued simultaneously. This keeps independently operating processors in rough synchronization, allowing good performance on a common problem. This time during which puts and gets occur is termed the put/get window. This window extends both in time (when it occurs) and in memory (over which range of memory addresses does the data in the put or get reside). Figure 2 shows a put/get window 30 having a number of distinct messages. In such a massively parallel supercomputer, algorithms often proceed as a series of steps, where each step consists of a computation phase followed by a communication phase. In the communication phase, the nodes exchange data produced by the computation phase and required for the next step of the algorithm. Because of the nature of the algorithms, the phases are usually tightly synchronized, sot that the communication happens all at once over the entire machine. Therefore, the cost of managing the synchronization of put/get windows can be amortized over a large number of nodes at the start and end of each communication phase. Briefly, a global operation can be used to open many put/get windows at the start of a communication.
The present invention utilizes this put/get window to provide a simple means to manage memory coherence. In accordance with a first aspect, a software algorithm is provided that simplifies and significantly speeds the management of cache coherence in a message passing massively parallel supercomputer (such as the one described in copending patent application no. (attorney Docket
15275)) containing two or more non-coherent processing elements (or even a DMA controller) where one processing element is primarily performing calculations, while the other element is performing message passing activities. Briefly, this algorithm uses the opening and closing of "Put/Get Windows" to coordinate the activities required to achieve memory coherence.
Because the messages cannot actually be sent or received until after cache coherence has been guaranteed, this invention provides a mechanism to ensure that the data being "put" (sent) is not in the cache of either processor, and that the data being "gotten" (received) is also not in the cache of either processor. By coordinating these activities upon opening and closing the "Put/Get Window", this invention reduces the total amount of work required to achieve coherence and allow that work to be amortized over a large number of individual messages. Also, since both processing elements within a node must perform this work, this invention enables this to happen concurrently. Further, when required, these activities can be coordinated over a large number of independent nodes in the massively parallel machine by employing the Global Barrier Network described in copending patent application no. (attorney Docket 1527).
This algorithm is assisted by the hardware, described below, but even in the absence of the apparatus benefits message-passing computers in general. Without the apparatus, a special reserved area of physical memory, equal in size to the processor's cache may be utilized, albeit at reduced performance by loading from this physical area into cache by issuing a DCBT (Data Cache Block Touch) instruction for each cache line of the reserved physical area.
In accordance with a second aspect of the invention, a novel hardware apparatus is provided that assists the above-described cache coherence algorithm, and limits the total time (or latency) required to achieve cache coherence over the Put/Get Window. This apparatus is a simple extension to the hardware address decoder that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements. This further speeds the coherence activities because it allows garbage data (which the processor will never use) to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance. The performance is faster because this garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
The performance is also faster because only actually modified data is written to memory from cache, while clean data is simply instantly discarded. Further, for the case where the total size of the "Put/Get Window" exceeds, perhaps greatly, the size of the processor's cache, cleaning the cache in this manner provides an upper bound on the total amount of work that is required to ensure that no data from the communication area remains in the cache. For example, assuming a fully associative cache, if the communication area is 16 Megabytes (common occurrence), traditional cache flush techniques would require (16MB / 32B per cache line equals) 524,288 DCBF instructions, while the algorithm described here would require at most 1,024 DCBT instructions if the processor's cache was 32 Kilobytes in size with 32 byte cache lines. It may be noted that, independent of the above-described software algorithm, this hardware device is useful for computer systems in general which employ a Least Recently Used cache replacement policy.
Two specific software embodiments are described below. The first embodiment may be preferred if the size of the message being received is smaller than the size of LI, while the second embodiment may be preferred if the size of the message received is larger than LI .
First embodiment: If the size of the message being received is smaller than the size ofLl.
In this case, the invention makes use of a software instruction termed "data cache block flush and invalidate" (DCBF), whereby a contiguous range of memory is written from LI back to the common memory if it has been modified in LI . DCBF is a PowerPC BookE instruction; similar instructions exist for other processors. At the same time, the data in the cache is marked as invalid, and cannot be used without reloading contents of the common memory. A DCBF is issued for every line in the address window.
More specifically, when the window is opened for puts or gets, software, (in the communication library) instructs the receiving processor (the Compute Processor in our dual processor node) to flush the contents of LI in the address window, as described above. This simple operation insures that the data in common memory are the same as the data in the compute processor's cache, and further, because of the invalidate, allows an opportunity for the I/O processor to change the contents of the common memory, because the entire contents of LI is replaced quickly from the reserved area. The software then instructs the I/O processor to proceed until all expected messages arrive. The software then allows the computer processor to continue to process instructions, and closes the put/get window using a global synchronization operation such as the global barrier described in copending application copending application D#15272 Global Interrupt and Barrier Networks. Second embodiment: If the size of the message received is larger than the size of LI. In this case, the invention makes use of an instruction termed "data cache block zero" (DCBZ), on a reserved contiguous physical address range equal in size to LI . DCBZ creates a new cache line with contents of zero. If a new cache line is not available, then another cache line in LI (for example, the least recently used line), has its data written back to the common memory, and is then zero'ed with the address given by the DCBZ instruction. DCBZ is a PowerPC BookE instruction; similar instructions exist for other processors. The software executes DCBZ to each line of the reserved area consecutively, where a line of the reserved area is equal in size to a cache line and like-aligned. This causes all lines in the LI to be flushed, i.e., all modified lines are written back to common memory, because the entire contents of LI is replaced quickly from the reserved area. The software then allows the compute processor to continue to process instructions, and closes the put/get window using a global synchronization operation such as the global barrier described in copending application copending application D#l 5272 Global Interrupt and Barrier Networks.
It may be notes that the reserved physical space need not exist in physical memory, only that accesses to the space must not cause access violations. All writes to this reserved memory space must be acknowledged by the memory controller. All reads to this reserved space must immediately return an arbitrary (i.e. "garbage") value to the requesting processor's LI . Note further that such an apparatus also provides the most efficient means for an un-privileged (a.k.a. user-space) program to flush and invalidate the entire contents of the LI cache.
It may also be noted that if DCBF instructions are slower than DCBZ, then the operating system may use the DCBZ instruction for messages smaller then LI and vice-versa.
Using this invention, the I/O Processor need not flush its cache at all if the communication memory space is marked write-through to its LI cache. The making of the above-mentioned global "and" in a short interval of time, which allows the put/get window to be made temporarily narrow, is discussed in detail in related patent application no. (Attorney Docket: 15258 ).
While it is apparent that the invention herein disclosed is well calculated to fulfill the objects previously stated, it will be appreciated that numerous modifications and embodiments may be devised by those skilled in the art, and it is intended that the appended claims cover all such modifications and embodiments as fall within the true spirit and scope of the present invention.

Claims

WHAT IS CLAIMED IS:
1. A method of simplifying and speeding the management of cache coherence in a message passing parallel supercomputer including two or more non-coherent processor elements, where one processor element is primarily performing calculations, while the other processor element is performing message passing activities, the method comprising the steps:
opening and closing a put/get window;
performing activities to achieve cache coherence; and
using said opening and closing of the put/get window to coordinate the activities to achieve cache coherence.
2. A method according to Claim 1, wherein the method is implemented by a software algorithm.
3. A method according to Claim 1, wherein said using step includes the step of ensuring that data being sent is not in the cache of either processor, and that the data being received is also not in the cache of either processor.
4. A method according to Claim 3, wherein the ensuring step includes the step of loading data into cache by issuing a software command.
5. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for simplifying and speeding the management of cache coherence in a message passing parallel supercomputer including two or more non-coherent processor elements, where one processor element is primarily performing calculations, while the other processor element is performing message passing activities, the method steps comprising:
opening and closing a put/get window; performing activities to achieve cache coherence; and
using said opening and closing of the put/get window to coordinate the activities to achieve cache coherence.
6. A program storage device according to Claim 5, wherein said using step includes the step of ensuring that data being sent is not in the cache of either processor, and that the data being received is also not in the cache of either processor.
7. A program storage device according to Claim 6, wherein the ensuring step includes the step of loading data into cache by issuing a software command.
8. A system to simplify and speed the management of cache coherence in a message passing parallel supercomputer including two or more non-coherent processor elements, where one processor element is primarily performing calculations, while the other processor element is performing message passing activities, the system comprising:
means for opening and closing a put/get window;
means for performing activities to achieve cache coherence; and
means for using said opening and closing of the put/get window to coordinate the activities to achieve cache coherence.
9. A system according to Claim 8, wherein said using means includes means for ensuring that data being sent is not in the cache of either processor, and that the data being received is also not in the cache of either processor.
10. A system according to Claim 9, wherein the ensuring means includes means for loading data into cache by issuing a software command.
1 1. Hardware apparatus to assist achieving cache coherence in a message passing parallel computer including two or more non-coherent processing elements, where one processing element is principally performing calculations, while the second processing element is performing message passing activities, the hardware apparatus comprising:
a memory controller to create, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
12. Hardware apparatus according to Claim 11, wherein the memory controller allows garbage data, which the processor will never use, to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance.
13. Hardware apparatus according to Claim 12, wherein the garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
14. Hardware apparatus according to Claim 13, wherein only actually modified data is written to memory from cache, while clean data is simply instantly discarded.
15. Hardware apparatus according to Claim 14, wherein, when the total size of the put/get window exceeds the size of the processor's cache, cleaning the cache in this manner provides an upper bound on the total amount of work that is required to ensure that no data from the communication area remains in the cache.
16. A method of operating computer hardware apparatus to assist achieving cache coherence in a message passing parallel computer including two or more non- coherent processing elements, where one processing element is principally performing calculations, while the second processing element is performing message passing activities, the method comprising the steps: using a memory controller to create, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
17. A method according to Claim 16, wherein the memory controller allows garbage data, which the processor will never use, to be pulled into the processor's cache, thereby evicting just the modified data and displacing unmodified data with optimal performance.
18. A method according to Claim 17, wherein the garbage data does not actually need to be fetched from memory, rather, the memory controller need only instantly reply.
19. A method according to Claim 18, wherein only actually modified data is written to memory from cache, while clean data is simply instantly discarded.
20. A method according to Claim 19, wherein, when the total size of the put/get window exceeds the size of the processor's cache, cleaning the cache in this manner provides an upper bound on the total amount of work that is required to ensure that no data from the communication area remains in the cache.
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AT02713681T ATE437402T1 (en) 2001-02-24 2002-02-25 COHERENCE MANAGEMENT VIA PUT/GET WINDOWS
KR1020037010817A KR100615411B1 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
DE60233055T DE60233055D1 (en) 2001-02-24 2002-02-25 COHERENCE MANAGEMENT VIA PUT / GET WINDOW
CNB028054318A CN1286016C (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
PCT/US2002/005587 WO2002069238A2 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
AU2002245518A AU2002245518A1 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
IL15751702A IL157517A0 (en) 2001-02-24 2002-02-25 Managing colerence via put/get windows
US10/468,995 US7870343B2 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
CA002437663A CA2437663A1 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
JP2002568284A JP3954969B2 (en) 2001-02-24 2002-02-25 Coherence management via put / get windows
EP02713681A EP1410216B1 (en) 2001-02-24 2002-02-25 Managing coherence via put/get windows
US12/543,890 US8122197B2 (en) 2001-02-24 2009-08-19 Managing coherence via put/get windows
US12/953,770 US8161248B2 (en) 2001-02-24 2010-11-24 Simplifying and speeding the management of intra-node cache coherence

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US8161248B2 (en) 2012-04-17
CN1493027A (en) 2004-04-28
US7870343B2 (en) 2011-01-11
DE60233055D1 (en) 2009-09-03

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