WO2002071448A2 - Single transistor ferroelectric memory cell - Google Patents
Single transistor ferroelectric memory cell Download PDFInfo
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- WO2002071448A2 WO2002071448A2 PCT/US2002/006421 US0206421W WO02071448A2 WO 2002071448 A2 WO2002071448 A2 WO 2002071448A2 US 0206421 W US0206421 W US 0206421W WO 02071448 A2 WO02071448 A2 WO 02071448A2
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- ferroelectric
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- ferroelectric layer
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
Definitions
- the present invention relates, in general, to the field of nonvolatile memory devices. More particularly, the present invention relates to a nonvolatile memory device utilizing a single transistor as the only element in the memory cell and a method for the formation of such an element incorporating a ferroelectric material as the gate dielectric thin film formed at a relatively high temperature .
- Nonvolatile ferroelectric random access memory (“FeRAM”) devices represent an emerging, multibillion- dollar market.
- the most advanced FeRAMs utilize a 1- transistor/1 capacitor (“1T1C”) cell technology and a destructive read out (“DRO”) scheme.
- These devices compete with electrically erasable programmable read only memory (“EEPROMs”), battery backed static random access memory (“RAM”; “BBSRAMs”), and Flash nonvolatile memory devices.
- EEPROMs electrically erasable programmable read only memory
- RAM battery backed static random access memory
- Flash nonvolatile memory devices Flash nonvolatile memory devices.
- FeRAM is a type of semiconductor memory, constructed similarly to a dynamic random access memory (“DRAM") device, but which stores bits of data without the need for a continuous power requirement (nonvolatile characteristic) .
- DRAM dynamic random access memory
- FeRAMs have gained recent interest because of the possibility that they could become the ideal memory of the future, also replacing standard mass-produced DRAM.
- Ferroelectric materials exhibit ferroelectric behavior below a critical temperature, known as the Curie temperature. The Curie temperatures of many ferroelectric materials are above
- FeRAMs operate using an array of memory cells, which contain capacitors, built of a special dielectric material (a ferroelectric) sandwiched between two conducting material (electrode) layers.
- the special ferroelectric material is comprised of a lattice of ions, in which one of the ions in each unit cell has two stable states on either side of the center of the unit cell along an elongated axis as shown in Figs 1A and IB.
- the charge displacement within a ferroelectric capacitor is often displayed as a hysteresis curve, where the polarization (or polarization charge) of the ferroelectric layer is plotted against the applied electric field (or applied voltage) , as shown in Fig. 1C.
- Fig. ID shows a schematic of a conventional 1T1C memory cell.
- FeRAMs offer an advantage over DRAMs because ferroelectric polarization can be retained in either state, +Q 0 or -Q 0 , for a very long time (retention) without continuously applied power
- non-volatility Unlike other nonvolatile memory elements, ferroelectric capacitors can be switched from state to state many times (currently >10 10 cycles) without wear-out (fatigue) . Also, because the ferroelectric capacitors operate at a relatively low voltage, there is no need for high voltages provided by charge pumps to program (or "write") the memory as required for certain nonvolatile memories (e.g., EEPROM and Flash) . These low programming voltages ultimately allow ferroelectric memory cells to scale to smaller dimensions than Flash memory and improve radiation hardness.
- nonvolatile memory e.g., EEPROM and Flash
- CMOS complementary metal oxide semiconductor
- ferroelectric materials are very sensitive to moisture, which contamination can be formed when hydrogen is released.
- planarization techniques are commonly used. Most processes require interconnect, metalization to be added before the ferroelectric materials are deposited and activated. This interconnect metalization will generally not withstand the high temperatures of ferroelectric film activation. All of these problems have slowed the development of dense FeRAMs and have clouded the future for an ideal memory.
- a memory cell, device and method for producing the same which advantageously includes a memory cell comprising a single transistor.
- This transistor is formed, for example, utilizing a rare earth manganite as the thin film ferroelectric material that forms part of the gate dielectric of the ferroelectric transistor.
- This ferroelectric gate material may be deposited directly on silicon instead of a metallic or conductive oxide bottom electrode as in prior art ferroelectric devices.
- the ferroelectric material has to be inserted relatively early in the CMOS process. It has, therefore, to be able to withstand higher temperatures, most likely up to and on the order of 950 °C, (e.g. the activation temperature for the implanted source and drain junctions) .
- ferroelectric gate material in accordance with the technique of the present invention are quite different from the ones encountered in a conventional 1T1C cell. In addition to the high temperature requirements, it should also have a relatively low dielectric constant, preferably on the order of less than 20. The reason for this is that any ferroelectric material deposited on silicon forms an interfacial layer with a rather low dielectric constant, most likely around 3.9, the value for Si0 2 . A voltage applied to the gate of the transistor is, therefore, divided between the ferroelectric material and the interfacial layer. If the capacitance of the interfacial layer is much smaller than the capacitance of the ferroelectric layer, most of the voltage will drop over the interfacial layer and is not available for switching the ferroelectric material.
- the ferroelectric material and technique of the present invention exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of Si0 2 , which makes it particularly suitable for a IT cell.
- the ferroelectric material of the present invention is also substantially different from known ferroelectric materials such as lead zirconate titanate (“PZT”) and strontium bismuth tantalate (“SBT”), which are the preferred ferroelectric materials in current use.
- a device in accordance with a preferred embodiment of the present invention may include a substrate such as silicon, a thin film of a rare earth manganite (or "manganate” ; the terms may be used in an equivalent sense herein since a broad range of compositions is contemplated [i.e.
- Source and drain regions may be formed either before or after the ferroelectric layer deposition.
- the device is provided with contacts to the source and drain regions and to the gate electrode. Standard metalization (e.g. aluminum, or other conductive materials) is used to connect these contacts to other elements in an integrated circuit device, such as a CMOS circuit, and to external circuit elements.
- the rare earth manganites used in a representative implementation of the present invention have been demonstrated to possess the desired properties for successful operation of a IT memory cell. Further, they appear to have typical dielectric permittivities of less than 20, they generally form a stable interfacial layer with a relatively high dielectric constant of -30, they exhibit high transition temperatures (Curie temperature) of typically > 600 °C and they have inherently low mobile charges (e.g. oxygen vacancies) . In order for IT devices to exhibit good retention, mobile ionic charges in the ferroelectric film have to be minimized. Rare earth manganates have low oxygen vacancy concentration, the most significant of the ionic mobile charges. Still further, the ferroelectric polarization is in the ideal range of substantially 0.1 to 2 ⁇ C/cm 2 .
- Rare earth manganites are high temperature materials which means that they are ideal for forming ferroelectric transistors which have to withstand a considerable thermal budget.
- Most rare earth manganites e.g. YMn0 3 and CeMn0 3
- a high temperature treatment anneal
- the processing window is approximately 100 to 200 °C, which means that they are able to withstand heat treatments of 950 to 1050 °C , well above the thermal budget of a modern CMOS process.
- the ferroelectric materials utilized in the implementation of the present invention may be deposited, preferably, by metallorganic chemical vapor deposition ("MOCVD") techniques, although other methods such as plasma enhanced chemical vapor deposition (“PECVD”), metal -organic decomposition (“MOD”) or other techniques could be used.
- MOCVD metallorganic chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- MOD metal -organic decomposition
- the MOCVD process may be preferred as it tends to minimize ionic contamination (e.g. Na+) which is detrimental to data retention in a final IT cell device.
- the MOCVD process may preferably employ a liquid source delivery and flash evaporation method, since the precursors preferably used typically have low vapor pressure, making other methods such as vapor delivery with bubblers more difficult.
- These materials are solid powders and can be brought into solution with tetrahydrofuron (“THF”) as the solvent with tetraglyme added to prevent any early evaporation problems .
- THF tetrahydrofuron
- the exemplary MOCVD process disclosed herein produces rare earth manganite thin films with low mobile ion contamination, excellent uniformity, good step coverage and excellent compositional control . Importantly, it produces a well controlled interfacial layer of Si x O y A z that is enhanced by the subsequent anneal steps in 0 2 .
- Figs. 1A and IB illustrate the crystal lattice of a ferroelectric material
- Fig. 1C is a representative hysteresis loop for a conventional ferroelectric material
- Fig. ID is a representative schematic diagram of a prior art 1T1C memory cell
- Fig. 2A is a cross-sectional view of a representative embodiment of the present invention.
- Fig. 2B depicts a corresponding schematic diagram of an embodiment of the present invention
- Fig. 2C illustrates a representative hysteresis loop for an embodiment of the present invention
- Fig. 3A depicts a simplified cross-section through the gate area of a ferroelectric transistor in accordance with the present invention
- Fig. 3B illustrates the voltage drops over the ferroelectric thin film and the interfacial layer as shown in schematic form
- Fig. 4 illustrates a ferroelectric transistor in accordance with the disclosure of the present invention as integrated, for example, into a standard CMOS manufacturing process.
- the IT memory cell 10 comprises a substrate 20 of a suitable material such as silicon.
- Substrate 20 may be the starting material for a complex integrated circuit and what is shown is only a representative memory cell 10 itself.
- the memory cell 10 may be the building block of a larger memory array that, in turn, is interconnected with peripheral circuitry such as decoders, sense ' amplifiers and input/output circuitry (not shown) .
- a ferroelectric thin film layer 30 is, in the embodiment illustrated, deposited directly onto substrate 20.
- An interfacial layer 31 is then formed between the substrate 20 and ferroelectric layer 30 either automatically during deposition of ferroelectric layer 30 or deliberately as a separate processing step prior to deposition of the ferroelectric layer 30.
- the ferroelectric layer 30 may be deposited as hereinafter described and the interfacial layer 31 is then a mixture of the oxides of silicon and the rare earth element.
- the ferroelectric layer 30 may be patterned using standard photolithography and etch techniques.
- Source and drain regions 40 and 41 may also be formed adjacent to the patterned ferroelectric layer 30 using standard techniques used in semiconductor processing. In practice, these regions 40 and 41 can either be formed before or after deposition of the ferroelectric layer 30.
- the most common technique used for source and drain formation is by ion implantation of, for example, boron for p+ regions (p- channel transistors) , or phosphorous or arsenic for n+ regions (n-channel transistors) . The use of any of these or other known techniques is within the contemplation of the present invention.
- a conductive gate material 50 is then deposited using standard techniques (e.g.
- the conductive gate material may be composed of platinum, gold or any other noble metal, iridium, rhodium, ruthenium or oxides thereof, doped polycrystalline silicon (e.g. an n+ or p+ doping with, for example, B for p+ or P or As for n+) , a metal suicide (such as platinum suicide) or other known materials.
- doping of polycrystalline silicon can occur during deposition of the polycrystalline silicon layer (in situ) or can be performed as a separate processing step after the polycrystalline silicon is deposited.
- CMOS complementary metal-oxide-semiconductor
- An insulating layer 60 e.g. Si0 2
- contact windows 70, 71 are etched to the source and drain regions 40, 41 and also to the gate electrode, respectively, and connections 80 may be provided by standard metalization techniques (e.g. aluminum) .
- the device may be passivated with a suitable passivation layer 90, e.g. polyimide, plasma oxide, plasma nitride or the like.
- the memory cell 10 of the present invention operates- quite differently from a prior art 1T1C cell. Instead of using the switched (or non-switched) charge as a signal (as in the 1T1C DRO cell previously described) the magnitude of the drain current I d of the ferroelectric transistor is instead used to distinguish between the two logic states.
- the threshold voltage of the device is increased (to e.g., 1.5 volts) and the drain current is "low” (at a drain voltage V d ⁇ 0.3 volt, less than the threshold voltage), representing, for example, a logic "0".
- the threshold voltage of the device is decreased (to e.g., -2.5 volts) and the drain current is "high", representing, for example, a logic "1".
- the cell is selected and a positive or negative voltage is applied to the gate of the selected transistor to write either a logic "1" (polarization up) or a logic “0" (polarization down) .
- a small drain voltage is applied to the selected cell.
- the sense amplifier determines if the drain current is "high” or “low”, representing a logic "1” or “0” as shown particularly with respect to Fig. 2C.
- a "read” operation does not change the polarization state of the device and, therefore, does not destroy the information providing a nondestructive read-out (“NDRO") capability.
- the memory cell 10 does, therefore, not fatigue under a "read” operation (and only fatigues under a “write” operation) thereby providing a major advantage over conventional DRO memories.
- a NDRO technique is ultimately faster since no "restore” operation is needed, thereby shortening the "write” cycle.
- NDRO operation also is potentially more reliable, especially in adverse environments (e.g., radiation) as might be encountered, for example, in military and space applications, as there is never an instance where the memory state is unidentified such that an upsetting event (e.g., single event upset "SEU”) could inadvertently alter the state of the memory.
- adverse environments e.g., radiation
- SEU single event upset
- the memory cell 10 of the present invention also has a much smaller footprint than any known ferroelectric storage cell and comprises what is potentially the smallest possible ferroelectric memory cell with a density similar to that of a Flash memory cell, the densest of any competing nonvolatile semiconductor memory technologies.
- the challenges of building such a IT ferroelectric memory cell 10 is that the ferroelectric material has generally to be deposited directly on silicon instead of a metallic bottom electrode as in the prior art devices. This means that requirements for the ferroelectric material are different.
- the switched polarization (P r ) should be in a range of approximately 0.1 to 1 ⁇ C/cm 2 and not as high as possible as in the prior art devices.
- the dielectric permittivity should be as low as possible, ideally less than 20, and the leakage current over the operating voltage range (e.g. +- 5 Volt) should also be as low as possible. This applies both to electronic and ionic charge motion in the ferroelectric material, but most importantly for the slow moving ionic charge.
- the polarization charge cannot be compensated. Any ionic charge that would slowly drift through the films and accumulate at the ferroelectric interfaces to the electrodes could compensate the polarization charge over time and destroy the information.
- ferroelectric thin film is part of the gate of a transistor, it has to be deposited early in the fabrication process during the formation of the transistors. That means that the material has to be able to withstand a considerable thermal budget without unacceptable device degradation.
- ferroelectric materials are not optimum for this application since they degrade at temperatures above about 800 °C for extended times (e.g. hours) .
- .their transition temperatures are high relative to the maximum operating temperature of a circuit, in the range of approximately 500 to 700 °C providing a large margin for the high temperature limit of operating the device.
- This property is also linked to the high ferroelectric phase formation temperature that allows insertion of the ferroelectric film into a manufacturing process early in the process flow, for example, prior to source/drain formation.
- the material can withstand the processing temperatures of > 850 °C that is required to, for example, activate the junctions.
- Rare earth manganites also exhibit low dielectric permittivties , in the range from approximately 10 to 50, due to the closely packed crystal lattice in a hexagonal structure.
- the interfacial layer 31 has relatively high dielectric permittivities, in the range of substantially 10 to 30, because it is a mixture of the rare earth oxide A X 0 Z and the silicon oxide Si v O w .
- the interfacial layer 31 is, therefore, most likely non- stoichiometric with x,y,v, and w in the range of 0.1 to 10. In a preferred embodiment, the range for x,y,v and w is approximately 1 to 3.
- Ce 2 0 3 , Y0 3 and Pr 2 0 3/ exemplary preferred embodiments of the present invention have relative dielectric permittivties of about 25, 20 and 30, respectively.
- the interfacial layer 31 may be formed either automatically during CVD deposition of the rare earth manganite, enhanced by the subsequent anneals in 0 2 , or may be deposited or otherwise formed deliberately, preferably by MOCVD in the same processing chamber and prior to the ferroelectric deposition. Deliberate deposition has the advantage that the dielectric permittivity ratio may be better optimized such that a selected rare earth oxide may be employed for the interfacial layer
- the interfacial layer 31 can also be formed by other means, for example by sputtering, e-beam evaporation or other known techniques.
- the ferroelectric layer is preferably deposited using MOCVD techniques
- other techniques such as MOD, sol-gel, PECVD and the like can be used and fall within the scope of the invention as claimed.
- the preferred embodiment, incorporating the formation of the ferroelectric layer by .MOCVD may be carried out by using a liquid source delivery technique as described, for example, ' in US Patent No. 5,887,117, for: “Flash Evaporator", the disclosure of which is herein specifically incorporated by this reference.
- Flash Evaporator the disclosure of which is herein specifically incorporated by this reference.
- An important element of this method involves the use of a suitable precursor chemistry.
- a preferred embodiment might use Cerium (IV) tris- tetramethylheptanedionate (thd) for Cerium (Ce) , Manganese (III) tris- tetramethylheptanedionate for Manganese (Mn) and tetrahydrofuron (THF) as the solvent .
- Table 1 lists some typically preferred deposition conditions for depositing CeMn0 3 .
- the ferroelectric films may be annealed in 0 2 at temperatures of around 800 to 950 °C in order to form the proper ferroelectric phase.
- This anneal operation also increases the thickness of the interfacial layer, an added advantage, since it improves the quality and reliability of this important oxide layer.
- the relatively high anneal temperature which would be found to be detrimental in prior art ferroelectric memory devices, is not a problem as the ferroelectric films may be inserted into the process flow early, for example, prior to source and drain formation.
- Figs. 3A and 3B The combination of a low relative dielectric permittivity ferroelectric material in conjunction with a high relative dielectric permittivity oxide interfacial layer is a significant factor in the efficaciousness of the present invention and will be discussed in greater detail with reference additionally now to Figs. 3A and 3B.
- the former figure shows a simplified cross-section taken through the gate area of a ferroelectric transistor in accordance with the present invention whereas the later figure is a corresponding schematic representation of the two capacitors formed by the ferroelectric layer and the interfacial layer, respectively, connected in series.
- the applied gate voltage V g between gate 50 and substrate 20 is divided between the ferroelectric layer 30 (V f ) and the interfacial layer 31 (V 0 ) according to the formula
- V g V f + V 0 .
- the gate electrode 50 may be formed of a conducting material consistent with CMOS processing.
- noble metals such as Pt are typically used in order to prevent the formation of unwanted oxides at the interfaces .
- oxide interfacial layers are not critical due to the relatively low dielectric permittivity of the rare earth manganites.
- the thickness ratio of the ferroelectric layer to that of the interfacial layer can be as small as approximately 3:1, e.g. 60 nm thickness of a ferroelectric layer to 20 nm for the interfacial layer.
- a much wider range of gate electrode materials can then be used including, for example, noble metals, conductive oxide and, most importantly, doped polycrystalline silicon or metal suicides. These latter materials are particularly attractive since they are inexpensive and compatible with current CMOS processing techniques.
- a ferroelectric transistor in accordance with the present invention can, therefore, be integrated into a standard CMOS manufacturing process to result in a structure shown, for example, in Fig. 4.
- the ferroelectric transistor (or memory cell) 10 can be formed prior to or after the formation of the standard CMOS transistors 95. If the ferroelectric transistor 10 is formed prior to the standard CMOS transistors 95, it may be preferably encapsulated by a thin layer of a barrier material 96 that prevents any possible out diffusion of the materials composing the rare earth manganite films which might possibly contaminate the remainder of the CMOS structure. This barrier material can be silicon nitride, aluminum oxide or other suitable materials. If the ferroelectric transistor 10 is formed after the standard CMOS transistors 95, the standard CMOS transistors may be encapsulated with a barrier material 96 to avoid any contamination from the any possible out diffusion of the materials composing the rare earth manganite films.
Abstract
Description
Claims
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- 2002-03-01 WO PCT/US2002/006421 patent/WO2002071448A2/en active Search and Examination
- 2002-03-01 AU AU2002306638A patent/AU2002306638A1/en not_active Abandoned
- 2002-03-01 US US10/087,361 patent/US6674110B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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WO2002071477A1 (en) | 2002-09-12 |
US20020153542A1 (en) | 2002-10-24 |
US20040026725A1 (en) | 2004-02-12 |
US6674110B2 (en) | 2004-01-06 |
US20020164850A1 (en) | 2002-11-07 |
US6908772B2 (en) | 2005-06-21 |
WO2002071448A3 (en) | 2004-01-29 |
AU2002306638A1 (en) | 2002-09-19 |
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