WO2002073881A3 - Atm linked list buffer system - Google Patents

Atm linked list buffer system Download PDF

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Publication number
WO2002073881A3
WO2002073881A3 PCT/IB2002/000719 IB0200719W WO02073881A3 WO 2002073881 A3 WO2002073881 A3 WO 2002073881A3 IB 0200719 W IB0200719 W IB 0200719W WO 02073881 A3 WO02073881 A3 WO 02073881A3
Authority
WO
WIPO (PCT)
Prior art keywords
buffer
linked
monitor
circuitry
linked list
Prior art date
Application number
PCT/IB2002/000719
Other languages
French (fr)
Other versions
WO2002073881A2 (en
Inventor
Koby Reshef
Yochai Parchak
Amir Cohen
David Shyken
Original Assignee
Adc Telecomm Israel Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Adc Telecomm Israel Ltd filed Critical Adc Telecomm Israel Ltd
Priority to IL15762702A priority Critical patent/IL157627A0/en
Priority to AU2002237471A priority patent/AU2002237471A1/en
Priority to EP02703793A priority patent/EP1368931A2/en
Publication of WO2002073881A2 publication Critical patent/WO2002073881A2/en
Publication of WO2002073881A3 publication Critical patent/WO2002073881A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/29—Flow control; Congestion control using a combination of thresholds
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Abstract

A linked list buffer circuit can be configured to store different linked lists. The buffer includes insert logic and an insert state machine to add ATM cells to the linked lists in the buffer. Extract logic and an extract state machine allow for the removal of ATM cells from the linked lists in the buffer. Because, ATM cells can have different levels of priority, programmable monitor circuitry is provided to monitor the linked lists in the buffer. The monitor circuitry keeps track of buffer and list capacity, and also keeps track of cell loss priority and delay priority cells of the buffer and the linked lists. This information is used to drop received cells if necessary. The linked list monitor circuitry can be configured based upon the linked list configuration of the buffer. The linked list monitor can be configured by changing threshold levels provided to counter/comparator circuitry. Assignments of internal counter circuitry are also programmable based upon the buffer configuration.
PCT/IB2002/000719 2001-03-13 2002-03-12 Atm linked list buffer system WO2002073881A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IL15762702A IL157627A0 (en) 2001-03-13 2002-03-12 Atm linked list buffer system
AU2002237471A AU2002237471A1 (en) 2001-03-13 2002-03-12 Atm linked list buffer system
EP02703793A EP1368931A2 (en) 2001-03-13 2002-03-12 Atm linked list buffer system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/804,929 2001-03-13
US09/804,929 US7215672B2 (en) 2001-03-13 2001-03-13 ATM linked list buffer system

Publications (2)

Publication Number Publication Date
WO2002073881A2 WO2002073881A2 (en) 2002-09-19
WO2002073881A3 true WO2002073881A3 (en) 2003-03-13

Family

ID=25190237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/000719 WO2002073881A2 (en) 2001-03-13 2002-03-12 Atm linked list buffer system

Country Status (5)

Country Link
US (1) US7215672B2 (en)
EP (1) EP1368931A2 (en)
AU (1) AU2002237471A1 (en)
IL (1) IL157627A0 (en)
WO (1) WO2002073881A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3407696B2 (en) 1999-07-13 2003-05-19 日本電気株式会社 ATM exchange and call acceptance processing method
JP3911380B2 (en) * 2000-03-31 2007-05-09 松下電器産業株式会社 Transfer rate control device
AU2001289045A1 (en) * 2000-09-08 2002-03-22 Avaz Networks Hardware function generator support in a dsp
FR2822319B1 (en) * 2001-03-16 2003-05-30 Thomson Csf VARIABLE SIZE INFORMATION FRAME SWITCH FOR ON-BOARD SECURITY NETWORKS
JP3771153B2 (en) * 2001-08-29 2006-04-26 三菱電機株式会社 UTOPIA interface control apparatus and method, and back wire board used in the apparatus
US20030112758A1 (en) * 2001-12-03 2003-06-19 Pang Jon Laurent Methods and systems for managing variable delays in packet transmission
US20030105799A1 (en) * 2001-12-03 2003-06-05 Avaz Networks, Inc. Distributed processing architecture with scalable processing layers
US7359321B1 (en) * 2002-01-17 2008-04-15 Juniper Networks, Inc. Systems and methods for selectively performing explicit congestion notification
CN100484123C (en) * 2003-09-13 2009-04-29 华为技术有限公司 Access multiplex device for digital subscriber line and signal transmission method
CA2593247A1 (en) * 2005-01-10 2006-11-16 Quartics, Inc. Integrated architecture for the unified processing of visual media
US7742506B2 (en) * 2005-05-27 2010-06-22 Agere Systems Inc. Controlling timeslot delay in a digital communication system
US7733894B1 (en) * 2005-12-14 2010-06-08 Juniper Networks, Inc. Dynamic queue management
US7697435B1 (en) * 2007-02-02 2010-04-13 Sprint Communications Company L.P. Dynamic backhaul delay determination
US20090168905A1 (en) * 2007-12-28 2009-07-02 Teradyne, Inc. Decoding of LVDS Protocols
ES2354344B1 (en) * 2009-05-22 2011-10-05 Telefonica, S.A. METHOD AND SYSTEM OF TRANSMISSION AND RECEPTION OF PACKAGES.
JP6273780B2 (en) * 2013-11-06 2018-02-07 富士通株式会社 Transmission apparatus, transmission method, and transmission program
US9940344B2 (en) * 2013-12-18 2018-04-10 Red Hat, Inc. Fractal approach for probabilistic flow cache maintenance

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472408A2 (en) * 1990-08-20 1992-02-26 Kabushiki Kaisha Toshiba ATM communication system
US6021115A (en) * 1996-08-30 2000-02-01 Sgs-Thomson Microelectronics Limited ATM switch flow control
US6151301A (en) * 1995-05-11 2000-11-21 Pmc-Sierra, Inc. ATM architecture and switching element

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0936912A (en) * 1995-07-14 1997-02-07 Fujitsu Ltd Buffer control system
US5893162A (en) * 1997-02-05 1999-04-06 Transwitch Corp. Method and apparatus for allocation and management of shared memory with data in memory stored as multiple linked lists
US20020031132A1 (en) * 2000-05-25 2002-03-14 Mcwilliams Patrick UTOPIA-LVDS bridge

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472408A2 (en) * 1990-08-20 1992-02-26 Kabushiki Kaisha Toshiba ATM communication system
US6151301A (en) * 1995-05-11 2000-11-21 Pmc-Sierra, Inc. ATM architecture and switching element
US6021115A (en) * 1996-08-30 2000-02-01 Sgs-Thomson Microelectronics Limited ATM switch flow control

Also Published As

Publication number Publication date
WO2002073881A2 (en) 2002-09-19
EP1368931A2 (en) 2003-12-10
IL157627A0 (en) 2004-03-28
US20020131421A1 (en) 2002-09-19
AU2002237471A1 (en) 2002-09-24
US7215672B2 (en) 2007-05-08

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