WO2002078082A2 - Electronic structure - Google Patents
Electronic structure Download PDFInfo
- Publication number
- WO2002078082A2 WO2002078082A2 PCT/GB2002/001414 GB0201414W WO02078082A2 WO 2002078082 A2 WO2002078082 A2 WO 2002078082A2 GB 0201414 W GB0201414 W GB 0201414W WO 02078082 A2 WO02078082 A2 WO 02078082A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- damascene
- contact via
- copper
- silicon dioxide
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Definitions
- the present invention relates to a method for fabricating an electronic structure.
- An integrated circuit fabricated on a semiconductor substrate typically requires multiple levels of metal interconnections for electrically interconnecting discrete semiconductor devices on the semiconductor substrate .
- a lower wiring level of damascene tungsten contacts is commonly used to provide local interconnections between the semiconductor devices which exist within and upon the substrate layer.
- it is problematic to generate reliable, low resistance contacts between an upper level of damascene copper wiring and the lower wiring level of damascene tungsten contacts.
- the present invention includes a method for fabricating an electronic structure comprising the steps of:
- the first layer includes a plurality of electrically conduction regions of tungsten or silicon separated by electrically insulating material
- the present invention also provides an electronic structure, comprising: a semiconductor substrate;
- the first layer includes a plurality of electrically conducting regions, wherein the electrically conductive regions each include an electrically conductive material selected from the group consisting of tungsten and silicon, and wherein the electrically conducting regions are separated by insulative material;
- damascene copper interconnect wiring level having a plurality of damascene copper wires within one or more corresponding damascene contact vias wherein each damascene copper wire is in electrically conductive contact with a corresponding conducting region of the electrically conducting regions;
- each etch stop layer does not exist where the damascene contact via exists, and wherein the etch stop layer includes an etch stop insulative material;
- a third insulator region on a third portion of the etch stop layer and disposed between the damascene copper interconnect and the third portion of the etch stop layer, wherein the second insulator region includes the electrically insulative material.
- the present invention also provides a method of cleaning a surface of a volume of material, comprising the steps of:
- the material includes a refractory metal or silicon
- the advantage of the present invention is that it is able to provide reliable, low resistance contacts between an upper level of damascene copper wiring and a lower wiring level of damascene tungsten contacts .
- FIG. 1A depicts a cross-sectional view of an electronic structure having a damascene tungsten wiring level on a silicon substrate, a silicon nitride layer on the damascene tungsten wiring level, and a silicon dioxide layer on the silicon nitride layer;
- FIG. IB depicts a cross-sectional view of an electronic structure having a damascene tungsten wiring level on a silicon substrate similar to FIG. 1, wherein a variety of undesirable manufacturing topographies are shown, including a bump, a recess, a seam, a scratch, and an embedded particle.
- FIG. 2 depicts FIG. IB after the silicon dioxide layer has been polished, to remove or reduce prior level scratches and topography, to a reduced height and cleaned.
- FIG. 3 depicts FIG. 2 after a silicon dioxide cap has been deposited on the silicon dioxide layer.
- FIG. 3A depicts FIG. 3 with a scratch or other topography in one layer that is replicated in a second layer.
- FIG. 4 depicts a FIG. 3 after a resist layer has been deposited on the silicon dioxide cap.
- FIG. 5 depicts FIG. 4 after etching the resist to form contact vias to the silicon nitride layer and after removal of the resist layer.
- FIG. 6 depicts FIG. 5 after deposition and reflow of an anti-reflective coating layer which covers the entire wafer surface including the interiors of the contact vias, and deposition of a photoresist layer on the anti-reflective coating layer, followed by lithographic patterning and opening of the photoresist.
- FIG. 7 depicts FIG. 6 after etching of the anti-reflective coating has been performed, using a process which etches the anti-reflective coating but does not etch the silicon dioxide.
- FIG. 8 depicts FIG. 7 after etching of a top portion of the silicon dioxide between the contact troughs, and etching to round off the corners of the silicon dioxide to promote good liner and copper fill.
- FIG. 9 depicts FIG. 8 after the photoresist layer and the anti-reflective layer have both been stripped away.
- FIG. 10 depicts FIG. 9 after the silicon nitride layer at the bottom of each contact trough is etched.
- FIG. 11 depicts FIG. 10 after deposition of a standard copper diffusion barrier, comprising a film stack composed of layers of tantalum-nitride and tantalum over the entire wafer surface, depositing a copper seed layer, and depositing electroplated copper over the copper seed barrier.
- a standard copper diffusion barrier comprising a film stack composed of layers of tantalum-nitride and tantalum over the entire wafer surface, depositing a copper seed layer, and depositing electroplated copper over the copper seed barrier.
- FIG. 12 depicts FIG. 11 after an upper portion of the copper on the wafer has been removed with a CMP process which does not remove the tantalum nitride and tantalum copper diffusion barrier, and a remaining exposed surface has been planarized.
- FIG. 13 depicts an alternative embodiment of FIG. 12 wherein damascene tungsten interconnects are replaced by semiconductor material and included semiconductor devices.
- FIG. 14A depicts a cross-section view of an alternative embodiment of the present invention showing a multiplicity of dual damascene copper wires and contact vias.
- FIG. 14B depicts a plan view of the structure depicted in FIG. 14A.
- the present embodiment discloses a structure and associated method of fabrication of a high-aspect-ratio dual damascene copper interconnect electrically coupled to a damascene tungsten local wiring level.
- the phrase "damascene tungsten” is used for the sake of clarity, and not to limit the invention.
- the tungsten in the damascene tungsten wiring level may be replaced by any suitable damascene conductor, including, in ter al ia, polysilicon, etc.
- the phrase “damascene copper” is understood to mean that one or more trenches are made in a dielectric layer, one or more levels of refractory metal liners are deposited in the trench(es), the trench(es) is filled with copper and polished flat leaving liner and copper in the trench(es).
- the present invention is described in terms of two contact vias and troughs. This has been done for the sake of clarity, and not to limit the invention. One skilled in the art will recognize that there may be one or more contact vias, and also that one or more troughs may be used.
- the wafer 100 has a substrate 110, which in the preferred embodiment is a silicon substrate, but which may include, in ter alia , a p-type or n-type single crystal silicon, silicon-on-insulator (SOI), quartz, sapphire, gallium arsenide, etc. Numerous devices (not shown) such as gates, transistors, diffusions, capacitors, etc., may be embedded in the substrate 110.
- a substrate 110 which in the preferred embodiment is a silicon substrate, but which may include, in ter alia , a p-type or n-type single crystal silicon, silicon-on-insulator (SOI), quartz, sapphire, gallium arsenide, etc.
- SOI silicon-on-insulator
- Numerous devices such as gates, transistors, diffusions, capacitors, etc., may be embedded in the substrate 110.
- the devices in the substrate 110 are contacted, using standard processing, by damascene tungsten electrically conductive interconnects 120 which are formed in a damascene tungsten local wiring level 90.
- Titanium or titanium nitride lined tungsten or doped polysilicon, among other conductors, are employed as the conductor in wiring level 90.
- tungsten is the preferred embodiment.
- the damascene tungsten wiring level 90 exemplifies a damascene refractory metal local interconnect layer.
- the damascene tungsten interconnects 120 are isolated from one another by an insulative dielectric material 130 such as, in ter alia , borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) .
- a surface 122 of the damascene tungsten local wiring level 90 (i.e., of the damascene tungsten interconnects 120 and the insulative dielectric material 130) is then planarized using known techniques. This resulting flat surface 122 forms the basis for the processing sequence disclosed in the present invention.
- a relatively thin (such as, inter alia, . approximately 50 nm) layer of film 140 is deposited over the layer of damascene tungsten interconnects 120 and insulative dielectric material 130.
- This film 140 which is typically a silicon nitride film, may be deposited using plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) , low pressure chemical vapor deposition (LPCVD) , or other suitable processing technique known in the art.
- PECVD plasma-enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- the film 140 is followed by a relatively thick (such as, approximately 150 tolOOO nm) silicon dioxide layer 150.
- the film 140 and silicon dioxide layer 150 films are preferably deposited using low charging damage processes, preferably using low pressure RF power density silane-oxide based chemistries or high pressure (i.e., approximately 14 Torr) tetraethylorthosilicate (TEOS) chemistry PECVD.
- TEOS tetraethylorthosilicate
- fluorine doped or carbon doped dielectrics could be used to reduce the dielectric constant.
- the film 140 is desirable to act as a reactive ion etching (RIE) stop for subsequent etching, as discussed infra, and also will act as a copper diffusion barrier.
- RIE reactive ion etching
- Film 140 could be any dielectric which acts as a RIE stop during the etching of layer 150, such as, inter alia, silicon dioxide, fluorinated silicon dioxide, phosphosilicate glass, borophosphosilicate glass, CH 3 -doped silicon dioxide, SiC x H y or SiC x H y N z .
- FIG. 2 depicts FIG. 1A after the silicon dioxide layer 150 has been polished to a reduced height and cleaned by any method known in the art.
- a chemical-mechanical polish CMP
- CMP chemical-mechanical polish
- the purpose of this polishing step is to planarize the silicon dioxide layer 150 to remove any topography which may have resulted from the process used to make the damascene tungsten interconnects 120.
- damascene processing is used to make damascene tungsten interconnects, two problems can arise. Referring to FIG.
- the first problem is that the insulative dielectric material 130 may be scratched, and those scratches in the insulative dielectric material 130 can replicate in the next silicon dioxide layer 150.
- the second problem is that the damascene tungsten interconnects 120 . may either protrude above the insulative dielectric material 130 by a small amount, or they may be recessed below the insulative dielectric material 130 surface a small amount. This small amount of topography due to process defects (e.g., scratches, protrusions, or insufficient tungsten fill, recessed damascene tungsten layer, etc. ) of the damascene tungsten interconnects 120 will be smoothed out by the polish processing step.
- the purpose of this silicon dioxide polishing step is to eliminate the aforementioned small topography.
- FIG. IB is shown a version of a cross-sectional view of an electronic structure 109 having a damascene tungsten wiring level 107 on a silicon substrate 108 similar to FIG. 1, and wherein a variety of undesirable manufacturing topographies are shown, including a bump 101, a recess 102, a seam 103, a scratch 104, and an embedded particle 106.
- the CMP step is optimized, and can be avoided if the subsequent copper/tantalum nitride/tantalum CMP steps are modified to overpolish into the insulator layer 150.
- the disadvantage of this approach is that this leads to much more damascene copper wire resistance and capacitance variability.
- the CMP step is followed by a brush-clean processing step, and alternatively, a hydrofluoric (HF) acid etch, which may be, in ter al ia, a 500:1 buffered hydrofluoric (BHF) acid etch.
- HF hydrofluoric
- BHF buffered hydrofluoric
- FIG. 3A illustrates the wafer 100 after an optional post-silicon dioxide CMP PECVD silicon dioxide cap layer 350 deposition is performed.
- the silicon dioxide cap layer 350 may be undoped, or it may contain doping (such as, e.g., fluorine or carbon) to reduce the dielectric constant of the silicon dioxide cap layer 350.material.
- This silicon dioxide cap layer 350 deposition while not required, is beneficial because it reduces electrical shorts in a subsequently deposited copper layer due to any scratches which may have occurred during the CMP of the silicon dioxide layer 150.
- the final thickness of this silicon dioxide cap layer 350 is tuned, such that the heights of subsequently formed contacts and copper layers are optimized. For example, for a 250 nm wide contact and copper layer, one possible set of heights would be 400 nm and 300 nm for the contact and the copper layer, respectively.
- a feature of the silicon dioxide cap layer 350 is that it further reduces surface layer scratch propagation. That is, if there is a scratch 157 in the lower silicon dioxide layer 150, as shown in FIG. 3B, it will be smoothed out by the deposition of the conformal, or near conformal, silicon dioxide cap layer 350.
- FIG. 4 depicts the structure of FIG. 3A after a photoresist layer 440 has been deposited on the silicon dioxide cap layer 350 (see FIG. 3) to pattern contact vias under portions 410 and 420 of the photoresist layer 440 using standard procedures known in the art.
- the silicon dioxide layer " 150 and the silicon dioxide cap layer 350 " of EIG. 3, in composite, has been replaced for simplicity of illustration by a silicon dioxide layer 450.
- the photoresist layer 440 may also use a first anti-reflective coating (ARC) layer 460, which is deposited upon the silicon dioxide layer 450.
- ARC first anti-reflective coating
- an ARC layer improves the ability to resolve small features when the photoresist is exposed.
- FIG. 5 depicts the structure of FIG. 4 after selective etching of the silicon dioxide layer 450 to form two contact via holes 510 which extend through the silicon dioxide layer 450 to the film 140.
- the contact via holes 510 are located underneath the portions 410 and 420 of FIG. 4.
- a selective silicon dioxide RIE chemistry is employed such that the contact via holes 510 extend down to, but not through, the film 140.
- This process stage actually involves a two step reactive ion etch (RIE) .
- RIE reactive ion etch
- the first ARC layer 460 is etched using RIE, or, optionally, using a selective etch chemistry so that the etch is stopped on the silicon dioxide layer 450.
- the silicon dioxide layer 450 is etched, using a selective etch chemistry, as known in the art, which substantially stops on the film 140, with selectivities on the order of 10:1, or better.
- Selectivity is defined as the etch rate of the material you want to etch divided by the etch rate of the material you don't want to etch.
- the photoresist layer 440 is stripped, preferably using an oxygen plasma or downstream plasma drip process. Note that standard wet chemical photoresist strip methods, such as sulfuric acid mixed with hydrogen peroxide, may etch the conductor in 120 through pinholes in the film 140, and therefore should not be used.
- Stripping the photoresist during the second step of this dual damascene process is a critical process because of concerns of rounding the upper corners of the wire trough. If the upper wire trough corners are substantially rounded, the likelihood for electrical shorts between wires increases. This means that the photoresist strip steps, employed either when the wire trough photoresist is stripped before RIE etching the wire troughs because lithographic printing or registration problems (referred to as lithographic rework) or after the trough RIE etch, must be substantially nondirectional during the portion of the photoresist strip - when there is resist left on the wafer.
- the photoresist strip is broken up into two steps, the first step removes the photoresist from blanket surfaces on the wafer and the second step removes photoresist from trenches or other topographic features on the wafer and includes an overstrip portion, during which the photoresist strip process continues to run despite the full removal of the photoresist.
- the first photoresist step if performed in a plasma strip tool, striped photoresist and/or RIE etch residuals mix with the strip chemistry and can add a significant sputter and RIE component to the photoresist strip process.
- the wafer bias increases ion bombardment on the wafer which results in increased corner rounding of the wire troughs.
- This problem can be significantly reduced by performing the first photoresist step either in a non-plasma environment (i.e., solvent strip, downstream plasma, ozone strip, etc.) or by minimizing the wafer RF bias power applied to the wafer.
- the optimal plasma photoresist strip process uses a non-plasma or low RF bias power on the wafer plasma photoresist first step followed by a high RF bias power on the wafer plasma strip for the second step.
- the high RF bias power second step is needed to remove photoresist, ARC, or RIE etch residuals from trenches or other topographic features on the wafer.
- an optional step may be performed " which consists of an etch using, in ter alia , a 100:1 dilute HF acid etch to remove approximately 5 to 10 nm of silicon dioxide. This step removes etch residuals of the prior second step etch.
- aqueous HF acid solution deionized water, or any solvent known in the art as useful for cleaning etch residuals could be used.
- FIG. 6 depicts the structure of FIG. 5- after deposition, using techniques known in the art, of a second anti-reflective coating layer 620 which covers the entire surface of the wafer 100, including the interiors of the damascene vias 510.
- the second ARC layer 620 is processed using a known technique (e.g., via-first dual damascene processing) which reflows the anti-reflective coating material into the contact holes or damascene vias 510 at a low temperature (e.g., approximately 170 to 230 °C) as is known in the art related to via-first dual damascene processing.
- a known technique e.g., via-first dual damascene processing
- a low temperature e.g., approximately 170 to 230 °C
- This deposition of the ARC layer 620 is followed by the subsequent deposition and patterning of photoresist layer 610 which is used to selectively open a continuous space 630 in the second anti-reflective layer 620.
- the patterned photoresist layer 610 is located on top of the ARC layer 620, and- is patterned with the desired damascene wire -pattern.
- FIG. 7 the structure of FIG. 6 is shown following etching of exposed portions of the second anti-reflective coating layer 620, using a process which etches the second anti-reflective coating layer 620 in selected areas, but which does not substantially etch the silicon dioxide layer 450.
- FIG. 8 depicts the structure of FIG. 7 after continued RIE etching to a reduced height of a portion of the silicon dioxide layer 450 that exists between the damascene troughs, and further etching to round off corners 810 (shown in phantom) of the silicon dioxide layer 450 to promote good liner and copper fill in subsequent processing steps.
- Etching of the portion of the silicon dioxide layer 450 to a reduced height results in an increase in the continuous space 630, now extending between damascene vias 510 and silicon dioxide layer 450.
- the etch used in this step may be, inter alia, a silicon dioxide RIE which is used to etch the damascene vias 510 to a depth which is deeper ( e . g. , by approximately 50 nm) than the desired final depth.
- This RIE is optimized to round the corners 810 of the silicon dioxide layer 450, while leaving nearly vertical contact sidewalls 830 on the top of the damascene via 510.
- FIG. 9 depicts the structure of FIG. 8 after the photoresist layer
- the photoresist layer 610 strip step is performed such that the ion bombardment on the wafer 100 is minimized, to minimize the rounding of corners 810.
- a non-directional strip such as, in ter al ia , a low wafer bias plasma strip, can be used.
- the continuous space 630 has been extended to include the contact vias 910.
- a high pressure strip process step may be performed.
- RF radio frequency
- most or all of the RF power should be coupled to the top electrode to minimize wafer ion bombardment.
- a two-step strip process can be employed with RF power coupled to the electrode only during the second step of the two step strip when the resist of the photoresist layer 620 has been stripped.
- a two step strip ⁇ process ⁇ wo" ⁇ ld ard in removing polymer or residual ARC from the contact vias 910.
- the RF power must be minimized during the resist strip step, prior to an overstrip step used in the single electrode system, to minimize ion bombardment-induced corner rounding. Note that, for all resist strip processes, the corner rounding is enhanced while fluorinated resist remains on the wafer 100 and the critical parameter to control is the ion bombardment density/energy during the resist strip step, prior to the resist overstrip step(s).
- FIG. 10 depicts the structure of FIG. 9 after the film 140 at the bottom of each contact via 910 is etched using industry standard RIE chemistry to extend each contact via 910 to top surfaces 125 of the damascene tungsten interconnects 120. Accordingly, the continuous space 630 has been further extended to include the extended contact vias 910. As will be discussed infra in conjunction with FIGS. 11-12, a dual damascene copper interconnect will be formed in the continuous space 630. Thus, the bottom of each contact via 910 permits electrical contact with the top surfaces 125 of the damascene tungsten interconnects 120 by the dual damascene copper interconnect to be subsequently formed.
- the damascene vias 510 RIE see FIG. 7
- the resist strip of the photoresist layer 610 see FIG. 8
- the film 140 RIE are all performed in a single RIE chamber or tool.
- the next step in the process involves a hydrofluoric (HF) acid clean (e.g., using a dilute 1% solution of hydrofluoric acid) to remove approximately 10 nm of silicon dioxide from the wafer 100 and, particularly, from on the damascene tungsten interconnects 120.
- This acid clean is performed to defluorinate the surface and also to remove any residual polymer.
- the concentration of the hydrofluoric acid may include, in ter al ia, between about 10:1 and about 500:1, preferably about 100:1.
- the 100:1 dilution here refers to diluting the HF as it comes from the bottle, which actually, as it comes from the manufacturer is about 1 part water to 1 part HF.
- the dilutions listed in this speci ication are with respect to the HF from the bottle.
- NMPTM are typically performed to clean off tungsten or suicided silicon surfaces. Hydrofluoric acid is not known to etch refractory metal oxides or other such products (oxides formed from titanium, tungsten, cobalt, etc. ) .
- the standard AZTM, or other, -solvent cleans performed for single damascene structures results in sharply degraded (i.e., sharply decreased) contact remittances of the refractory metal, perhaps due to either the inability to totally remove the solvent from voids in the damascene local tungsten interconnect, or to the inability to remove damaged regions on the tungsten surface.
- the etch step of FIG. 10 may be followed with an argon (Ar) sputter clean which is directed to the sputter removal of silicon dioxide or other etch residuals such as tungsten oxide on top of the damascene tungsten interconnects 120 or elsewhere on the wafer 100.
- this argon sputter clean removes about 10 nm of silicon dioxide from planar surfaces.
- the argon gas may also include other dopant gases, such as, inter alia, hydrogen or helium.
- the sputter clean needs to be of sufficiently long duration to fully remove the residue from the wafer 100.
- Empirical evidence shows that the time required to sputter away 5 nm of residue is insufficient to remove unwanted residue, while the necessary time to sputter away 10 nm is sufficient.
- silicon dioxide is removed with the argon sputter clean, a problem arises in that rounding of the corners of the etched structures can result. Therefore, a balance must be found so that s sufficient amount is sputter cleaned, but not an excessive amount.
- An example of too much would be about 20 nm.
- An example of too little would be about 5 nm.
- FIG. 10 After the sputter preclean, and referring now to FIG. 11, the structure of FIG. 10 is shown after deposition of a film stack 1125 which is composed of layers 1110 of tantalum-nitride and tantalum (copper diffusion barriers), and a thin sputtered copper layer 1115, which covers the exposed wafer 100 surfaces.
- This film stack 1125 provides good sidewall coverage.
- a tantalum nitride/tantalum/copper (TaN/Ta/Cu) deposition process such as ionized physical vapor deposition (IPVD), hollow cathode magnetron (HCM) , chemical vapor deposition (CVD) , long- throw sputter, or a combination of these, is employed.
- IPVD ionized physical vapor deposition
- HCM hollow cathode magnetron
- CVD chemical vapor deposition
- TaN/Ta/Cu film stack using IPVD a 10 nm/40 nm/100 nm TaN/Ta/Cu film stack using IPVD was deposited, though many other TaN/Ta/Cu thickness combinations may be used.
- Ta is described herein, any other refractory metal or a combination of metals could be used instead of Ta, such as tantalum nitride, titanium nitride, tungsten nitride, tungsten, etc.
- the TaN/Ta layer 1110 is deposited as any standard copper diffusion barrier, using any refractory metal (listed supra) , followed by a thin sputtered copper layer 1115.
- the thin sputtered copper layer 1115 acts as -a -s «cd f ⁇ lm, for the subsequent copper plating.
- the sputtere -copper layer 1115 may be replaced by electroless plated copper.
- a thick copper layer 1120 is electroplated upon the entire wafer surface and fills all depressions.
- a nominal thickness for the tantalum nitride portion of the TaN/Ta layer 1110 is approximately 10 nm; for the tantalum portion of the TaN/Ta layer 1110 approximately 40 nm; and for the sputtered copper layer 1115, approximately 100 nm.
- these thicknesses can be tailored for the particular dimensions desired in the fabrication process.
- the typical depth of contact vias 910 is about 450 nm, and the minimum trough width of contact vias 910 is about 250 nm.
- the minimum contact width to the damascene tungsten interconnects 120 is about 250 nm, and the contact height is about 500 nm.
- the electroplated copper layer 1120 thickness is slightly thicker than about 750 nm.
- the reason that the electroplated copper layer 1120 must be slightly thicker than the height of the film 140 and the silicon dioxide layer 450, in combination, is because the electroplated copper layer 1120 tends to produce a nonconformal fill which does not come up on all surfaces equally. Therefore, to ensure that electroplated copper layer 1120 fits properly, it must be plated a little thicker, approximately 10 % thicker, than the height of the film 140 and the silicon dioxide layer 450, in combination.
- the electroplated copper layer 1120 may be even thicker than just described.
- Other methods of copper fill such as a combination of PVD and CVD could be used instead of electroplating.
- an optional anneal such as, in ter alia, 100 °C, 1 hour, is performed to crystallize the electroplated copper layer 1120.
- FIG. 12 depicts the structure of FIG. 11 after the upper surface of the wafer 100 has been planarized using a copper chemical-mechanical polish process.
- This planarization process may be a wet-mechanical polish process used to remove the upper portion of the electroplated copper layer 1120 along with the top portion of the TaN/Ta layer 1110.
- the electroplated copper layer 1120 is polished using an industry-standard known process, and stopping on the TaN/Ta layer 1110. In general, it is well known in the art to polish copper and stop on a liner or endpoint, and then to switch processes and polish the liner. Then, one can CMP the wafer to remove the tantalum nitride and tantalum copper diffusion barrier. Alternatively, one can employ a single step CMP process which removes both the tantalum nitride/tantalum copper diffusion barrier in a single step.
- the polishing of the electroplated copper layer 1120 is preferably done for a longer period than for a single damascene process.
- the overpolish for the dual damascene process should be 30 to 100 % longer than for the single damascene process. This increased polish time is required to clear the copper between closely spaced damascene contacts due to the presence of corner rounding in these structures.
- a copper polish process with an increased chemical etch component for example one using 4 % peroxide, is employed.
- polish step is employed to remove the top portion of the TaN/Ta layers 1110.
- This polish step continues down to the silicon dioxide layer 450. This step typically removes some (e.g., approximately 50 nm) of the silicon dioxide layer 450 as well.
- an optional 300 to 450 °C anneal is employed to enhance the testability of the resultant dual damascene copper interconnect 1250, which is in electrically conductive contact with the damascene tungsten interconnects 120.
- the dual damascene copper interconnect 1250 has contact vias 1251 and 1252.
- the contact vias 1251 and 1252 are portions of the dual damascene copper interconnect 1250 which make a direct electrical connection with the damascene tungsten interconnects 120.
- the contact vias 1251 and 1252 each have a width about 250 nm, and a height H L about 300 nm.
- the dual damascene copper interconnect 1250 has a total width ⁇ about 250 nm, and a total height H ⁇ about 320 nm.
- FIG. 12 shows the film 140 as having a first portion 141, a second portion 142, and a third portion 143.
- FIG. 12 also shows the silicon dioxide layer 450 as having a first portion 451, a second portion 452, and a third portion 453.
- the 450 is on the first portion 141 of the film 140, and is contacting a first surface 1251 of the dual damascene copper interconnect 1250.
- the second portion 452 of the silicon dioxide layer 450 is on the second portion 142 of the film 140, and is contacting a second surface 1252 of the dual damascene copper interconnect 1250.
- the third portion 453 of the silicon dioxide layer 450 is on the third portion 143 of the film 140, and is disposed between the dual damascene copper interconnect 1250 and the third portion 143 of the film 140.
- the damascene tungsten interconnects 120 of FIGS. 1-12 can be replaced by silicon volumes 1310 and 1320 which may include diffusions, transistors, and other passive or active devices.
- silicon volumes 1310 and 1320 may include diffusions, transistors, and other passive or active devices.
- care must be exercised to prevent copper from diffusing through the TaN/Ta liner 1110 into the silicon volumes 1310 and 1320, because copper degrades the proper use of any type of transistor, and of metal oxide semiconductor (MOS) transistors in particular.
- MOS metal oxide semiconductor
- damascene tungsten interconnects 120 may be generalized to, and identified as, electrically conducting regions 120 which include, inter alia, damascene refractory metal interconnects (e.g., damascene tungsten interconnects) or semiconductor material (e.g., silicon) .
- damascene refractory metal interconnects e.g., damascene tungsten interconnects
- semiconductor material e.g., silicon
- FIG. 14A and FIG. 14B depict a cross-sectional view and an associated plan view, respectively, of a multiplicity of dual damascene copper wires 1250 and contact vias 1251, 1252, 1410, with the contact vias 1251, 1252, 1410 connecting down to a damascene tungsten wiring level 90 at damascene tungsten interconnects 120.
- the damascene copper wires 1250 shown in FIG. 14B can have zero, one, or more than one, dual damascene contact vias 1251, 1252, 1410.
- FIG. 14A and FIG. 14B depict a cross-sectional view and an associated plan view, respectively, of a multiplicity of dual damascene copper wires 1250 and contact vias 1251, 1252, 1410, with the contact vias 1251, 1252, 1410 connecting down to a damascene tungsten wiring level 90 at damascene tungsten interconnects 120.
- the damascene copper wires 1250 shown in FIG. 14B can have zero, one, or more
- the 14B shows the plan view of the damascene copper wires 1250 and (hidden) dual damascene contact vias (the damascene tungsten wiring level, under the contact vias, is not shown) .
- the size of the copper wires 1250 is not limited, and may be enlarged to form an electrically conductive level, such as, in ter alia, a ground plane.
- the film 140 may generally be viewed as an etch stop layer with respect to selectively etching the silicon dioxide layer 450 above, as described supra in conjunction with FIG. 5. Accordingly, the film 140 may include an etch stop insulative material such as, in ter alia, silicon nitride, silicon carbide (SiC ⁇ H y ) , or silicon carbon-hydrogen-nitrogen compounds ( SiC IntelH y N .
- an etch stop insulative material such as, in ter alia, silicon nitride, silicon carbide (SiC ⁇ H y ) , or silicon carbon-hydrogen-nitrogen compounds ( SiC IntelH y N .
- the layers 150, 350, and 450 may generally be viewed as electrically insulative layers which include an insulative material such as, inter alia, silicon dioxide, fluorine doped or carbon doped dielectrics could be used to reduce the dielectric constant of the oxides.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0322556A GB2391388B (en) | 2001-03-23 | 2002-03-25 | Electronic structure |
KR10-2003-7011768A KR100530306B1 (en) | 2001-03-23 | 2002-03-25 | Electronic structure |
JP2002576013A JP2004532519A (en) | 2001-03-23 | 2002-03-25 | Manufacturing method of electronic structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/816,977 | 2001-03-23 | ||
US09/816,977 US6566242B1 (en) | 2001-03-23 | 2001-03-23 | Dual damascene copper interconnect to a damascene tungsten wiring level |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002078082A2 true WO2002078082A2 (en) | 2002-10-03 |
WO2002078082A3 WO2002078082A3 (en) | 2003-02-27 |
Family
ID=25222072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2002/001414 WO2002078082A2 (en) | 2001-03-23 | 2002-03-25 | Electronic structure |
Country Status (6)
Country | Link |
---|---|
US (2) | US6566242B1 (en) |
JP (2) | JP2004532519A (en) |
KR (1) | KR100530306B1 (en) |
GB (1) | GB2391388B (en) |
TW (1) | TW587327B (en) |
WO (1) | WO2002078082A2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007516848A (en) * | 2003-12-24 | 2007-06-28 | キャベンディッシュ・キネティックス・リミテッド | Device accommodation method and corresponding apparatus |
EP1796159A3 (en) * | 2005-12-07 | 2007-08-08 | Canon Kabushiki Kaisha | Method for manufacturing a semiconductor device by using a dual damascene process |
KR101063796B1 (en) | 2004-05-28 | 2011-09-09 | 매그나칩 반도체 유한회사 | Method of forming a damascene pattern in a semiconductor device |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3920590B2 (en) * | 2000-06-19 | 2007-05-30 | 株式会社東芝 | Manufacturing method of semiconductor device |
US6740956B1 (en) | 2002-08-15 | 2004-05-25 | National Semiconductor Corporation | Metal trace with reduced RF impedance resulting from the skin effect |
US6703710B1 (en) * | 2002-08-15 | 2004-03-09 | National Semiconductor Corporation | Dual damascene metal trace with reduced RF impedance resulting from the skin effect |
US6864581B1 (en) | 2002-08-15 | 2005-03-08 | National Semiconductor Corporation | Etched metal trace with reduced RF impendance resulting from the skin effect |
US6853079B1 (en) | 2002-08-15 | 2005-02-08 | National Semiconductor Corporation | Conductive trace with reduced RF impedance resulting from the skin effect |
US7091133B2 (en) * | 2003-01-27 | 2006-08-15 | Asm Japan K.K. | Two-step formation of etch stop layer |
US6873057B2 (en) * | 2003-02-14 | 2005-03-29 | United Microelectrtonics Corp. | Damascene interconnect with bi-layer capping film |
US7387960B2 (en) * | 2003-09-16 | 2008-06-17 | Texas Instruments Incorporated | Dual depth trench termination method for improving Cu-based interconnect integrity |
US7361605B2 (en) * | 2004-01-20 | 2008-04-22 | Mattson Technology, Inc. | System and method for removal of photoresist and residues following contact etch with a stop layer present |
KR100701375B1 (en) * | 2004-07-08 | 2007-03-28 | 동부일렉트로닉스 주식회사 | Method for fabricating metal line in a semiconductor |
US7223684B2 (en) * | 2004-07-14 | 2007-05-29 | International Business Machines Corporation | Dual damascene wiring and method |
US7253501B2 (en) * | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
US20060051965A1 (en) * | 2004-09-07 | 2006-03-09 | Lam Research Corporation | Methods of etching photoresist on substrates |
US7795150B2 (en) * | 2004-11-29 | 2010-09-14 | Renesas Electronics America Inc. | Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition |
US7288487B1 (en) * | 2004-12-01 | 2007-10-30 | Spansion Llc | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure |
US7422983B2 (en) * | 2005-02-24 | 2008-09-09 | International Business Machines Corporation | Ta-TaN selective removal process for integrated device fabrication |
US20060228881A1 (en) * | 2005-04-08 | 2006-10-12 | Texas Instruments Incorporated | Structure and method for minimizing substrate effect on nucleation during sputtering of thin film resistors |
US7501690B2 (en) * | 2005-05-09 | 2009-03-10 | International Business Machines Corporation | Semiconductor ground shield method |
US7713865B2 (en) * | 2005-06-24 | 2010-05-11 | International Business Machines Corporation | Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation |
US7915735B2 (en) * | 2005-08-05 | 2011-03-29 | Micron Technology, Inc. | Selective metal deposition over dielectric layers |
US7323410B2 (en) * | 2005-08-08 | 2008-01-29 | International Business Machines Corporation | Dry etchback of interconnect contacts |
US7572741B2 (en) | 2005-09-16 | 2009-08-11 | Cree, Inc. | Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen |
US7998809B2 (en) * | 2006-05-15 | 2011-08-16 | Micron Technology, Inc. | Method for forming a floating gate using chemical mechanical planarization |
US20070269975A1 (en) * | 2006-05-18 | 2007-11-22 | Savas Stephen E | System and method for removal of photoresist and stop layer following contact dielectric etch |
US7585758B2 (en) | 2006-11-06 | 2009-09-08 | International Business Machines Corporation | Interconnect layers without electromigration |
KR101100142B1 (en) * | 2007-02-21 | 2011-12-29 | 후지쯔 세미컨덕터 가부시키가이샤 | Semiconductor device and process for producing the same |
JP5165287B2 (en) * | 2007-06-27 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | Wiring structure and manufacturing method thereof |
US20090087992A1 (en) * | 2007-09-28 | 2009-04-02 | Chartered Semiconductor Manufacturing Ltd. | Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first scheme |
US8105937B2 (en) * | 2008-08-13 | 2012-01-31 | International Business Machines Corporation | Conformal adhesion promoter liner for metal interconnects |
US20100104770A1 (en) * | 2008-10-27 | 2010-04-29 | Asm Japan K.K. | Two-step formation of hydrocarbon-based polymer film |
KR200452428Y1 (en) * | 2008-10-27 | 2011-02-25 | 김정대 | Led light emitting device for fishing float |
US8723325B2 (en) | 2009-05-06 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of forming a pad structure having enhanced reliability |
US8134234B2 (en) * | 2009-06-18 | 2012-03-13 | Kabushiki Kaisha Toshiba | Application of Mn for damage restoration after etchback |
FR2963160A1 (en) * | 2010-07-22 | 2012-01-27 | St Microelectronics Crolles 2 | METHOD FOR PRODUCING A METALLIZATION LEVEL AND A VIA LEVEL AND CORRESPONDING INTEGRATED CIRCUIT |
CN102403263B (en) * | 2010-09-17 | 2014-06-04 | 中芯国际集成电路制造(北京)有限公司 | Trench etching method in double Damascus structure |
US8546250B2 (en) | 2011-08-18 | 2013-10-01 | Wafertech Llc | Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another |
US9269612B2 (en) * | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
WO2013094213A1 (en) * | 2011-12-20 | 2013-06-27 | 株式会社 東芝 | Ceramic copper circuit board and semiconductor device employing same |
US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
US9240376B2 (en) | 2013-08-16 | 2016-01-19 | Globalfoundries Inc. | Self-aligned via fuse |
US9425093B2 (en) * | 2014-12-05 | 2016-08-23 | Tokyo Electron Limited | Copper wiring forming method, film forming system, and storage medium |
US9431343B1 (en) | 2015-03-11 | 2016-08-30 | Samsung Electronics Co., Ltd. | Stacked damascene structures for microelectronic devices |
US9613861B2 (en) | 2015-08-05 | 2017-04-04 | Globalfoundries Inc. | Damascene wires with top via structures |
US9859156B2 (en) * | 2015-12-30 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure with sidewall dielectric protection layer |
US9761526B2 (en) | 2016-02-03 | 2017-09-12 | Globalfoundries Inc. | Interconnect structure having tungsten contact copper wiring |
US9741812B1 (en) | 2016-02-24 | 2017-08-22 | International Business Machines Corporation | Dual metal interconnect structure |
US9905459B1 (en) * | 2016-09-01 | 2018-02-27 | International Business Machines Corporation | Neutral atom beam nitridation for copper interconnect |
US11043465B2 (en) * | 2017-05-11 | 2021-06-22 | Sumitomo Electric Industries, Ltd. | Semiconductor device |
US10361120B2 (en) * | 2017-11-30 | 2019-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure |
US10347528B1 (en) * | 2018-03-06 | 2019-07-09 | Globalfoundries Inc. | Interconnect formation process using wire trench etch prior to via etch, and related interconnect |
US11101175B2 (en) * | 2018-11-21 | 2021-08-24 | International Business Machines Corporation | Tall trenches for via chamferless and self forming barrier |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000019498A1 (en) * | 1998-10-01 | 2000-04-06 | Applied Materials, Inc. | In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications |
JP2000150644A (en) * | 1998-11-10 | 2000-05-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US6096655A (en) * | 1998-09-02 | 2000-08-01 | International Business Machines, Corporation | Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure |
EP1033745A2 (en) * | 1999-03-02 | 2000-09-06 | Motorola, Inc. | Method for forming a barrier layer for use in a copper interconnect |
JP2000260870A (en) * | 1999-03-12 | 2000-09-22 | Toshiba Corp | Manufacture of semiconductor device using dry etching |
US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4789648A (en) | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US5071518A (en) | 1989-10-24 | 1991-12-10 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer interconnect |
US5137597A (en) | 1991-04-11 | 1992-08-11 | Microelectronics And Computer Technology Corporation | Fabrication of metal pillars in an electronic component using polishing |
US5169802A (en) | 1991-06-17 | 1992-12-08 | Hewlett-Packard Company | Internal bridging contact |
EP0609496B1 (en) | 1993-01-19 | 1998-04-15 | Siemens Aktiengesellschaft | Process of making a metallization stage comprising contacts and runners which canneet these contacts |
US5447887A (en) | 1994-04-01 | 1995-09-05 | Motorola, Inc. | Method for capping copper in semiconductor devices |
KR100215759B1 (en) | 1994-12-19 | 1999-08-16 | 모리시타 요이치 | Semiconductor device and manufacturing method thereof |
EP0751566A3 (en) | 1995-06-30 | 1997-02-26 | Ibm | A thin film metal barrier for electrical interconnections |
JPH09115875A (en) * | 1995-10-20 | 1997-05-02 | Texas Instr Japan Ltd | Semiconductor device manufacturing method and treating liq. for this manufacturing method |
US5670425A (en) | 1995-11-09 | 1997-09-23 | Lsi Logic Corporation | Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench |
JPH09330981A (en) * | 1996-06-12 | 1997-12-22 | Mitsubishi Gas Chem Co Inc | Manufacture of semiconductor device |
US6429120B1 (en) * | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US5950102A (en) | 1997-02-03 | 1999-09-07 | Industrial Technology Research Institute | Method for fabricating air-insulated multilevel metal interconnections for integrated circuits |
KR100243286B1 (en) * | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
US5821168A (en) * | 1997-07-16 | 1998-10-13 | Motorola, Inc. | Process for forming a semiconductor device |
US6051881A (en) | 1997-12-05 | 2000-04-18 | Advanced Micro Devices | Forming local interconnects in integrated circuits |
JP3403058B2 (en) * | 1998-03-26 | 2003-05-06 | 株式会社東芝 | Wiring formation method |
JP3228217B2 (en) * | 1998-03-27 | 2001-11-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
JP4095731B2 (en) * | 1998-11-09 | 2008-06-04 | 株式会社ルネサステクノロジ | Semiconductor device manufacturing method and semiconductor device |
US6028015A (en) * | 1999-03-29 | 2000-02-22 | Lsi Logic Corporation | Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption |
US6211071B1 (en) * | 1999-04-22 | 2001-04-03 | Advanced Micro Devices, Inc. | Optimized trench/via profile for damascene filling |
US6326301B1 (en) * | 1999-07-13 | 2001-12-04 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
JP3235062B2 (en) * | 1999-07-26 | 2001-12-04 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
JP2001053151A (en) * | 1999-08-17 | 2001-02-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method of the same |
WO2001015211A1 (en) * | 1999-08-26 | 2001-03-01 | Brewer Science | Improved fill material for dual damascene processes |
JP2001068455A (en) * | 1999-08-30 | 2001-03-16 | Hitachi Ltd | Manufacture of semiconductor device |
US6168984B1 (en) * | 1999-10-15 | 2001-01-02 | Taiwan Semiconductor Manufacturing Company | Reduction of the aspect ratio of deep contact holes for embedded DRAM devices |
US6541863B1 (en) * | 2000-01-05 | 2003-04-01 | Advanced Micro Devices, Inc. | Semiconductor device having a reduced signal processing time and a method of fabricating the same |
US6284657B1 (en) * | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
US6576550B1 (en) * | 2000-06-30 | 2003-06-10 | Infineon, Ag | ‘Via first’ dual damascene process for copper metallization |
-
2001
- 2001-03-23 US US09/816,977 patent/US6566242B1/en not_active Expired - Lifetime
-
2002
- 2002-03-21 TW TW091105493A patent/TW587327B/en not_active IP Right Cessation
- 2002-03-25 GB GB0322556A patent/GB2391388B/en not_active Expired - Fee Related
- 2002-03-25 JP JP2002576013A patent/JP2004532519A/en active Pending
- 2002-03-25 KR KR10-2003-7011768A patent/KR100530306B1/en not_active IP Right Cessation
- 2002-03-25 WO PCT/GB2002/001414 patent/WO2002078082A2/en active Application Filing
-
2003
- 2003-01-07 US US10/338,624 patent/US7230336B2/en not_active Expired - Fee Related
-
2007
- 2007-12-06 JP JP2007316113A patent/JP5220398B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6096655A (en) * | 1998-09-02 | 2000-08-01 | International Business Machines, Corporation | Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure |
WO2000019498A1 (en) * | 1998-10-01 | 2000-04-06 | Applied Materials, Inc. | In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications |
JP2000150644A (en) * | 1998-11-10 | 2000-05-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
EP1033745A2 (en) * | 1999-03-02 | 2000-09-06 | Motorola, Inc. | Method for forming a barrier layer for use in a copper interconnect |
JP2000260870A (en) * | 1999-03-12 | 2000-09-22 | Toshiba Corp | Manufacture of semiconductor device using dry etching |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 08, 6 October 2000 (2000-10-06) & JP 2000 150644 A (MITSUBISHI ELECTRIC CORP), 30 May 2000 (2000-05-30) -& US 6 251 774 B1 (MITSUBISHI) 26 June 2001 (2001-06-26) * |
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 12, 3 January 2001 (2001-01-03) & JP 2000 260870 A (TOSHIBA CORP), 22 September 2000 (2000-09-22) -& US 6 352 931 B1 (TOSHIBA) 5 March 2002 (2002-03-05) * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007516848A (en) * | 2003-12-24 | 2007-06-28 | キャベンディッシュ・キネティックス・リミテッド | Device accommodation method and corresponding apparatus |
KR101063796B1 (en) | 2004-05-28 | 2011-09-09 | 매그나칩 반도체 유한회사 | Method of forming a damascene pattern in a semiconductor device |
EP1796159A3 (en) * | 2005-12-07 | 2007-08-08 | Canon Kabushiki Kaisha | Method for manufacturing a semiconductor device by using a dual damascene process |
US7422981B2 (en) | 2005-12-07 | 2008-09-09 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole |
US7598172B2 (en) | 2005-12-07 | 2009-10-06 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole |
Also Published As
Publication number | Publication date |
---|---|
JP5220398B2 (en) | 2013-06-26 |
JP2008135758A (en) | 2008-06-12 |
GB2391388A (en) | 2004-02-04 |
GB2391388B (en) | 2005-10-26 |
KR100530306B1 (en) | 2005-11-22 |
US7230336B2 (en) | 2007-06-12 |
WO2002078082A3 (en) | 2003-02-27 |
TW587327B (en) | 2004-05-11 |
GB0322556D0 (en) | 2003-10-29 |
JP2004532519A (en) | 2004-10-21 |
US6566242B1 (en) | 2003-05-20 |
US20030232494A1 (en) | 2003-12-18 |
KR20030086603A (en) | 2003-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6566242B1 (en) | Dual damascene copper interconnect to a damascene tungsten wiring level | |
US7393777B2 (en) | Sacrificial metal spacer damascene process | |
US7125792B2 (en) | Dual damascene structure and method | |
US6245663B1 (en) | IC interconnect structures and methods for making same | |
US6744090B2 (en) | Damascene capacitor formed in metal interconnection layer | |
US7550822B2 (en) | Dual-damascene metal wiring patterns for integrated circuit devices | |
US7208404B2 (en) | Method to reduce Rs pattern dependence effect | |
US20050146040A1 (en) | Metal spacer in single and dual damascene processing | |
EP1233449A2 (en) | A method of fabricating a semiconductor device | |
US6436814B1 (en) | Interconnection structure and method for fabricating same | |
JP2002525840A (en) | In situ integrated oxide etching process especially useful for copper dual damascene | |
US7166532B2 (en) | Method for forming a contact using a dual damascene process in semiconductor fabrication | |
US20030181034A1 (en) | Methods for forming vias and trenches with controlled SiC etch rate and selectivity | |
US20040121583A1 (en) | Method for forming capping barrier layer over copper feature | |
US6426558B1 (en) | Metallurgy for semiconductor devices | |
US5849367A (en) | Elemental titanium-free liner and fabrication process for inter-metal connections | |
US7091612B2 (en) | Dual damascene structure and method | |
JP2003508896A (en) | Method of manufacturing an integrated circuit having at least one metallization surface | |
US6599838B1 (en) | Method for forming metal filled semiconductor features to improve a subsequent metal CMP process | |
US6380082B2 (en) | Method of fabricating Cu interconnects with reduced Cu contamination | |
US7192877B2 (en) | Low-K dielectric etch process for dual-damascene structures | |
US7288487B1 (en) | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure | |
US7198705B2 (en) | Plating-rinse-plating process for fabricating copper interconnects | |
KR20070033175A (en) | Method of forming a metal wiring in a semiconductor device | |
GB2323704A (en) | Multilevel interconnects for semiconductors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
ENP | Entry into the national phase |
Ref document number: 0322556 Country of ref document: GB Kind code of ref document: A Free format text: PCT FILING DATE = 20020325 |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020037011768 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002576013 Country of ref document: JP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
122 | Ep: pct application non-entry in european phase |