WO2002079788A2 - Validation fub for an agent - Google Patents
Validation fub for an agent Download PDFInfo
- Publication number
- WO2002079788A2 WO2002079788A2 PCT/US2002/002286 US0202286W WO02079788A2 WO 2002079788 A2 WO2002079788 A2 WO 2002079788A2 US 0202286 W US0202286 W US 0202286W WO 02079788 A2 WO02079788 A2 WO 02079788A2
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- WO
- WIPO (PCT)
- Prior art keywords
- transaction
- data
- external bus
- bus
- validation fub
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/27—Built-in tests
Definitions
- the present invention relates to stress testing for microprocessors and other agents in a computer system. More specifically, the present invention relates to an on-die 5 validation functional unit block ("FUB") provided in an agent such as a microprocessor.
- FUB on-die 5 validation functional unit block
- an "agent” may include any device that communicates with other devices via a common communication bus using a common bus interface protocol.
- Typical agents include microprocessors, memory controllers, bridge interface circuits, digital signal processors and application specific integrated circuits.
- a modern agent may include several hundreds of thousands of transistors fabricated into a single integrated circuit.
- Validation testing includes stress testing. Stress testing involves pushing the operating conditions of an agent to its performance limits to determine that the agent's actual behavior matches simulated predictions. Stress testing, however, is a costly, complicated hit-or-miss process because it traditionally is performed through software- controlled algorithms. When an integrated circuit is manufactured, traditional stress
- testing requires that the integrated circuit execute program instructions that are designed to place the agent in a predetermined condition of stress. For example, software may be written to cause two different processors to continually read and modify data at the same memory location. By creating contention between the two processors, it provides an opportunity for validation personnel to observe the behavior of the processors as they
- FIG. 1 is a simplified block diagram of FUBs in an agent according to an embodiment of the present invention.
- FIG. 2 is a flow diagram illustrating a method of operation according to an
- FIG. 3 illustrates an agent according to another embodiment of the present invention.
- FIG. 4 is a block diagram of a validation FUB according to an embodiment of the present invention.
- FIG. 5 illustrates an embodiment of a processor constructed in accordance with an embodiment of the present invention.
- FIG. 6 illustrates an exemplary computer system according to an embodiment of the present invention.
- FIG. 7 illustrates an exemplary computer system according to another
- Embodiments of the present invention provide a validation FUB for an agent, a hardware system within the agent that places a computer system in a stress condition.
- a validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions.
- the validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.
- FIG. 1 is a simplified block diagram of FUBs in an agent 100 according to an embodiment of the present invention.
- An agent 100 may include a core 110 and data request handler 120 provided in communication with an external bus 130.
- the data request handler 120 may interface with the bus 130 via an external bus controller ("EBC") 140.
- EBC 140 manages the progress of transactions on the external bus 130.
- the 10 core 110 may read and modify data as it executes program instructions. It may generate data requests to the data request handler 120, to read data from or store data to predetermined memory locations of a system memory (not shown).
- the data request handler 120 may receive data requests from the core 110 and from possibly other sources (not shown) within the agent 100. It interprets the data 15 requests and, if the agent must communicate with other agents to fulfill the request, it generates an external bus transaction in response thereto.
- the data request handler 120 may include various queues for management of the data requests and may interface with other FUBs, for example internal caches (not shown), to manage the data requests.
- FUBs for example internal caches (not shown)
- An embodiment of the present invention may introduce a validation FUB 150 into an agent 100.
- the validation FUB 150 may be coupled to the EBC 160 to observe transactions posted on the external bus 130.
- the validation FUB 150 may generate data for a new transaction, called a "harassing" bus transaction, to be posted on the external bus 130.
- a new external bus transaction When a new external bus transaction is observed, a harassing transaction may be generated if a request type of the new transaction matches a predetermined type.
- the first external bus transaction is said to be a "triggering" transaction.
- all external bus transaction may be triggering transactions. In this case, 30 harassing bus transactions would be generated for every transaction on the external bus 130.
- An agent 100 may include a selection multiplexer (“MUX") 160 to select transaction data from either the data request handler 120 or the MUX 160.
- the MUX 160 may be controlled solely by the validation FUB 150.
- the MUX 160 may be controlled both by the validation FUB 150 and by the core 110. In this case, data requests from the core 110 may have a higher priority than the data requests from the validation FUB 150. This 5 alternate embodiment is discussed in greater detail herein.
- the validation FUB 150 may provides several advantages for stress testing over prior, software-controlled schemes.
- the validation FUB 150 operates within the clock domain of the agent in which it sits and, therefore, can create stress test events with greater reliability than would be available in a software-controlled algorithm.
- the validation FUB 150 can observe a triggering bus transaction and generate a new "harassing" bus transaction as the very next bus transaction.
- the validation FUB 150 of the present embodiment can be used in a such a way so as to ensure that a harassing bus transaction is generated in response to each and every bus
- the validation FUB 150 operates within the clock domain of the agent, a clock that often is much faster than the clock domain of the external bus, it may generate
- the external bus is a pipelined bus.
- a pipelined bus protocol such as the bus protocol defined for the Pentium Pro® processor
- data is requested in a bus transaction.
- a bus transaction may be organized into a variety of phases.
- the bus transaction includes an arbitration
- a pipelined bus may permit several bus transactions to be in progress on the bus simultaneously but each request must be in a different phase.
- a second transaction may enter
- the validation FUB 150 because it may operate in the domain of the agent's clock, may detect and respond to triggering conditions often while the triggering bus transaction remains pending on the external bus. Thus, in an embodiment, a validation FUB 150 may generate and post a harassing transaction on the bus before the 5 transaction that triggered it concludes. No known stress testing technique permits an agent to capture and respond to a triggering transaction while the triggering transaction remains pending on an external bus.
- the validation FUB 150 provides another advantage in that it can stress test a single-processor computing system. Software-controlled stress testing typically required
- a validation FUB 150 may eavesdrop on transactions generated by the agent in which it is located and may generate harassing transactions in response to transactions observed on the external bus. Further, no special software is necessary. Thus, instead of investing time and money to develop custom software applications for
- a validation FUB 150 permits developers to stress test their agents in a single-agent system executing off-the-shelf software packages.
- the validation FUB 150 therefore, can dramatically reduce development costs for integrated circuit developers.
- FIG. 2 is a flow diagram illustrating a method of operation 1000 according to an
- Operation may begin when a new transaction is posted on the external bus.
- transaction data may be captured by the validation FUB (box 1010).
- the validation FUB may determine whether a request type of the transaction matches a predetermined triggering condition (box 1020). If so, the validation FUB may generate harassing transaction data using an address 25 captured from the external bus transaction (box 1030).
- the new data request may be output to the EBC (box 1040). If the captured data request did not match the predetermined triggering condition, the method may end.
- the captured address may be modified (box 1050, shown in phantom).
- the 30 captured address may be incremented or decremented by a cache line increment.
- memory systems typically are organized into predetermined units commonly called "cache lines.”
- cache lines are 32 bytes in length. In other processors, cache lines may have different lengths.
- the validation FUB 150 may direct transactions to adjacent locations in system memory. In such an embodiment, rather than direct a new external transaction to the same address as was observed on the external bus, the validation FUB 5 150 may direct the new external transaction to an adjacent cache line.
- captured address may be incremented or decremented by amounts that are less than a cache line unit.
- agents may exchange data in cache line-sized units
- bus transactions typically address system memory using addresses having granularities that are smaller than a cache line increment.
- 10 techniques permit computer systems to identify a data "chunk,” data units that are smaller than a cache line size, that is needed by the requesting agent.
- other agents such as a memory controller or another agent that stored the data
- a data phase of an external bus transaction may occur over four cycles, each transferring an 8 byte chunk.
- the requested chunk may be transferred in a first cycle, followed by the remaining chunks from the cache line in later cycles.
- the validation FUB 150 may cause a new external bus transaction to be posted on the external bus.
- the new bus transaction would have an address that refers to the same cache line in system memory that was referenced by the captured bus transaction but may refer to a different chunk within the cache line than did the captured bus transaction.
- An embodiment of the present invention imposes a priority scheme among data requests from the core 100 and the validation FUB 150.
- data 5 requests from the validation FUB 150 are shown being input to the MUX 160 along with data requests from the data request handler 120.
- data requests from the validation FUB 150 may be thought as "competing" with the data request handler 120 for the resources of the external bus 130.
- the MUX 160 may be controlled not only by the validation FUB 150 but also by the data request handler 120.
- the MUX 160 may select a data request from the data request handler 120 when the core 100 is generating data requests to the data request handler 120.
- the MUX 160 may select data requests from the validation FUB 150 when there are no data requests being generated by the core 100.
- data requests from the data request handler 120 may be processed with higher priority than requests from the
- FIG. 3 illustrates an agent 200 according to another embodiment of the present invention.
- an agent 200 may include a core 210 and a data request handler 220 as in the foregoing embodiment.
- the data request 20 handler 220 may field data requests from various sources within the agent 200 and may generate external bus transactions to fulfill the data requests. It may interface with the bus 230 via an external bus interface (“EBI") 240 which may include electrical drivers and interface circuitry to generate and capture electrical signals on the bus 230.
- EBI external bus interface
- the agent 200 may include a validation FUB 250.
- the validation FUB 250 may interface with the EBI 240 to observe transactions on the external bus 230.
- the validation FUB 250 may output harassing data requests to the data request handler 220.
- the data request handler 220 may include an arbiter 260 for managing data requests input to the data request handler 220 from the 30 core 210 and various other sources.
- the data request handler 220 would include other processing elements 270 to manage and fulfill the data requests.
- the validation FUB 250 may input data requests to the data request handler 220 which would be processed in the same manner as a data request from any other source within the agent 200.
- data requests from the validation FUB 250 could be queued by the data request handler 220 and possibly may be fulfilled within the agent 200 itself, depending upon operating conditions.
- FIG. 3 optionally may operate according to a priority scheme
- the arbiter 260 may be controlled not only by the validation FUB 250 but also by the core 210. While data requests are being generated by the core 210, the arbiter 260 may admit the core data requests to the exclusion of data requests from the validation FUB 250. At other times, the arbiter 260 may admit data requests from the validation FUB 250.
- FIG. 4 is a block diagram of a validation FUB 300 according to an embodiment of the present invention.
- the validation FUB 300 may include a transaction latch 310, a request library 320 and a controller 330.
- the transaction latch 310 may receive transaction data from the external bus 130 and latch it for use elsewhere within the validation FUB 300.
- the request library 320 may be a register memory or other data 15 structure storing data requests.
- the controller 340 may manage operation of the validation FUB 300.
- the request library 320 may store data patterns corresponding to each of the data requests that can be handled by the data request handler 120 (FIG. 1).
- the request library 320 may receive latched address data from the 20 transaction latch 310. Under management from the controller 330, the request library 320 may append address data received from the transaction latch 310 to a request pattern stored within to form a data request.
- the request library 320 may output the data request to the MUX 360.
- the validation FUB 300 may generate new data requests in response to transactions on the external bus.
- the controller 330 may be a programmable state machine, in an embodiment, having registers (not shown) that store information identifying the data transactions to which the validation FUB 300 should respond. As shown in FIG. 4, the controller 330 may include a first register 332 to store transaction type data and a second register 334 to store a data request index. The transaction type data may determine the triggering 30 condition to which the validation FUB 300 should respond.
- the first register 332 may be a CAM register or some other register having match detection logic. During an initialization mode, transaction type data may be loaded into the first register 332. Thereafter, during stress testing, the controller 330 may receive transaction type data from transactions posted on the external bus 130. If the newly receive transaction type data matches the transaction type data stored during initialization, the controller 330 may determine to output a new data request from the validation FUB 300.
- the data request index may determine how the validation FUB 300 will respond to
- the data request index can address a data request pattern stored in the instruction library 320.
- the controller 330 may apply the index value from the second register 334 to the instruction library 320 and cause data for a harassing 10 transaction to be read out.
- the instruction library 320 may append an address value received from the transaction latch 310 with the data request pattern from the library to create a valid data request.
- the instruction library 320 may receive address data directly from the transaction latch 310. This embodiment permits the validation FUB 300 to 15 generate external bus transactions (via the data request handler 120) that are directed to the same data referenced in the triggering bus transaction. In an alternate embodiment, the instruction library 320 may generate data requests to addresses that are related, but not identical, to the addresses received from the transaction latch 310.
- FIG. 4 illustrates in phantom an optional address manipulator 340 operating under
- the address manipulator 340 may perform arithmetic operations on address data from the transaction latch 310. It may output altered address data to the instruction library 320. For example, the address manipulator 340 may increment or decrement an address by a cache line increment. Alternatively, the address manipulator may increment or decrement the address by a chunk value.
- instructions may be omitted from the transaction library if their use could violate cache coherency or other system integrity mechanisms.
- many multiprocessor computer systems operate according to a cache coherency scheme in which each item of data stored in a processor is assigned a coherency state. The state of the data determines how the processor may use the data. For example, in the known "MESI" protocol, data may be assigned to one of four states:
- 15 of the data may be stored in the caches of other agents.
- An agent may not modify data in shared state without first performing an external bus transaction to ensure that the agent has exclusive control over the copy of data.
- a transaction library may omit certain transactions that could cause a system to violate cache coherency rules. For example, a zero data length transactions such as BRL0 (bus read line with zero length), IO reads and other transactions that require coherency support may be omitted in an 30 embodiment.
- BRL0 bus read line with zero length
- IO reads and other transactions that require coherency support may be omitted in an 30 embodiment.
- FIG. 5 illustrates an embodiment of a processor 400 constructed in accordance with an embodiment of the present invention.
- the processor 400 may include a bus sequencing unit 410 ("BSU") and a core 420. Both the BSU 410 and the core 420 may operate at much greater speeds than are associated with an external bus 430.
- the 35 external bus 430 interconnects the processor 400 with other components such as other processors, memories and other devices (not shown).
- BSUs per se are known. They may include an arbiter 440, a cache memory 450, an internal queue 460 and an external transaction queue 470.
- the arbiter 440 may receive requests from a variety of inputs, such as from the core 420 and perhaps from other sources. Requests may include a request code representing the type of request 5 being made and, where appropriate, an address identifying a memory location to which the request is directed.
- the cache 450 may be an internal memory. As is known, relative to core cache memories (not shown), the cache 450 typically possesses much greater capacity. For example, a typical cache 450 may be a 256 memory. By contrast a core data cache may 10 be a 16K memory and a core instruction cache may be an 16K memory. The cache 450 may be a unified cache, one that stores both instruction data and variable data (collectively, "data"). The BSQ 400 also may interface with higher levels of cache (not show), which may 3H or more in size.
- Read requests from the arbiter 440 may be input to both the cache 450 and to the
- the cache 450 may include control logic (not shown) that can determine whether the requested data is stored in the cache 450. If so, the request is said to "hit” the cache 450. The cache 450 will furnish the requested data to the core 420 over a communication path (also not shown). Otherwise, the request is said to "miss” the cache. The cache 450 may communicate a hit or a miss to the internal queue 430 over a 20 line 452.
- the internal queue 460 may include control circuitry and buffer memory to process requests from the arbiter 430.
- the internal queue 460 also receives hit/miss indicators from the cache 450. If a read request hits the cache 450, the internal queue 460 may permit the queued request to terminate as it advances out of the queue 460. 25 But if a read request misses the cache 450, the request should be completed by retrieving the requested data from an external memory (not shown). In this case, when the read request advances out of the internal queue 460, the internal queue 460 may cause the request to be entered in the external transaction queue 470.
- the external transaction queue 470 also may include control circuitry and buffer
- the external transaction queue 470 may control operation of the bus 430 via an external bus controller 480.
- a bus protocol will have been defined for the bus 430, the external transaction queue 470 and external bus controller 480 may generate and receive signals in accordance with such a protocol.
- FIG. 5 illustrates the internal queue 460 and external transaction queue 470
- reaction queue The principles of the present invention find application with either embodiment. In this regard, the operation and structure of a BSQ 410 is well known.
- a validation FUB 490 may observe data requests posted within the BSQ 410 and generate harassing transactions in response thereto.
- the validation FUB 490 may capture data requests output by the arbiter 440.
- the validation FUB 490 may compare data identifying the request type and source to determine whether to generate a new data request. If so, the new data request may be output to the arbiter 440 for independent processing.
- the BSQ 410 may process both the captured data request
- the validation FUB 490 also may
- triggering conditions may be defined for the validation FUB 490 based not only upon the request type of a data request but also based on whether requested data is present in the internal cache 450.
- a validation FUB 150 may generate a harassing bus
- a validation FUB 150 may generate a harassing bus transaction in the absence of new transactions on the external bus 130.
- Many bus protocols identify the onset of a new transaction with a predetermined signal. In the bus protocol of the Pentium Pro® processor, assertion of an ADS# signal indicates the onset 30 of a new transaction. A new transaction may be posted on the bus during each bus clock cycle.
- a validation FUB 150 may track the number of consecutive cycles that expire without a new transaction being posted on the external bus. If the number exceeds a predetermined threshold (e.g. 2), the validation FUB 150 may spontaneously generate a harassing transaction. The harassing transaction may be directed to an address last captured from an external bus transaction, perhaps having been modified (incremented or decremented).
- FIG. 6 illustrates an exemplary computer system 500 according to an embodiment of the present invention.
- the computer system 500 may include multiple agents 510-560 each coupled to a common communication bus 570. Of 10 the agents, four are shown as processors 510-540. Other agents include a system memory 550 and an IO interface 560.
- a validation FUB 515 is illustrated as being a member of one of the processors 510 but, alternatively, could be provided in one or more of the other agents 520-560.
- FIG. 7 illustrates another exemplary computer system 600 according to an
- multiple agents 610-630 are coupled to a common communication bus 640.
- only one agent 610 is shown as a processor.
- a memory controller 620 and IO interface 630 also are shown in FIG. 7.
- a validation FUB 625 is shown as a member of the memory controller.
- the validation FUB could be a member of the IO interface 630 (not shown).
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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GB0318622A GB2387917B (en) | 2001-03-28 | 2002-01-25 | Validation FUB for an agent |
AU2002240105A AU2002240105A1 (en) | 2001-03-28 | 2002-01-25 | Validation fub for an agent |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/818,788 | 2001-03-28 | ||
US09/818,788 US7032134B2 (en) | 2001-03-28 | 2001-03-28 | Microprocessor design support for computer system and platform validation |
Publications (2)
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WO2002079788A2 true WO2002079788A2 (en) | 2002-10-10 |
WO2002079788A3 WO2002079788A3 (en) | 2004-02-12 |
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PCT/US2002/002286 WO2002079788A2 (en) | 2001-03-28 | 2002-01-25 | Validation fub for an agent |
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US (2) | US7032134B2 (en) |
CN (1) | CN100524242C (en) |
AU (1) | AU2002240105A1 (en) |
GB (3) | GB2409906B (en) |
TW (1) | TW561337B (en) |
WO (1) | WO2002079788A2 (en) |
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DE102006051444C5 (en) * | 2006-10-31 | 2011-12-08 | Softing Ag | Diagnostic method and apparatus for a fieldbus system |
US20090216493A1 (en) * | 2008-02-27 | 2009-08-27 | Underdal Olav M | Hierarchy of diagnosis for advanced diagnostics equipment |
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CN103729259B (en) * | 2012-10-12 | 2017-02-01 | 安凯(广州)微电子技术有限公司 | Verification method and device for AHB read-write burst mutual interruption |
CN104317683A (en) * | 2014-09-26 | 2015-01-28 | 浪潮电子信息产业股份有限公司 | Method for testing power consumption of memory |
US10126362B2 (en) * | 2014-12-15 | 2018-11-13 | International Business Machines Corporation | Controlling a test run on a device under test without controlling the test equipment testing the device under test |
CN107341082A (en) * | 2017-07-21 | 2017-11-10 | 郑州云海信息技术有限公司 | A kind of server system places an order and deposits power consumption test design method in vivo |
CN107992387A (en) * | 2017-11-30 | 2018-05-04 | 郑州云海信息技术有限公司 | Monomer hard disk power consumption test method under a kind of server system |
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- 2002-01-25 GB GB0318622A patent/GB2387917B/en not_active Expired - Fee Related
- 2002-01-25 WO PCT/US2002/002286 patent/WO2002079788A2/en not_active Application Discontinuation
- 2002-01-25 AU AU2002240105A patent/AU2002240105A1/en not_active Abandoned
- 2002-01-25 GB GB0506951A patent/GB2409907B/en not_active Expired - Fee Related
- 2002-01-25 CN CNB028075463A patent/CN100524242C/en not_active Expired - Fee Related
- 2002-03-05 TW TW091104063A patent/TW561337B/en not_active IP Right Cessation
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2005
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Also Published As
Publication number | Publication date |
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CN1500247A (en) | 2004-05-26 |
GB0506950D0 (en) | 2005-05-11 |
GB0506951D0 (en) | 2005-05-11 |
TW561337B (en) | 2003-11-11 |
GB2387917B (en) | 2005-06-08 |
GB0318622D0 (en) | 2003-09-10 |
US7487398B2 (en) | 2009-02-03 |
AU2002240105A1 (en) | 2002-10-15 |
CN100524242C (en) | 2009-08-05 |
WO2002079788A3 (en) | 2004-02-12 |
US20020144183A1 (en) | 2002-10-03 |
GB2409906B (en) | 2005-09-21 |
GB2409907A (en) | 2005-07-13 |
GB2409906A (en) | 2005-07-13 |
US7032134B2 (en) | 2006-04-18 |
GB2409907B (en) | 2005-09-21 |
US20060107120A1 (en) | 2006-05-18 |
GB2387917A (en) | 2003-10-29 |
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