WO2002080275A3 - Speicherzellenarrays und deren herstellungssverfahren - Google Patents

Speicherzellenarrays und deren herstellungssverfahren Download PDF

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Publication number
WO2002080275A3
WO2002080275A3 PCT/EP2002/001508 EP0201508W WO02080275A3 WO 2002080275 A3 WO2002080275 A3 WO 2002080275A3 EP 0201508 W EP0201508 W EP 0201508W WO 02080275 A3 WO02080275 A3 WO 02080275A3
Authority
WO
WIPO (PCT)
Prior art keywords
bitline
recesses
substrate
production
memory medium
Prior art date
Application number
PCT/EP2002/001508
Other languages
English (en)
French (fr)
Other versions
WO2002080275A2 (de
Inventor
Ronald Kakoschke
Josef Willer
Original Assignee
Infineon Technologies Ag
Ronald Kakoschke
Josef Willer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Ronald Kakoschke, Josef Willer filed Critical Infineon Technologies Ag
Priority to AU2002338242A priority Critical patent/AU2002338242A1/en
Priority to EP02757712A priority patent/EP1364409A2/de
Priority to KR1020037011519A priority patent/KR100608407B1/ko
Priority to JP2002578576A priority patent/JP2004530296A/ja
Publication of WO2002080275A2 publication Critical patent/WO2002080275A2/de
Publication of WO2002080275A3 publication Critical patent/WO2002080275A3/de

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Ein Verfahren zum Herstellen von Bitleitungen (40) für ein Speicherzellenarray umfaßt zunächst den Schritt des Bereitstellens einer Schichtstruktur aus einem Substrat (10) mit in eine Oberfläche desselben implantierten Transistorwannen (12), einer auf der Oberfläche des Substrats (10) vorgesehenen Speichermediumschichtfolge (20) und einer auf der Speichermediumschichtfolge (20) vorgesehenen Gatebereichschicht (22). In der Gatebereichschicht (22) werden Bitleitungsausnehmungen, die bis zu der Speichermediumschichtfolge (20) reichen, erzeugt. Nachfolgend werden isolierende Abstandsschichten (36) auf seitlichen Oberflächen der Bitleitungsausnehmungen erzeugt, woraufhin eine Source/Drainimplantation (38) nach einer vollständigen oder teilweisen Beseitigung der Speichermediumschichtfolge (20) im Bereich der Bitleitungsausnehmungen durchgeführt wird. Im Anschluß wird das Substrat im Bereich der Bitleitungsausnehmungen vollständig freigelegt, falls dies vor der Implantation nicht erfolgt ist. Dann werden auf dem freigelegten Substrat Metallisierungen zum Erzeugen von metallischen Bitleitungen (40) erzeugt, wobei die Metallisierungen durch die isolierenden Abstandsschichten (36) von der Gatebereichschicht (22) isoliert sind.
PCT/EP2002/001508 2001-03-02 2002-02-13 Speicherzellenarrays und deren herstellungssverfahren WO2002080275A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002338242A AU2002338242A1 (en) 2001-03-02 2002-02-13 Memory cell arrays and method for the production thereof
EP02757712A EP1364409A2 (de) 2001-03-02 2002-02-13 Verfahren zum herstellen von metallischen bitleitungen für speicherzellenarrays, verfahren zum herstellen von speicherzellenarrays und speicherzellenarray
KR1020037011519A KR100608407B1 (ko) 2001-03-02 2002-02-13 비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이
JP2002578576A JP2004530296A (ja) 2001-03-02 2002-02-13 メモリセルアレイの金属性ビット線の製造方法、メモリセルアレイの製造方法、およびメモリセルアレイ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10110150.3 2001-03-02
DE10110150A DE10110150A1 (de) 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray

Publications (2)

Publication Number Publication Date
WO2002080275A2 WO2002080275A2 (de) 2002-10-10
WO2002080275A3 true WO2002080275A3 (de) 2003-01-30

Family

ID=7676114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/001508 WO2002080275A2 (de) 2001-03-02 2002-02-13 Speicherzellenarrays und deren herstellungssverfahren

Country Status (9)

Country Link
US (1) US6686242B2 (de)
EP (1) EP1364409A2 (de)
JP (1) JP2004530296A (de)
KR (1) KR100608407B1 (de)
CN (1) CN100336227C (de)
AU (1) AU2002338242A1 (de)
DE (1) DE10110150A1 (de)
TW (1) TW540141B (de)
WO (1) WO2002080275A2 (de)

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Also Published As

Publication number Publication date
EP1364409A2 (de) 2003-11-26
KR20030088444A (ko) 2003-11-19
US6686242B2 (en) 2004-02-03
WO2002080275A2 (de) 2002-10-10
AU2002338242A1 (en) 2002-10-15
CN1502134A (zh) 2004-06-02
TW540141B (en) 2003-07-01
JP2004530296A (ja) 2004-09-30
DE10110150A1 (de) 2002-09-19
KR100608407B1 (ko) 2006-08-03
CN100336227C (zh) 2007-09-05
US20020132430A1 (en) 2002-09-19

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