WO2002093625B1 - Method of making a flexible substrate containing self-assembling microstructures - Google Patents

Method of making a flexible substrate containing self-assembling microstructures

Info

Publication number
WO2002093625B1
WO2002093625B1 PCT/US2002/021638 US0221638W WO02093625B1 WO 2002093625 B1 WO2002093625 B1 WO 2002093625B1 US 0221638 W US0221638 W US 0221638W WO 02093625 B1 WO02093625 B1 WO 02093625B1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
less
amorphous thermoplastic
article
recesses
Prior art date
Application number
PCT/US2002/021638
Other languages
French (fr)
Other versions
WO2002093625A1 (en
Inventor
Pi Chang
Philip Yi Zhi Chu
Dong Hseih
Robert M Pricone
W Scott Thielman
Original Assignee
Avery Dennison Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avery Dennison Corp filed Critical Avery Dennison Corp
Priority to EP02749869A priority Critical patent/EP1366509A1/en
Publication of WO2002093625A1 publication Critical patent/WO2002093625A1/en
Publication of WO2002093625B1 publication Critical patent/WO2002093625B1/en

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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24355—Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Abstract

A substrate having embossed thereon a plurality of shaped recesses of a predetermined precise geometric profile, each recess having a flat bottom surface having a major dimension of about 500 ν or less, the substrate being capable of undergoing a thermal cycle of about one hour at about 150 °C while maintaining about ± 10 ν or less dimensional stability of the embossed shaped indentations, and wherein the substrate comprises an amorphous thermoplastic material. During the thermal cycle the substrate has an elastic modulus greater than about 1010 dynes/cm2 and a viscoelastic index of less than about 0.1.

Claims

37
AMENDED CLAIMS
[received by the International Bureau on 26 November 2002 (26.11.2002); original claims 1, 14 and 30 amended; remaining claims unchanged (3 pages)]
1. A substrate having embossed thereon a plurality of shaped recesses of predetermined dimensions, each recess having a flat bottom surface, the largest dimension of each such flat bottom surface being about 1000 μm or less, said substrate comprising an amorphous thermoplastic material such that said substrate is capable of undergoing a thermal cycle of about one hour at about 150° C while maintaining about ± 10 μm or less dimensional stability of said embossed shaped indentations. 2. The substrate of claim 1, wherein during said thermal cycle said substrate has an elastic modulus greater than about 1010 dynes/cm2.
3. The substrate of claim 1 , wherein during said thermal cycle said substrate has a viscoelastic index of less than about 0.1.
4. The substrate of claim 1, wherein said substrate is substantially chemically inert to an aqueous solution of about 5% non-ionic surfactant.
5. The substrate of claim 1, wherein said substrate is substantially chemically inert to a solution containing propylene glycol monomethyl ether acetate. 6. The substrate of claim 1, wherein said substrate is substantially chemically inert to a solution comprising phosphoric acid, acetic acid, and nitric acid. 7. The substrate of claim 1, wherein said substrate is substantially chemically inert to a solution containing monoethanolamine. 8. The substrate of claim 1, wherein said amorphous thermoplastic material is in the form of a flexible web capable of being wound about a core. 9. The substrate of claim 1, wherein during said thermal cycle the spacing of said recesses from specified reference points does not vary by more than about + 20 μm. 38
10. The substrate of claim I, wherein each recess is at least about 5 μm deep.
11. The substrate of claim 1 , wherein each recess has a substantially rectangular bottom surface and four outwardly sloping side walls. 12. The substrate of claim 1, wherein said amorphous thermoplastic material is selected from the group consisting of polyarylate, polysulfone, polyetherimide, cyclo-olefmic copolymer, and high Tg polycarbonate.
13. The substrate of claim 1 , wherein said substrate is a multi-layer structure.
14. An article comprising
(a) a substrate comprising a first amorphous thermoplastic layer having embossed on a first surface thereof a plurality of recesses of predetermined dimensions, each recess having a flat bottom surface, the largest dimension of said flat bottom surface being about 1000 μm or less;
(b) a plurality of microstructures respectively disposed within said recesses, said microstructures having dimensions complementary to the dimensions of said recesses; and
(c) a planarization layer disposed over said microstructures and said first surface of said amorphous thermoplastic substrate.
15. The article of claim 14, wherein said substrate further comprises a second amorphous thermoplastic layer disposed opposite said first surface of said amorphous thermoplastic layer in laminar configuration therewith, said second amorphous thermoplastic layer having a dimensional stability of <0.01 % change in dimension, an elastic modulus of greater than about 1010 dynes/cm2, and a viscoelastic index of less than about 0.1, all at a temperature of about 150° C for about 1 hour.
16. The article of claim 15, wherein said second amorphous thermoplastic material is selected from the group consisting of high Tg polycarbonate, polyethylene terephthalate),and polyarylate.
29. The method of claim 26, further including laser forming of vias through the planarization layer to permit predetermined conductive access to said microstructure blocks in the covered recesses.
30. An article comprising a flexible substrate having at least one layer, said layer consisting of an amorphous thermoplastic material having a plurality of micro recesses of predetermined dimensions embossed therein, wherein each recess has a flat bottom surface, the largest dimension of each said flat bottom surface being about 1000 μm or less; an upwardly tapered wall at an angle of between 50° - 70° to the normal of the substrate, a height of between about 5 μm to 100 μm, and an upper opening between about 10 μm to 1000 μm in major dimension.
31. The article of claim 30, wherein the spacing of recesses relative to predetermined references points does not vary by +/- 20 μm or less. 32. The article of claim 30, wherein at least one recess is in the form of a truncated four sided pyramid, having a depth of about 69 μm, angled walls of about 57°, and a base of about 280 μm by 280 μm and a top of about 380 μm by 380 μm.
33. The article of claim 30, wherein the substrate has a thickness of about 180 μm.
34. The article of claim 30, wherein the substrate is formed of a polymeric material selected from a group in which the glass transition temperature Tg is between 163° C and 215° C, and wherein at embossing temperature Te the material has an elastic modulus less than about 1x10s dynes/cm2 and a viscoelastic index greater than about 0.3 if processed up to 150°C and has dimensional stability of <0.01% change and an elastic modulus of greater than about 1010 dynes/cm2, and a viscoelastic index of less than about 0.1. 35. The article of claim 34, wherein at a temperature Te, the elastic modulus is less than about lxl 06 dynes/cm2.
PCT/US2002/021638 2001-02-02 2002-01-30 Method of making a flexible substrate containing self-assembling microstructures WO2002093625A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9495632B2 (en) 2001-02-02 2016-11-15 Avery Dennison Corporation RFID label technique

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6468638B2 (en) * 1999-03-16 2002-10-22 Alien Technology Corporation Web process interconnect in electronic assemblies
US6623579B1 (en) * 1999-11-02 2003-09-23 Alien Technology Corporation Methods and apparatus for fluidic self assembly
US6479395B1 (en) * 1999-11-02 2002-11-12 Alien Technology Corporation Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
DE10053334B4 (en) * 2000-10-27 2018-08-02 Robert Bosch Gmbh Method and device for controlling an actuating element in a vehicle
US6606247B2 (en) 2001-05-31 2003-08-12 Alien Technology Corporation Multi-feature-size electronic structures
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US7214569B2 (en) 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US20040258885A1 (en) * 2002-09-05 2004-12-23 Kreutter Nathan P. Etched dielectric film in microfluidic devices
US20060234042A1 (en) * 2002-09-05 2006-10-19 Rui Yang Etched dielectric film in microfluidic devices
US6764885B2 (en) * 2002-10-17 2004-07-20 Avery Dennison Corporation Method of fabricating transistor device
JP2004140632A (en) * 2002-10-18 2004-05-13 Hitachi Ltd High-frequency transmitting and receiving device and its manufacturing method
US7224280B2 (en) * 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
US6940408B2 (en) * 2002-12-31 2005-09-06 Avery Dennison Corporation RFID device and method of forming
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
US8226880B2 (en) * 2003-07-07 2012-07-24 10X Technology, Llc Process for fabricating precise microstructures
US20050008821A1 (en) * 2003-07-07 2005-01-13 Pricone Robert M. Process and apparatus for fabricating precise microstructures and polymeric molds for making same
US20060051517A1 (en) * 2004-09-03 2006-03-09 Eastman Kodak Company Thermally controlled fluidic self-assembly method and support
US7629026B2 (en) * 2004-09-03 2009-12-08 Eastman Kodak Company Thermally controlled fluidic self-assembly
US7251882B2 (en) 2004-09-03 2007-08-07 Eastman Kodak Company Method for assembling micro-components to binding sites
US7615479B1 (en) 2004-11-08 2009-11-10 Alien Technology Corporation Assembly comprising functional block deposited therein
US7353598B2 (en) * 2004-11-08 2008-04-08 Alien Technology Corporation Assembly comprising functional devices and method of making same
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
WO2006059732A1 (en) 2004-12-03 2006-06-08 Hallys Corporation Interposer bonding device
US7687277B2 (en) 2004-12-22 2010-03-30 Eastman Kodak Company Thermally controlled fluidic self-assembly
US7906722B2 (en) 2005-04-19 2011-03-15 Palo Alto Research Center Incorporated Concentrating solar collector with solid optical element
US7542301B1 (en) * 2005-06-22 2009-06-02 Alien Technology Corporation Creating recessed regions in a substrate and assemblies having such recessed regions
US20070031992A1 (en) * 2005-08-05 2007-02-08 Schatz Kenneth D Apparatuses and methods facilitating functional block deposition
US20070065637A1 (en) * 2005-09-16 2007-03-22 Extrand Charles W Carrier with anisotropic wetting surfaces
US20070169806A1 (en) * 2006-01-20 2007-07-26 Palo Alto Research Center Incorporated Solar cell production using non-contact patterning and direct-write metallization
US20070107773A1 (en) 2005-11-17 2007-05-17 Palo Alto Research Center Incorporated Bifacial cell with extruded gridline metallization
US7765949B2 (en) 2005-11-17 2010-08-03 Palo Alto Research Center Incorporated Extrusion/dispensing systems and methods
US7799371B2 (en) 2005-11-17 2010-09-21 Palo Alto Research Center Incorporated Extruding/dispensing multiple materials to form high-aspect ratio extruded structures
US7855335B2 (en) 2006-04-26 2010-12-21 Palo Alto Research Center Incorporated Beam integration for concentrating solar collector
US7851693B2 (en) 2006-05-05 2010-12-14 Palo Alto Research Center Incorporated Passively cooled solar concentrating photovoltaic device
US20070256725A1 (en) * 2006-05-05 2007-11-08 Palo Alto Research Center Incorporated Solar Concentrating Photovoltaic Device With Resilient Cell Package Assembly
US7922471B2 (en) 2006-11-01 2011-04-12 Palo Alto Research Center Incorporated Extruded structure with equilibrium shape
US8226391B2 (en) 2006-11-01 2012-07-24 Solarworld Innovations Gmbh Micro-extrusion printhead nozzle with tapered cross-section
US8322025B2 (en) 2006-11-01 2012-12-04 Solarworld Innovations Gmbh Apparatus for forming a plurality of high-aspect ratio gridline structures
US7780812B2 (en) 2006-11-01 2010-08-24 Palo Alto Research Center Incorporated Extrusion head with planarized edge surface
US7638438B2 (en) 2006-12-12 2009-12-29 Palo Alto Research Center Incorporated Solar cell fabrication using extrusion mask
US7928015B2 (en) 2006-12-12 2011-04-19 Palo Alto Research Center Incorporated Solar cell fabrication using extruded dopant-bearing materials
US7656017B2 (en) * 2006-12-18 2010-02-02 Stats Chippac Ltd. Integrated circuit package system with thermo-mechanical interlocking substrates
US20090025784A1 (en) 2007-02-02 2009-01-29 Sol Focus, Inc. Thermal spray for solar concentrator fabrication
US7692256B2 (en) * 2007-03-23 2010-04-06 Heptagon Oy Method of producing a wafer scale package
US7954449B2 (en) 2007-05-08 2011-06-07 Palo Alto Research Center Incorporated Wiring-free, plumbing-free, cooled, vacuum chuck
US7999175B2 (en) 2008-09-09 2011-08-16 Palo Alto Research Center Incorporated Interdigitated back contact silicon solar cells with laser ablated grooves
US8117983B2 (en) 2008-11-07 2012-02-21 Solarworld Innovations Gmbh Directional extruded bead control
US8080729B2 (en) 2008-11-24 2011-12-20 Palo Alto Research Center Incorporated Melt planarization of solar cell bus bars
US8960120B2 (en) 2008-12-09 2015-02-24 Palo Alto Research Center Incorporated Micro-extrusion printhead with nozzle valves
US7816856B2 (en) * 2009-02-25 2010-10-19 Global Oled Technology Llc Flexible oled display with chiplets
US8013525B2 (en) 2009-04-09 2011-09-06 Global Oled Technology Llc Flexible OLED display with chiplets
US7973472B2 (en) * 2009-04-15 2011-07-05 Global Oled Technology Llc Display device with polygonal chiplets
US20110079702A1 (en) * 2009-10-06 2011-04-07 International Business Machines Corporation Forming a protective layer on a mold and mold having a protective layer
US20110100418A1 (en) * 2009-11-03 2011-05-05 Palo Alto Research Center Incorporated Solid Linear Solar Concentrator Optical System With Micro-Faceted Mirror Array
US10672748B1 (en) 2010-06-02 2020-06-02 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional heterogeneous technologies integration
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
US20120119421A1 (en) * 2010-11-15 2012-05-17 Lin Allen F C Device and method for processing the embossing structure of 3-layer co-extruded biaxial oriented polypropylene (bopp) pearl synthetic paper
US8040609B1 (en) 2010-11-29 2011-10-18 Palo Alto Research Center Incorporated Self-adjusting solar light transmission apparatus
US8884156B2 (en) 2010-11-29 2014-11-11 Palo Alto Research Center Incorporated Solar energy harvesting device using stimuli-responsive material
US8752380B2 (en) 2012-05-22 2014-06-17 Palo Alto Research Center Incorporated Collapsible solar-thermal concentrator for renewable, sustainable expeditionary power generator system
US20180312421A1 (en) * 2017-04-28 2018-11-01 Corning Incorporated Systems and methods for display formation using a mechanically pressed pattern
JP7292253B2 (en) * 2017-07-12 2023-06-16 スリーエム イノベイティブ プロパティズ カンパニー Faceted microstructured surface
CN111595841B (en) * 2020-05-20 2022-07-05 中国科学院新疆理化技术研究所 Preparation method and application of array type chemical colorimetric vertical display analysis card
CN115331553B (en) * 2022-08-11 2023-11-10 合肥维信诺科技有限公司 Screen support piece and display module

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157223A (en) * 1979-05-25 1980-12-06 Tokyo Shibaura Electric Co Method of manufacturing electret
US5156863A (en) * 1982-09-30 1992-10-20 Stimsonite Corporation Continuous embossing belt
US4601861A (en) * 1982-09-30 1986-07-22 Amerace Corporation Methods and apparatus for embossing a precision optical pattern in a resinous sheet or laminate
US4486363A (en) * 1982-09-30 1984-12-04 Amerace Corporation Method and apparatus for embossing a precision optical pattern in a resinous sheet
US4478769A (en) * 1982-09-30 1984-10-23 Amerace Corporation Method for forming an embossing tool with an optically precise pattern
US4460449A (en) * 1983-01-03 1984-07-17 Amerace Corporation Apparatus for making a tool
US5824186A (en) * 1993-12-17 1998-10-20 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
US5545291A (en) * 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
US5904545A (en) * 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
US5792539A (en) * 1996-07-08 1998-08-11 Oceaneering International, Inc. Insulation barrier
EP1019239B1 (en) * 1997-10-01 2003-05-28 Minnesota Mining And Manufacturing Company Embossed oriented polymer films
US6200399B1 (en) * 1999-01-14 2001-03-13 Avery Dennison Corporation Method and apparatus for embossing a precision pattern of micro-prismatic elements in a resinous sheet or laminate
US6274508B1 (en) * 1999-02-05 2001-08-14 Alien Technology Corporation Apparatuses and methods used in forming assemblies
US6683663B1 (en) * 1999-02-05 2004-01-27 Alien Technology Corporation Web fabrication of devices
US6291896B1 (en) * 1999-02-16 2001-09-18 Alien Technology Corporation Functionally symmetric integrated circuit die
US6316278B1 (en) * 1999-03-16 2001-11-13 Alien Technology Corporation Methods for fabricating a multiple modular assembly
US6257964B1 (en) * 1999-11-01 2001-07-10 Voith Sulzer Paper Technology North America, Inc. Roll grinding system for a roll
US6479395B1 (en) * 1999-11-02 2002-11-12 Alien Technology Corporation Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
US6527964B1 (en) * 1999-11-02 2003-03-04 Alien Technology Corporation Methods and apparatuses for improved flow in performing fluidic self assembly
US6623579B1 (en) * 1999-11-02 2003-09-23 Alien Technology Corporation Methods and apparatus for fluidic self assembly
US6375776B1 (en) * 2000-01-24 2002-04-23 Avery Dennison Corporation Method for forming multi-layer laminates with microstructures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9495632B2 (en) 2001-02-02 2016-11-15 Avery Dennison Corporation RFID label technique

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US20030232174A1 (en) 2003-12-18
US20060210769A1 (en) 2006-09-21
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US20020149107A1 (en) 2002-10-17

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