WO2002093641A1 - Layered hard mask and dielectric materials and methods therefor - Google Patents
Layered hard mask and dielectric materials and methods therefor Download PDFInfo
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- WO2002093641A1 WO2002093641A1 PCT/US2002/015829 US0215829W WO02093641A1 WO 2002093641 A1 WO2002093641 A1 WO 2002093641A1 US 0215829 W US0215829 W US 0215829W WO 02093641 A1 WO02093641 A1 WO 02093641A1
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- layer
- hard mask
- diffusion barrier
- electronic device
- etch stop
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/312—Organic layers, e.g. photoresist
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31652—Of asbestos
- Y10T428/31663—As siloxane, silicone or silane
Definitions
- the field of the invention is manufacture of microelectronic devices, especially relating to damascene processing and methods of deposition of etch resistant material.
- copper and copper alloys are especially promising alternative material because of their greater robustness and higher electrical conductivity.
- copper has an approximately 40% lower resistivity than aluminum, and has fewer reliability problems such as electromigration, etc.
- copper is more difficult to etch than aluminum alloys, and generally can not be processed in a conventional metallization process in which a metal layer is deposited on a substrate and etched to form conductive lines, and in which the space between the lines is subsequently filled with a line dielectric.
- damascene process To circumvent at least some of the problems associated with the use of copper in the fabrication of interconnect structures, a new process for the manufacture of interconnects has been developed, also known as damascene process.
- via and line formation can be integrated into a single process, which is then called dual damascene process.
- a via dielectric layer is laid down onto a substrate, and the via dielectric layer is subsequently coated with a patterned etch stop layer, whereby voids in the etch stop layer correspond to positions of vias that will be etched into the via dielectric.
- a line dielectric is deposited onto the etch stop layer, which in turn is coated with a patterned hard mask layer that defines the traces of the lines.
- via and line traces are formed, whereby the line trenches are etched into the line dielectric until the etchant reaches the etch stop layer.
- the dual damascene process requires sequential deposition of additional layers of dielectric material with different etch selectivity.
- various relatively fast and efficient methods are known in the art to lay down the via and line dielectric material.
- CVD chemical vapor deposition
- CVD typically requires a separate production environment with reduced atmospheric pressure and relatively high temperatures, thereby at least partially limiting the choice of line and via dielectric to materials that are able to withstand such relatively harsh conditions.
- the CVD step is often time consuming, and usually adds additional cost to the production.
- the present invention is directed to electronic devices and related methods, wherein the electronic devices include a hard mask layer that is applied in a liquid phase to a line dielectric layer (preferably in a spin-on process), wherein the hard mask layer comprises a Si-N bond, and wherein the hard mask layer is densified such that etch rate of the hard mask layer is less than the etch rate of both the line dielectric layer and the dielectric layer. It is further contemplated that the hard mask layer, the line dielectric layer, the via dielectric layer, and a copper element form a dual damascene structure.
- Fig. 1 is a flow diagram of one method according to the inventive subject matter.
- Fig. 4 is an exemplary formula of a Si-N bond-containing hard mask material according to the inventive subject matter.
- low dielectric constant refers to a dielectric constant (k-value) of less than 10.
- dielectric constants of less than 6, and more preferably of less than 3.
- etch resistivity to an etchant characterizes the rate and/or dynamics with which an etchant dissolves, or physically or chemically disintegrates a substrate.
- a low etch resistivity corresponds to dissolution of a substrate at a relatively high rate
- a high etch resistivity corresponds to dissolution of a substrate at a relatively low rate.
- the term "etch resistivity to an etchant” does not necessarily describe an intrinsic characteristic of a substrate or etchant, but rather describes an interaction between a particular substrate and a particular etchant.
- SiO 2 has a high etch resistivity to H 2 O, whereas the same material has a low etch resistivity towards HF.
- acetone is a strong etchant of polystyrene, but a weak etchant to SiO 2 .
- the term "etchant” refers to a reagent that is capable of dissolving, and/or chemical or physical degradation of a substrate.
- the etchant may be present in various forms, including a liquid, a mixture of liquids, a gas, ion plasma, or an electron beam.
- the line dielectric layer it is contemplated that various organic, silicon- containing, and inorganic low dielectric constant materials are suitable for the formation of the line dielectric, and preferred materials for the line dielectric include material comprising silicon oxide.
- preferred materials for the line dielectric include material comprising silicon oxide.
- various alternative low dielectric constant materials are also contemplated so long as the low dielectric constant material for the line dielectric has a lower etch resistivity toward an etchant than the hard mask layer.
- Inorganic low dielectric constant materials may be especially advantageous where higher temperature resistance of the dielectric material is desirable, where CVD deposition of the first low dielectric material is desired, or where applications demand an etchant that is derived from mixtures comprising fluorocarbons such as QFs/CO, or CF CHFs.
- contemplated inorganic materials include modified silicon dioxide and aluminum oxide.
- Organic materials may be especially desirable in applications where CVD deposition of the first low dielectric constant material is to be avoided, and particularly suitable organic materials include polyarylene ethers, polyarylenes, polyimides, and cyanate ester resins.
- organic materials are especially contemplated that can be applied onto a surface by various alternative methods, including spin-coating, dip coating, doctor-blading, etc.
- Other applications may favor organic materials that allow control over the degree of curing or crosslinking of the first low dielectric constant material. Therefore, low dielectric constant materials are especially contemplated that can be polymerized from monomers or block monomers, and/or crosslinked.
- contemplated materials include derivatized and underivatized polyarylenes, polyesters, polyimides, polybenzazoles, polyphenylenes, etc.
- Silicon-containing low dielectric materials are disclosed in commonly assigned US Patent 6,143,855 and include HOSPTM (spin-on hybrid siloxane-organic polymer, commercially available from Honeywell). It should also be recognized, that although the line dielectric layer preferably has a thickness of several thousand angstroms, the thickness of the line dielectric layer may vary considerably between approximately 50 angstrom or less, and several hundred micrometers.
- a thickness of approximately 100 angstrom may be sufficient.
- the minimum thickness may well exceed 8000 angstroms.
- the material chosen for the line dielectric layer generally dictates the particular method that is employed. Consequently, the line dielectric layer need not necessarily be laid down by LPCVD with TEOS as a source gas.
- various methods known in the art are also contemplated, including CVD, PVD, spin coating, dip coating, doctor-blading, and so forth. Spin coating may be especially advantageous when both the line dielectric and the hard mask layer are deposited by spin coating.
- the method of deposition of the hard mask material may vary among several applications and need not be limited to spin coating, as long as the low dielectric constant hard mask material is a liquid coated layer (i.e. is applied in a liquid phase).
- Contemplated methods may include roll coating, dip coating, spray coating, and so forth.
- other methods of application are also contemplated, including brushing or rinsing.
- solvents for applying the hard mask material include polar and apolar solvents, as well as protic and aprotic solvents.
- Polyperhydrosilazane is then deposited onto the silicon oxide layer from a 5% (by weight) solution in o-xylene by spin coating at 1000-4000rpm, and cured for approximately 120 minutes at 350°C to form a hard mask layer.
- the diffusion barrier layer is deposited onto the damascene structure from a 5% (by weight) polyperhydrosilazane solution in o-xylene by spin coating at 1000-4000rpm, and cured for approximately 60 minutes at 350°C.
- a dual damascene structure may comprise a line dielectric layer, an etch stop layer disposed on top of the line dielectric layer, a via dielectric layer disposed on top of the etch stop layer, and a hard mask layer, disposed on top of the via dielectric layer, wherein at least one of the etch stop layer and the hard mask layer is a liquid coated layer, and wherein at least one of the etch stop layer and the hard mask layer comprises silicon.
- both the etch stop layer and the hard mask layer may be a liquid coated layer, and the etch stop layer and the hard mask layer may comprise silicon.
- A may be a single atom, including O or S, but also a substituent comprising heteroatoms, including C, O, N, Halogens, etc. With respect to the molecular weight it is contemplated that appropriate substituents are less than 150Da. It is also contemplated that in complex polysilazanes no more than 6 atoms separate one silicon atom in one monomer from another silicon atom in another monomer. Especially preferred substituents may advantageously influence physico-chemical properties such as adhesion, low dielectric constant, or flame retardancy. Still further contemplated variations of simple and complex polysilazanes are described in U S.Pat. No. 5,459,114 to Kaya et al, and U.S.Pat. No. 5,905,130 to Nakahara et al, hereby incorporated by reference.
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Abstract
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA028142756A CN1754257A (en) | 2001-05-17 | 2002-05-17 | Layered hard mask and dielectric materials and methods therefor |
EP20020731865 EP1390976A1 (en) | 2001-05-17 | 2002-05-17 | Layered hard mask and dielectric materials and methods therefor |
JP2002590413A JP2004538624A (en) | 2001-05-17 | 2002-05-17 | Layered hard mask, dielectric material and method therefor |
KR10-2003-7014866A KR20040012833A (en) | 2001-05-17 | 2002-05-17 | Layered hard mask and dielectric materials and methods therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/860,993 US6656532B2 (en) | 2001-05-17 | 2001-05-17 | Layered hard mask and dielectric materials and methods therefor |
US09/860,993 | 2001-05-17 |
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Publication Number | Publication Date |
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WO2002093641A1 true WO2002093641A1 (en) | 2002-11-21 |
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PCT/US2002/015829 WO2002093641A1 (en) | 2001-05-17 | 2002-05-17 | Layered hard mask and dielectric materials and methods therefor |
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US (1) | US6656532B2 (en) |
EP (1) | EP1390976A1 (en) |
JP (1) | JP2004538624A (en) |
KR (1) | KR20040012833A (en) |
CN (1) | CN1754257A (en) |
WO (1) | WO2002093641A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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- 2002-05-17 EP EP20020731865 patent/EP1390976A1/en not_active Withdrawn
- 2002-05-17 CN CNA028142756A patent/CN1754257A/en active Pending
- 2002-05-17 WO PCT/US2002/015829 patent/WO2002093641A1/en not_active Application Discontinuation
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006517742A (en) * | 2003-01-29 | 2006-07-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Patterning layer made of spin-on ceramic film |
JP2006523954A (en) * | 2003-04-17 | 2006-10-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Multilayer cap barrier with microelectronic interconnect structure |
JP2006080359A (en) * | 2004-09-10 | 2006-03-23 | Toppan Printing Co Ltd | Method of manufacturing silicon nitride film, and method of forming pattern using silicon nitride film |
JP4517791B2 (en) * | 2004-09-10 | 2010-08-04 | 凸版印刷株式会社 | Pattern formation method using silicon nitride film |
Also Published As
Publication number | Publication date |
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US6656532B2 (en) | 2003-12-02 |
CN1754257A (en) | 2006-03-29 |
JP2004538624A (en) | 2004-12-24 |
EP1390976A1 (en) | 2004-02-25 |
US20020172898A1 (en) | 2002-11-21 |
KR20040012833A (en) | 2004-02-11 |
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