WO2002097863A2 - Method for manufacturing contacts for a chalcogenide memory device - Google Patents
Method for manufacturing contacts for a chalcogenide memory device Download PDFInfo
- Publication number
- WO2002097863A2 WO2002097863A2 PCT/US2002/016492 US0216492W WO02097863A2 WO 2002097863 A2 WO2002097863 A2 WO 2002097863A2 US 0216492 W US0216492 W US 0216492W WO 02097863 A2 WO02097863 A2 WO 02097863A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- conductive layer
- oxide layer
- oxide
- spacer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
Definitions
- the present invention relates to integrated circuits in general, and in particular to
- Chalcogenide memory devices Still more particularly, the present invention relates to a method for manufacturing contacts for a Chalcogenide memory device.
- phase change materials that can be electrically switched between a generally amorphous first structural state and a generally crystalline second structural state for electronic memory applications is well-known in the art. Phase change materials may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states.
- phase change materials exhibit different electrical characteristics according to their state.
- Chalcogenide materials exhibit a lower electrical conductivity in its amorphous state than it does in its crystalline state.
- the Chalcogenide materials for making memory cells are typically selected from the group of tellurium, selenium, antimony, and germanium. Such Chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods by using picojoules of energy. The resulting memory cell is truly non- volatile and will maintain the integrity of the stored information without the need for periodic signal refresh.
- Chalcogenide memory cells require that a region of the Chalcogenide memory material, called the Chalcogenide active region, be subjected to a current pulse with a current density typically between 10 5 and 10 6 amperes/cm 2 .
- a current pulse with a current density typically between 10 5 and 10 6 amperes/cm 2 .
- Such current density may be accomplished by making a small opening, such as a via or contact, in a dielectric material that is itself deposited onto a lower electrode material.
- the Chalcogenide material is then deposited over the dielectric material and into the via to contact with the lower electrode material.
- a top electrode material is then deposited over the Chalcogenide material.
- Carbon is a commonly used electrode material although other materials, such as molybdenum and titanium nitride, have also been used.
- the size of the Chalcogenide active region is primarily defined by the volume of Chalcogenide material that is contained within the via delineated by the opening in the dielectric material.
- the upper portion of the Chalcogenide material not contained within the via acts as an electrode that in turn contacts with the upper electrode material.
- Chalcogenide active region makes contact with the lower electrode at an interface area that is substantially equal to the cross sectional area of the via.
- the interface area of the Chalcogenide material within the Chalcogenide active region is subjected to the high current density required for the operation of the
- the switching voltages, currents, and powers of a Chalcogenide memory element are believed to be scalable with device size or contact area.
- the minimum achievable dimension of a contact for a small area Chalcogenide memory device is limited by lithography tools, which is approximately 0.15 um x 0.15 um. Such dimension will cause switching currents, voltages, and switching times to be too large and cycle life to be too small for integration with leading edge silicon semiconductor processing. Consequently, it is desirable to provide an improve method for manufacturing smaller contacts for a Chalcogenide memory device.
- a via is initially formed within a first oxide layer on a substrate.
- a conductive layer is then deposited on top of the first oxide layer.
- a second oxide layer is deposited on the conductive layer.
- the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer.
- a third oxide layer is deposited on the conductive layer, and the first and second oxide layers.
- a pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer.
- a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers.
- the nitride layer conforms with the contour of the third oxide layer.
- the third oxide layer is removed to expose the spacer.
- the conductive layer is then etched to remove a portion of the conductive layer not underneath the spacer. The portion of the conductive layer underneath the spacer resembles a matchstick.
- the spacer is then removed to expose the matchstick-like conductive layer portion with a small top surface contact area.
- a final oxide layer is deposited on the exposed matchstick-like conductor and surrounding oxide layer.
- a chemical-mechanical polishing process is used to remove the final oxide to a depth that exposes the small top area of the matchstick-like conductor.
- FIG. 1 is a block diagram of a Chalcogenide memory device, in accordance with a preferred embodiment of the present invention
- FIG. 2 is a circuit diagram of the memory matrix within the Chalcogenide memory device from Figure 1, in accordance with a preferred embodiment of the present invention
- FIGS 3a-31 are pictorial representations of a process for making a small contact within the Chalcogenide memory device from Figure 1, in accordance with a preferred embodiment of the present invention.
- Figure 4 is a high-level process flow diagram of a method for manufacturing the small contact from Figures 3 a-31, in accordance with a preferred embodiment of the present invention.
- a memory matrix 11 is formed on a substrate 10. Also formed on substrate 10 is an addressing matrix 12 that is suitably connected to memory matrix 11 through connections 13. Addressing matrix 12 preferably includes various signal generating means that control and read pulses applied to memory matrix 11.
- memory matrix 11 includes an x-y grid with each of memory cells 20 being connected in series with a diode 21 at the cross points of x address lines 22 and y address lines 23.
- Address lines 22 and 23 are separately connected to external addressing circuitry, such as addressing matrix 12 from Figure 1, in a manner that is well-known in the art.
- an N-well 31 is first formed within a single crystal P-doped silicon substrate 30 by diffusion in a manner well-known in the art.
- An P+ diffusion 32 is then formed within N-well 31 using well-known masking and doping techniques.
- a silicon dioxide (SiO 2 ) layer 33 is deposited on top of substrate 30.
- a contact or via 34 is formed, using well-known masking and etching techniques, within silicon dioxide layer 33, as shown in Figure 3a.
- a metal layer 35 is then deposited over silicon dioxide layer 33 via a chemical- vapor deposition (CVD) process.
- Metal layer 35 can be metal or polysilicon with a thickness of approximately 300 A.
- a second silicon dioxide layer 36 is deposited over metal layer 35, filling contact 34, as depicted in Figure 3b.
- a chemical mechanical polishing (CMP) process is then utilized to remove silicon dioxide layer 36 and metal layer 35 such that the remaining portion of metal layer 35 within contact 34 flushes with the surface of silicon dioxide layer 33, as illustrated in Figure 3c.
- CMP chemical mechanical polishing
- the remaining portion of metal layer 35 within contact 34 resembles a ring if view from the top.
- the cross-section view of the remaining portion of metal layer 35 within contact 34, as shown in Figure 3c, resembles a "cup.”
- cup conductor 35 the remaining portion of metal layer 35 within contact 34 is hereon referred to as cup conductor 35.
- a third silicon oxide layer 37 is then deposited on top of silicon dioxide layer 33 and cup conductor 35.
- a photomask and etch process is employed to remove a portion of layer 34 such that the remaining layer 37 covers approximately half of contact 34.
- Figure 3d is a top view of contact 34 illustrating half of contact 34 is covered by third silicon oxide layer 37. The cross-sectional view along line X — X in Figure 3d is depicted in Figure 3e.
- a silicon nitride (Si 3 N 4 ) layer 38 is deposited conformably on top of silicon dioxide layer 37 and cup conductor 35 (and also silicon dioxide layer 33) via a CVD process, as depicted in Figure 3f.
- Silicon nitride layer 38 is then removed from the top of silicon dioxide layer 37 and cup conductor 35 (and also silicon dioxide layer 33) using a directional etch process such as a reactive ion etching (RIE) process.
- RIE reactive ion etching
- a sidewall spacer of silicon nitride remains in every location at which a step has occurred in silicon dioxide layer 37, formed by the photomask and etch operation.
- a spacer 39 is formed at an edge of silicon dioxide layer 37 after the RIE process.
- cup conductor 35 are also etched. As a result, sidewall 39 and cup conductor 35 are exposed, resembling an "ear,” as depicted in Figure 3h. Spacer 39 is now free standing, straddling on top of cup conductor 35.
- cup conductor 35 is etched back to expose the original portion of cup conductor 35 under the sidewall nitride, as shown in Figure 3i.
- the etching is achieved using a directional or RIE etch process.
- Spacer 39 is then removed, and an extension of cup conductor 35 is exposed as a sidewall rapier contact having a dimension of the width of cup conductor 35 times the thickness of spacer 39.
- the width of cup conductor 35 is 30 nm and the thickness of spacer 39 is 20 nm, as shown in a perspective view of Figure 3j.
- a silicon oxide layer 60 is then deposited on top of cup conductor 35, conformably covering the matchstick portion of cup conductor 35, as shown in Figure 3k. Silicon oxide layer 60 is subsequently chemical mechanical polished back to the top of the matchstick portion of cup conductor 35, as illustrated in Figure 31. A 30 nm x 20 nm contact area 61 is now formed upon which Chalcogenide and contact metallurgy can be deposited.
- a via is initially formed within a first oxide layer on a substrate, as shown in block 41.
- a conductive layer is then deposited on top of the first oxide layer, as depicted in block 42.
- a second oxide layer is deposited on the conductive layer, as shown in block 43.
- the second oxide layer and the conductive layer are then removed, as depicted in block 44, such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer.
- a third oxide layer is deposited on the conductive layer, and the first and second oxide layers, as shown in block 45.
- a photomask and etch process are used to pattern an edge in the third oxide layer, so that the edge of the third oxide layer falls in a perpendicular manner across the conductive layer, as shown in 46.
- a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers, as depicted in block 47.
- the nitride layer conforms with the contour of the third oxide layer.
- the third oxide layer is removed to expose the spacer, as depicted in block 49.
- the conductive layer is then etched to expose a portion of the conductive layer underneath the spacer, as shown in block 50.
- the portion of the conductive layer underneath the spacer resembles a matchstick.
- the spacer is removed to expose the matchstick-like conductive layer portion, as depicted in block 51.
- an oxide layer is deposited on top of the conductive layer, conforming with the contour of the matchstick-like conductive layer portion, as shown in block 52.
- the oxide layer is chemical mechanical polished back to the top of the matchstick-like conductive layer portion to form a small contact, as depicted in block 53.
- the present invention provides an improved method for manufacturing contacts for a Chalcogenide memory device. Formation of a Chalcogenide memory element having a minimum cross-section area will provide lower switching voltages, currents, and switching times, longer cycle life, and better overall parameter control.
- the present invention uses a spacer technology approach, along with a poly or metal stick structure to form a sub-lithographic minimum memory cell. As a result, the cell contact area size is reduced to the width of the stick material times the thickness of the spacer. With the current processing technology, those dimensions should be approximately
Abstract
A first and second oxide layers and a conductive layer are deposited on a substrate with a via formedwithin the first oxide layer. The conductive layer and the second oxide layer are then removed suchthat the remaining portion of the conductive layer within the via flushes with a surface of the firstoxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxidelayers. A pattern is formed to remove third oxide layer so that the pattern opens orthgonally acrossand exposes the conductive layer. After depositing and directionally removing a nitride layer to forma spacer at the exposed edge of the third oxide layer, the third oxide layer is removed to expose thespacer. The conductive layer is then etched to remove a portion of the conductive layer notunderneath the spacer. The spacer is then removed to expose the matchstick-like conductive layerportion with a small top surface contact area.
Description
METHOD FORMANUFACTURING CONTACTS FORACHALCOGENIDE MEMORYDEVICE
This application claims priority from U.S. Patent Application No. 09/867,120 filed on May 29, 2001, and entitled "Method for Manufacturing Contacts for a Chalcogenide
Memory Device" which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Technical Field The present invention relates to integrated circuits in general, and in particular to
Chalcogenide memory devices. Still more particularly, the present invention relates to a method for manufacturing contacts for a Chalcogenide memory device.
2. Description of the Prior Art The use of phase change materials that can be electrically switched between a generally amorphous first structural state and a generally crystalline second structural state for electronic memory applications is well-known in the art. Phase change materials may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states.
Some phase change materials exhibit different electrical characteristics according to their state. For example, Chalcogenide materials exhibit a lower electrical conductivity in its amorphous state than it does in its crystalline state. The Chalcogenide materials for making memory cells are typically selected from the group of tellurium, selenium, antimony, and germanium. Such Chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods by using picojoules of energy. The resulting memory cell is truly non- volatile and will maintain the integrity of the stored information without the need for periodic signal refresh.
The operation of Chalcogenide memory cells requires that a region of the Chalcogenide memory material, called the Chalcogenide active region, be subjected to a
current pulse with a current density typically between 105 and 106 amperes/cm2. Such current density may be accomplished by making a small opening, such as a via or contact, in a dielectric material that is itself deposited onto a lower electrode material. The Chalcogenide material is then deposited over the dielectric material and into the via to contact with the lower electrode material. A top electrode material is then deposited over the Chalcogenide material. Carbon is a commonly used electrode material although other materials, such as molybdenum and titanium nitride, have also been used.
The size of the Chalcogenide active region is primarily defined by the volume of Chalcogenide material that is contained within the via delineated by the opening in the dielectric material. The upper portion of the Chalcogenide material not contained within the via acts as an electrode that in turn contacts with the upper electrode material. The
Chalcogenide active region makes contact with the lower electrode at an interface area that is substantially equal to the cross sectional area of the via. As a result of such configuration, the interface area of the Chalcogenide material within the Chalcogenide active region is subjected to the high current density required for the operation of the
Chalcogenide memory cell. This is an undesirable situation because the high current density at the interface area of the Chalcogenide active region with the lower electrode causes mixing of the lower electrode material with the Chalcogenide material of the Chalcogenide active region due to heating and electrophoretic effects. More specifically, the mixing of the electrode material with the Chalcogenide material in the Chalcogenide active region causes instability of the Chalcogenide memory cell during operation.
The switching voltages, currents, and powers of a Chalcogenide memory element are believed to be scalable with device size or contact area. With current semiconductor processing technology, the minimum achievable dimension of a contact for a small area Chalcogenide memory device is limited by lithography tools, which is approximately 0.15 um x 0.15 um. Such dimension will cause switching currents, voltages, and switching times to be too large and cycle life to be too small for integration with leading edge silicon semiconductor processing. Consequently, it is desirable to provide an improve method for manufacturing smaller contacts for a Chalcogenide memory device.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer.
Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer.
Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer. After directionally removing the nitride layer to form a spacer at the exposed edge of the third oxide layer, the third oxide layer is removed to expose the spacer. The conductive layer is then etched to remove a portion of the conductive layer not underneath the spacer. The portion of the conductive layer underneath the spacer resembles a matchstick. The spacer is then removed to expose the matchstick-like conductive layer portion with a small top surface contact area. A final oxide layer is deposited on the exposed matchstick-like conductor and surrounding oxide layer. A chemical-mechanical polishing process is used to remove the final oxide to a depth that exposes the small top area of the matchstick-like conductor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
Figure 1 is a block diagram of a Chalcogenide memory device, in accordance with a preferred embodiment of the present invention;
Figure 2 is a circuit diagram of the memory matrix within the Chalcogenide memory device from Figure 1, in accordance with a preferred embodiment of the present invention;
Figures 3a-31 are pictorial representations of a process for making a small contact within the Chalcogenide memory device from Figure 1, in accordance with a preferred embodiment of the present invention; and
Figure 4 is a high-level process flow diagram of a method for manufacturing the small contact from Figures 3 a-31, in accordance with a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Referring now to the drawings and in particular to Figure 1, there is illustrated a block diagram of a Chalcogenide memory device, in accordance with a preferred embodiment of the present invention. As shown, a memory matrix 11 is formed on a substrate 10. Also formed on substrate 10 is an addressing matrix 12 that is suitably connected to memory matrix 11 through connections 13. Addressing matrix 12 preferably includes various signal generating means that control and read pulses applied to memory matrix 11.
With reference now to Figure 2, there is illustrated a circuit diagram of memory matrix 11 , in accordance with a preferred embodiment of the present invention. As shown, memory matrix 11 includes an x-y grid with each of memory cells 20 being connected in series with a diode 21 at the cross points of x address lines 22 and y address lines 23. Address lines 22 and 23 are separately connected to external addressing circuitry, such as addressing matrix 12 from Figure 1, in a manner that is well-known in the art.
In order to manufacture a small contact within a memory cell 20 from Figure 2, an N-well 31 is first formed within a single crystal P-doped silicon substrate 30 by diffusion in a manner well-known in the art. An P+ diffusion 32 is then formed within N-well 31 using well-known masking and doping techniques. Next, a silicon dioxide (SiO2) layer 33 is deposited on top of substrate 30. A contact or via 34 is formed, using well-known masking and etching techniques, within silicon dioxide layer 33, as shown in Figure 3a.
A metal layer 35 is then deposited over silicon dioxide layer 33 via a chemical- vapor deposition (CVD) process. Metal layer 35 can be metal or polysilicon with a thickness of approximately 300 A. Afterwards, a second silicon dioxide layer 36 is deposited over metal layer 35, filling contact 34, as depicted in Figure 3b.
A chemical mechanical polishing (CMP) process is then utilized to remove silicon dioxide layer 36 and metal layer 35 such that the remaining portion of metal layer 35 within contact 34 flushes with the surface of silicon dioxide layer 33, as illustrated in Figure 3c.
At this point, the remaining portion of metal layer 35 within contact 34 resembles a ring if view from the top. The cross-section view of the remaining portion of metal layer 35 within contact 34, as shown in Figure 3c, resembles a "cup." Thus, for the convenience of naming, the remaining portion of metal layer 35 within contact 34 is hereon referred to as cup conductor 35.
A third silicon oxide layer 37, preferably 50nm -lOOnm thick, is then deposited on top of silicon dioxide layer 33 and cup conductor 35. A photomask and etch process is employed to remove a portion of layer 34 such that the remaining layer 37 covers approximately half of contact 34. Figure 3d is a top view of contact 34 illustrating half of contact 34 is covered by third silicon oxide layer 37. The cross-sectional view along line X — X in Figure 3d is depicted in Figure 3e.
Next, a silicon nitride (Si3N4) layer 38, preferably 20nm - 30nm thick, is deposited conformably on top of silicon dioxide layer 37 and cup conductor 35 (and also silicon dioxide layer 33) via a CVD process, as depicted in Figure 3f. Silicon nitride layer 38 is then removed from the top of silicon dioxide layer 37 and cup conductor 35 (and also silicon dioxide layer 33) using a directional etch process such as a reactive ion etching (RIE) process. A sidewall spacer of silicon nitride remains in every location at which a step has occurred in silicon dioxide layer 37, formed by the photomask and etch operation. As shown in Figure 3g, a spacer 39 is formed at an edge of silicon dioxide layer 37 after the RIE process.
An additional oxide etch is then performed to remove the remaining portion of silicon dioxide layer 37 adjacent to spacer 39. The exposed portion of oxide layers 33 and
34 are also etched. As a result, sidewall 39 and cup conductor 35 are exposed, resembling an "ear," as depicted in Figure 3h. Spacer 39 is now free standing, straddling on top of cup conductor 35.
Next, approximately 50nm - 100 nm of cup conductor 35 is etched back to expose the original portion of cup conductor 35 under the sidewall nitride, as shown in Figure 3i. The etching is achieved using a directional or RIE etch process.
Spacer 39 is then removed, and an extension of cup conductor 35 is exposed as a sidewall rapier contact having a dimension of the width of cup conductor 35 times the thickness of spacer 39. In this example, the width of cup conductor 35 is 30 nm and the thickness of spacer 39 is 20 nm, as shown in a perspective view of Figure 3j.
A silicon oxide layer 60, preferably 200 nm - 250 nm thick, is then deposited on top of cup conductor 35, conformably covering the matchstick portion of cup conductor 35, as shown in Figure 3k. Silicon oxide layer 60 is subsequently chemical mechanical polished back to the top of the matchstick portion of cup conductor 35, as illustrated in Figure 31. A 30 nm x 20 nm contact area 61 is now formed upon which Chalcogenide and contact metallurgy can be deposited.
With reference now to Figure 4, there is depicted a high-level process flow diagram of a method for manufacturing the contact from Figures 3a-31, in accordance with a preferred embodiment of the present invention. Starting at block 40, a via is initially formed within a first oxide layer on a substrate, as shown in block 41. A conductive layer is then deposited on top of the first oxide layer, as depicted in block 42. A second oxide layer is deposited on the conductive layer, as shown in block 43. Subsequently, the second oxide layer and the conductive layer are then removed, as depicted in block 44, such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers, as shown in block 45.
A photomask and etch process are used to pattern an edge in the third oxide layer, so that the edge of the third oxide layer falls in a perpendicular manner across the conductive layer, as shown in 46. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers, as depicted in block 47. The nitride layer conforms with the contour of the third oxide layer. After directionally removing the nitride layer to form a spacer at an edge of the third oxide layer, as shown in block 48, the third oxide layer is removed to expose the spacer, as depicted in block 49.
The conductive layer is then etched to expose a portion of the conductive layer underneath the spacer, as shown in block 50. The portion of the conductive layer underneath the spacer
resembles a matchstick. Next, the spacer is removed to expose the matchstick-like conductive layer portion, as depicted in block 51. Subsequently, an oxide layer is deposited on top of the conductive layer, conforming with the contour of the matchstick-like conductive layer portion, as shown in block 52. Finally, the oxide layer is chemical mechanical polished back to the top of the matchstick-like conductive layer portion to form a small contact, as depicted in block 53.
As has been described, the present invention provides an improved method for manufacturing contacts for a Chalcogenide memory device. Formation of a Chalcogenide memory element having a minimum cross-section area will provide lower switching voltages, currents, and switching times, longer cycle life, and better overall parameter control. The present invention uses a spacer technology approach, along with a poly or metal stick structure to form a sub-lithographic minimum memory cell. As a result, the cell contact area size is reduced to the width of the stick material times the thickness of the spacer. With the current processing technology, those dimensions should be approximately
30nm x 30nm, or smaller.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims
1. A method for manufacturing a small contact for a Chalcogenide memory device, said method comprising: forming a via within a first oxide layer on a substrate; depositing a conductive layer on top of said first oxide layer; depositing a second oxide layer on said conductive layer; removing said second oxide layer and said conductive layer such that the remaining portion of conductive layer within said contact flushes with a surface of said first oxide layer; depositing a third oxide layer on said conductive layer, and said first and second oxide layers; removing a portion of said third oxide layer to leave an edge of said third oxide layer essentially perpendicular to said conductive layer; depositing a nitride layer on said third oxide layer, said conductive layer, and said first and second oxide layers, wherein said nitride layer conforms with said third oxide layer; removing said nitride layer to form a spacer at an edge of said third oxide layer; removing said third oxide layer to expose said spacer; etching said conductive layer such that a portion of said conductive layer underneath said spacer is exposed, wherein said portion of said conductive layer underneath said spacer resembles a matchstick; and removing said spacer to expose said matchstick-like conductive layer portion as a small contact.
2. The method according to Claim 1, wherein said conductive layer is a metal layer.
3. The method according to Claim 1, wherein said conductive layer is a polysilicon layer.
4. The method according to Claim 1 , wherein said conductive layer is approximately 300 A thick.
5. The method according to Claim 1 , wherein said third oxide layer is approximately 50-100 nm thick.
6. The method according to Claim 1 , wherein said nitride layer is approximately 20-30 nm thick.
7. The method according to Claim 1, wherein said etching includes etching said conductive layer back 50-100 nm such that a portion of said conductive layer underneath said spacer is exposed.
8. The method according to Claim 1, wherein a width of said portion of said conductive layer is 30 nm and a length of said portion of said conductive layer is 20 nm.
9. The method according to Claim 1, wherein said method further include: depositing an oxide layer conformably over said match-stick conductive layer portion; and polishing said oxide layer to expose said matchstick-like conductive layer portion as said small contact.
10. The method according to Claim 9, wherein said oxide layer is silicon oxide layer.
11. The method according to Claim 9, wherein said oxide layer is approximately 200-
250 nm thick.
12. A contact for a Chalcogenide memory device, said contact comprising: a conductive layer having a protruded area; and a sidewall spacer resided on top of said protruded area of said conductive layer.
13. The contact according to Claim 12, wherein said conductive layer is a metal layer.
14. The contact according to Claim 12, wherein said conductive layer is a polysilicon layer.
15. The contact according to Claim 12, wherein said sidewall spacer is silicon nitride.
16. The contact according to Claim 12, wherein a cross-section dimension of said protracted area of said conductive layer is 20nm x 30nm.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/867,120 | 2001-05-29 | ||
US09/867,120 US6514788B2 (en) | 2001-05-29 | 2001-05-29 | Method for manufacturing contacts for a Chalcogenide memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002097863A2 true WO2002097863A2 (en) | 2002-12-05 |
WO2002097863A3 WO2002097863A3 (en) | 2003-11-06 |
Family
ID=25349122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/016492 WO2002097863A2 (en) | 2001-05-29 | 2002-05-24 | Method for manufacturing contacts for a chalcogenide memory device |
Country Status (2)
Country | Link |
---|---|
US (1) | US6514788B2 (en) |
WO (1) | WO2002097863A2 (en) |
Families Citing this family (161)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7365354B2 (en) * | 2001-06-26 | 2008-04-29 | Ovonyx, Inc. | Programmable resistance memory element and method for making same |
US6864503B2 (en) * | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US6856002B2 (en) * | 2002-08-29 | 2005-02-15 | Micron Technology, Inc. | Graded GexSe100-x concentration in PCRAM |
DE102004014487A1 (en) * | 2004-03-24 | 2005-11-17 | Infineon Technologies Ag | Memory device with embedded in insulating material, active material |
KR100568543B1 (en) * | 2004-08-31 | 2006-04-07 | 삼성전자주식회사 | Method of forming a phase change memory device having a small area of contact |
US7364935B2 (en) | 2004-10-29 | 2008-04-29 | Macronix International Co., Ltd. | Common word line edge contact phase-change memory |
US7279380B2 (en) * | 2004-11-10 | 2007-10-09 | Macronix International Co., Ltd. | Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method |
US7135727B2 (en) * | 2004-11-10 | 2006-11-14 | Macronix International Co., Ltd. | I-shaped and L-shaped contact structures and their fabrication methods |
US7608503B2 (en) * | 2004-11-22 | 2009-10-27 | Macronix International Co., Ltd. | Side wall active pin memory and manufacturing method |
US7220983B2 (en) * | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
US20060138467A1 (en) * | 2004-12-29 | 2006-06-29 | Hsiang-Lan Lung | Method of forming a small contact in phase-change memory and a memory cell produced by the method |
US7709334B2 (en) | 2005-12-09 | 2010-05-04 | Macronix International Co., Ltd. | Stacked non-volatile memory device and methods for fabricating the same |
US20060169968A1 (en) * | 2005-02-01 | 2006-08-03 | Thomas Happ | Pillar phase change memory cell |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7514367B2 (en) * | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Method for manufacturing a narrow structure on an integrated circuit |
US7534647B2 (en) | 2005-06-17 | 2009-05-19 | Macronix International Co., Ltd. | Damascene phase change RAM and manufacturing method |
US7514288B2 (en) * | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Manufacturing methods for thin film fuse phase change ram |
US7238994B2 (en) | 2005-06-17 | 2007-07-03 | Macronix International Co., Ltd. | Thin film plate phase change ram circuit and manufacturing method |
US7321130B2 (en) | 2005-06-17 | 2008-01-22 | Macronix International Co., Ltd. | Thin film fuse phase change RAM and manufacturing method |
US8237140B2 (en) * | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7598512B2 (en) * | 2005-06-17 | 2009-10-06 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation layer and manufacturing method |
US7397060B2 (en) * | 2005-11-14 | 2008-07-08 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US20070111429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US7450411B2 (en) | 2005-11-15 | 2008-11-11 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7635855B2 (en) | 2005-11-15 | 2009-12-22 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US7394088B2 (en) * | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7786460B2 (en) * | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7414258B2 (en) | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
US7323357B2 (en) * | 2005-11-17 | 2008-01-29 | Qimonda Ag | Method for manufacturing a resistively switching memory cell and memory device based thereon |
DE102005054931B3 (en) * | 2005-11-17 | 2007-07-26 | Infineon Technologies Ag | Resistive circuit switching storage cell production method, involves producing two slat shaped spacers, where former slat shaped shaper is electrically connected with phase change material |
US7479649B2 (en) | 2005-11-21 | 2009-01-20 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US7449710B2 (en) | 2005-11-21 | 2008-11-11 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7816661B2 (en) * | 2005-11-21 | 2010-10-19 | Macronix International Co., Ltd. | Air cell thermal isolation for a memory array formed of a programmable resistive material |
US7829876B2 (en) * | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
US7507986B2 (en) | 2005-11-21 | 2009-03-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US7599217B2 (en) | 2005-11-22 | 2009-10-06 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7459717B2 (en) | 2005-11-28 | 2008-12-02 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7521364B2 (en) | 2005-12-02 | 2009-04-21 | Macronix Internation Co., Ltd. | Surface topology improvement method for plug surface areas |
US7605079B2 (en) * | 2005-12-05 | 2009-10-20 | Macronix International Co., Ltd. | Manufacturing method for phase change RAM with electrode layer process |
US7642539B2 (en) * | 2005-12-13 | 2010-01-05 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation pad and manufacturing method |
GB2433647B (en) | 2005-12-20 | 2008-05-28 | Univ Southampton | Phase change memory materials, devices and methods |
US7531825B2 (en) * | 2005-12-27 | 2009-05-12 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US8062833B2 (en) * | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US7595218B2 (en) * | 2006-01-09 | 2009-09-29 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7741636B2 (en) * | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US20070158632A1 (en) * | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method for Fabricating a Pillar-Shaped Phase Change Memory Element |
US7560337B2 (en) * | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7825396B2 (en) * | 2006-01-11 | 2010-11-02 | Macronix International Co., Ltd. | Self-align planerized bottom electrode phase change memory and manufacturing method |
US7432206B2 (en) * | 2006-01-24 | 2008-10-07 | Macronix International Co., Ltd. | Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram |
US7456421B2 (en) | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
US7956358B2 (en) * | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
US7910907B2 (en) * | 2006-03-15 | 2011-03-22 | Macronix International Co., Ltd. | Manufacturing method for pipe-shaped electrode phase change memory |
US7554144B2 (en) * | 2006-04-17 | 2009-06-30 | Macronix International Co., Ltd. | Memory device and manufacturing method |
US7928421B2 (en) | 2006-04-21 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell with vacuum spacer |
US8129706B2 (en) * | 2006-05-05 | 2012-03-06 | Macronix International Co., Ltd. | Structures and methods of a bistable resistive random access memory |
US7608848B2 (en) * | 2006-05-09 | 2009-10-27 | Macronix International Co., Ltd. | Bridge resistance random access memory device with a singular contact structure |
US7423300B2 (en) | 2006-05-24 | 2008-09-09 | Macronix International Co., Ltd. | Single-mask phase change memory element |
US7820997B2 (en) * | 2006-05-30 | 2010-10-26 | Macronix International Co., Ltd. | Resistor random access memory cell with reduced active area and reduced contact areas |
US7732800B2 (en) * | 2006-05-30 | 2010-06-08 | Macronix International Co., Ltd. | Resistor random access memory cell with L-shaped electrode |
US7696506B2 (en) | 2006-06-27 | 2010-04-13 | Macronix International Co., Ltd. | Memory cell with memory material insulation and manufacturing method |
US7785920B2 (en) * | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7442603B2 (en) * | 2006-08-16 | 2008-10-28 | Macronix International Co., Ltd. | Self-aligned structure and method for confining a melting point in a resistor random access memory |
US7772581B2 (en) * | 2006-09-11 | 2010-08-10 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
US7504653B2 (en) * | 2006-10-04 | 2009-03-17 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US7510929B2 (en) * | 2006-10-18 | 2009-03-31 | Macronix International Co., Ltd. | Method for making memory cell device |
US7527985B2 (en) * | 2006-10-24 | 2009-05-05 | Macronix International Co., Ltd. | Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas |
US20080094885A1 (en) * | 2006-10-24 | 2008-04-24 | Macronix International Co., Ltd. | Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States |
US7863655B2 (en) * | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
US7388771B2 (en) | 2006-10-24 | 2008-06-17 | Macronix International Co., Ltd. | Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states |
US8067762B2 (en) * | 2006-11-16 | 2011-11-29 | Macronix International Co., Ltd. | Resistance random access memory structure for enhanced retention |
US20080137400A1 (en) * | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same |
US7682868B2 (en) | 2006-12-06 | 2010-03-23 | Macronix International Co., Ltd. | Method for making a keyhole opening during the manufacture of a memory cell |
US7476587B2 (en) * | 2006-12-06 | 2009-01-13 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7473576B2 (en) * | 2006-12-06 | 2009-01-06 | Macronix International Co., Ltd. | Method for making a self-converged void and bottom electrode for memory cell |
US7697316B2 (en) * | 2006-12-07 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level cell resistance random access memory with metal oxides |
US7903447B2 (en) * | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
US8344347B2 (en) * | 2006-12-15 | 2013-01-01 | Macronix International Co., Ltd. | Multi-layer electrode structure |
US7718989B2 (en) * | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7515461B2 (en) * | 2007-01-05 | 2009-04-07 | Macronix International Co., Ltd. | Current compliant sensing architecture for multilevel phase change memory |
US7433226B2 (en) | 2007-01-09 | 2008-10-07 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell |
US7440315B2 (en) | 2007-01-09 | 2008-10-21 | Macronix International Co., Ltd. | Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell |
US7535756B2 (en) | 2007-01-31 | 2009-05-19 | Macronix International Co., Ltd. | Method to tighten set distribution for PCRAM |
US7663135B2 (en) | 2007-01-31 | 2010-02-16 | Macronix International Co., Ltd. | Memory cell having a side electrode contact |
US7619311B2 (en) * | 2007-02-02 | 2009-11-17 | Macronix International Co., Ltd. | Memory cell device with coplanar electrode surface and method |
US7701759B2 (en) * | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7483292B2 (en) * | 2007-02-07 | 2009-01-27 | Macronix International Co., Ltd. | Memory cell with separate read and program paths |
US7463512B2 (en) * | 2007-02-08 | 2008-12-09 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
US8138028B2 (en) * | 2007-02-12 | 2012-03-20 | Macronix International Co., Ltd | Method for manufacturing a phase change memory device with pillar bottom electrode |
US7884343B2 (en) * | 2007-02-14 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory cell with filled sidewall memory element and method for fabricating the same |
US8008643B2 (en) * | 2007-02-21 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory cell with heater and method for fabricating the same |
US7619237B2 (en) * | 2007-02-21 | 2009-11-17 | Macronix International Co., Ltd. | Programmable resistive memory cell with self-forming gap |
US7956344B2 (en) * | 2007-02-27 | 2011-06-07 | Macronix International Co., Ltd. | Memory cell with memory element contacting ring-shaped upper end of bottom electrode |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US8610098B2 (en) | 2007-04-06 | 2013-12-17 | Macronix International Co., Ltd. | Phase change memory bridge cell with diode isolation device |
US7755076B2 (en) | 2007-04-17 | 2010-07-13 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
US7569844B2 (en) * | 2007-04-17 | 2009-08-04 | Macronix International Co., Ltd. | Memory cell sidewall contacting side electrode |
US7483316B2 (en) * | 2007-04-24 | 2009-01-27 | Macronix International Co., Ltd. | Method and apparatus for refreshing programmable resistive memory |
US8513637B2 (en) | 2007-07-13 | 2013-08-20 | Macronix International Co., Ltd. | 4F2 self align fin bottom electrodes FET drive phase change memory |
TWI402980B (en) | 2007-07-20 | 2013-07-21 | Macronix Int Co Ltd | Resistive memory structure with buffer layer |
US7884342B2 (en) * | 2007-07-31 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory bridge cell |
US7729161B2 (en) * | 2007-08-02 | 2010-06-01 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US9018615B2 (en) | 2007-08-03 | 2015-04-28 | Macronix International Co., Ltd. | Resistor random access memory structure having a defined small area of electrical contact |
US8178386B2 (en) | 2007-09-14 | 2012-05-15 | Macronix International Co., Ltd. | Phase change memory cell array with self-converged bottom electrode and method for manufacturing |
US7642125B2 (en) * | 2007-09-14 | 2010-01-05 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US7551473B2 (en) * | 2007-10-12 | 2009-06-23 | Macronix International Co., Ltd. | Programmable resistive memory with diode structure |
US7919766B2 (en) * | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US7804083B2 (en) * | 2007-11-14 | 2010-09-28 | Macronix International Co., Ltd. | Phase change memory cell including a thermal protect bottom electrode and manufacturing methods |
US7646631B2 (en) * | 2007-12-07 | 2010-01-12 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US7639527B2 (en) | 2008-01-07 | 2009-12-29 | Macronix International Co., Ltd. | Phase change memory dynamic resistance test and manufacturing methods |
US7879643B2 (en) * | 2008-01-18 | 2011-02-01 | Macronix International Co., Ltd. | Memory cell with memory element contacting an inverted T-shaped bottom electrode |
US7879645B2 (en) * | 2008-01-28 | 2011-02-01 | Macronix International Co., Ltd. | Fill-in etching free pore device |
US8158965B2 (en) | 2008-02-05 | 2012-04-17 | Macronix International Co., Ltd. | Heating center PCRAM structure and methods for making |
US8084842B2 (en) * | 2008-03-25 | 2011-12-27 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US8030634B2 (en) | 2008-03-31 | 2011-10-04 | Macronix International Co., Ltd. | Memory array with diode driver and method for fabricating the same |
US7825398B2 (en) | 2008-04-07 | 2010-11-02 | Macronix International Co., Ltd. | Memory cell having improved mechanical stability |
US7791057B2 (en) * | 2008-04-22 | 2010-09-07 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
US8077505B2 (en) * | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US7701750B2 (en) | 2008-05-08 | 2010-04-20 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
US8415651B2 (en) * | 2008-06-12 | 2013-04-09 | Macronix International Co., Ltd. | Phase change memory cell having top and bottom sidewall contacts |
US8134857B2 (en) * | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US20100019215A1 (en) * | 2008-07-22 | 2010-01-28 | Macronix International Co., Ltd. | Mushroom type memory cell having self-aligned bottom electrode and diode access device |
US7903457B2 (en) * | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7719913B2 (en) * | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US8324605B2 (en) * | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US7897954B2 (en) | 2008-10-10 | 2011-03-01 | Macronix International Co., Ltd. | Dielectric-sandwiched pillar memory device |
US8036014B2 (en) * | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US8907316B2 (en) * | 2008-11-07 | 2014-12-09 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions |
US8664689B2 (en) | 2008-11-07 | 2014-03-04 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions |
US7869270B2 (en) * | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US8089137B2 (en) * | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8107283B2 (en) * | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8064247B2 (en) * | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US8173987B2 (en) * | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8097871B2 (en) * | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US7933139B2 (en) * | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US7968876B2 (en) * | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8350316B2 (en) | 2009-05-22 | 2013-01-08 | Macronix International Co., Ltd. | Phase change memory cells having vertical channel access transistor and memory plane |
US8809829B2 (en) * | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8238149B2 (en) * | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8363463B2 (en) * | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8110822B2 (en) * | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8064248B2 (en) * | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8178387B2 (en) * | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US8987700B2 (en) | 2011-12-02 | 2015-03-24 | Macronix International Co., Ltd. | Thermally confined electrode for programmable resistance memory |
CN104966717B (en) | 2014-01-24 | 2018-04-13 | 旺宏电子股份有限公司 | A kind of storage arrangement and the method that the storage arrangement is provided |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9159412B1 (en) | 2014-07-15 | 2015-10-13 | Macronix International Co., Ltd. | Staggered write and verify for phase change memory |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6022815A (en) * | 1996-12-31 | 2000-02-08 | Intel Corporation | Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
WO2000057498A1 (en) * | 1999-03-25 | 2000-09-28 | Energy Conversion Devices, Inc. | Electrically programmable memory element with improved contacts |
US6150253A (en) * | 1996-10-02 | 2000-11-21 | Micron Technology, Inc. | Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same |
WO2002009206A1 (en) * | 2000-07-22 | 2002-01-31 | Ovonyx, Inc. | Electrically programmable memory element |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5851882A (en) * | 1996-05-06 | 1998-12-22 | Micron Technology, Inc. | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask |
-
2001
- 2001-05-29 US US09/867,120 patent/US6514788B2/en not_active Expired - Fee Related
-
2002
- 2002-05-24 WO PCT/US2002/016492 patent/WO2002097863A2/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150253A (en) * | 1996-10-02 | 2000-11-21 | Micron Technology, Inc. | Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same |
US6022815A (en) * | 1996-12-31 | 2000-02-08 | Intel Corporation | Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
WO2000057498A1 (en) * | 1999-03-25 | 2000-09-28 | Energy Conversion Devices, Inc. | Electrically programmable memory element with improved contacts |
WO2002009206A1 (en) * | 2000-07-22 | 2002-01-31 | Ovonyx, Inc. | Electrically programmable memory element |
Non-Patent Citations (1)
Title |
---|
MAIMON J ET AL: "Chalcogenide-based non-volatile memory technology" IEEE AEROSPACE CONFERENCE PROCEEDINGS, XX, XX, vol. 5, 10 March 2001 (2001-03-10), pages 2289-2294, XP010548238 * |
Also Published As
Publication number | Publication date |
---|---|
US20020182835A1 (en) | 2002-12-05 |
WO2002097863A3 (en) | 2003-11-06 |
US6514788B2 (en) | 2003-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6514788B2 (en) | Method for manufacturing contacts for a Chalcogenide memory device | |
US6815266B2 (en) | Method for manufacturing sidewall contacts for a chalcogenide memory device | |
US6514805B2 (en) | Trench sidewall profile for device isolation | |
US6605527B2 (en) | Reduced area intersection between electrode and programming element | |
US8242034B2 (en) | Phase change memory devices and methods for fabricating the same | |
US6114713A (en) | Integrated circuit memory cell having a small active area and method of forming same | |
US6287887B1 (en) | Method for fabricating a small area of contact between electrodes | |
US6927093B2 (en) | Method for making programmable resistance memory element | |
US8026505B2 (en) | Memory device | |
TWI415220B (en) | Buried silicide structure and method for making | |
US20100163828A1 (en) | Phase change memory devices and methods for fabricating the same | |
US7371604B2 (en) | Method of forming a contact structure | |
US7459764B2 (en) | Method of manufacture of a PCRAM memory cell | |
TWI291217B (en) | Phase change memory device and method of manufacturing | |
WO1998036446A9 (en) | A method for fabricating a small area of contact between electrodes | |
US20070145346A1 (en) | Connection electrode for phase change material, associated phase change memory element, and associated production process | |
KR101262580B1 (en) | Select devices including an open volume, memory devices and systems including same, and methods for forming same | |
JP2004128486A (en) | Manufacturing method of self-alignment cross point memory array | |
TWI269430B (en) | Trench capacitor of a DEAM memory cell with metallic collar region and nonmetallic buried strap to the select transistor | |
JP2006040981A (en) | High density soi crosspoint memory array and its manufacturing method | |
US20230397514A1 (en) | Tunable resistive random access memory cell | |
US20230180636A1 (en) | Suppression of void-formation of pcm materials |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: JP |