WO2002103584A3 - Phase and generator based soc design and/or verification - Google Patents

Phase and generator based soc design and/or verification Download PDF

Info

Publication number
WO2002103584A3
WO2002103584A3 PCT/US2002/017368 US0217368W WO02103584A3 WO 2002103584 A3 WO2002103584 A3 WO 2002103584A3 US 0217368 W US0217368 W US 0217368W WO 02103584 A3 WO02103584 A3 WO 02103584A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
verification
generation phase
phase
generator based
Prior art date
Application number
PCT/US2002/017368
Other languages
French (fr)
Other versions
WO2002103584A2 (en
Inventor
Michael Y Chen
Michael C Brouhard
John Wilson
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/132,020 external-priority patent/US20030009730A1/en
Priority claimed from US10/132,040 external-priority patent/US20030005396A1/en
Priority claimed from US10/132,587 external-priority patent/US6757882B2/en
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of WO2002103584A2 publication Critical patent/WO2002103584A2/en
Publication of WO2002103584A3 publication Critical patent/WO2002103584A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

Abstract

An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment , the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.
PCT/US2002/017368 2001-06-16 2002-05-31 Phase and generator based soc design and/or verification WO2002103584A2 (en)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US29877101P 2001-06-16 2001-06-16
US29875101P 2001-06-16 2001-06-16
US29877201P 2001-06-16 2001-06-16
US60/298,772 2001-06-16
US60/298,751 2001-06-16
US60/298,771 2001-06-16
US10/132,040 2002-04-24
US10/132,020 US20030009730A1 (en) 2001-06-16 2002-04-24 Enhanced platform based SOC design including exended peripheral selection and automated IP customization facilitation
US10/132,020 2002-04-24
US10/132,587 2002-04-24
US10/132,040 US20030005396A1 (en) 2001-06-16 2002-04-24 Phase and generator based SOC design and/or verification
US10/132,587 US6757882B2 (en) 2001-06-16 2002-04-24 Self-describing IP package for enhanced platform based SOC design

Publications (2)

Publication Number Publication Date
WO2002103584A2 WO2002103584A2 (en) 2002-12-27
WO2002103584A3 true WO2002103584A3 (en) 2004-08-12

Family

ID=27558143

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/017368 WO2002103584A2 (en) 2001-06-16 2002-05-31 Phase and generator based soc design and/or verification

Country Status (1)

Country Link
WO (1) WO2002103584A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0309528D0 (en) * 2003-04-25 2003-06-04 Beach Solutions Ltd Database population system
US7571414B2 (en) * 2006-06-15 2009-08-04 National Chip Implementation Center, National Applied Research Laboratories Multi-project system-on-chip and its method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
WO1999042930A2 (en) * 1998-02-20 1999-08-26 Lsi Logic Corporation Method and apparatus for logic synthesis
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
WO2001042969A2 (en) * 1999-12-03 2001-06-14 Synchronicity, Software, Inc. Ip library management system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
WO1999042930A2 (en) * 1998-02-20 1999-08-26 Lsi Logic Corporation Method and apparatus for logic synthesis
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
WO2001042969A2 (en) * 1999-12-03 2001-06-14 Synchronicity, Software, Inc. Ip library management system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BERGAMASCHI R ET AL: "Coral-automating the design of systems-on-chip using cores", PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE. (CICC 2000). ORLANDO, FL, MAY 21-24, 2000, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE.CICC, NEW YORK, NY: IEEE, US, vol. CONF. 22, 21 May 2000 (2000-05-21), pages 109 - 112, XP002186200, ISBN: 0-7803-5810-4 *

Also Published As

Publication number Publication date
WO2002103584A2 (en) 2002-12-27

Similar Documents

Publication Publication Date Title
WO2003054666A3 (en) System and method for automated test-case generation for software
EP1394674A3 (en) System and method for generating initial vectors
RU2008104404A (en) METHOD FOR PREVENTING REVERSE ENGINEERING OF SOFTWARE, UNAUTHORIZED MODIFICATION AND INTERCEPT OF DATA AT THE TIME OF PERFORMANCE
WO2002075336A3 (en) Test system algorithmic program generators
ATE305631T1 (en) PSEUDO RANDOM NUMBERS GENERATOR
CA2290170A1 (en) Improved digital signature
Muscalu et al. A counterexample to a multilinear endpoint question of Christ and Kiselev
WO2002103584A3 (en) Phase and generator based soc design and/or verification
DE60036928D1 (en) OPPOSITION METHOD IN AN ELECTRONIC COMPONENT FOR CARRYING OUT A CYCLONE ALGORITHM WITH SECRETARY KEY
Zhu et al. Counteracting leakage power analysis attack using random ring oscillators
Huang et al. Trace buffer attack on the AES cipher
Dufour et al. An induction machine and power electronic test system on a field-programmable gate array
JPH1130646A (en) Semiconductor integrated circuit and test circuit to be comprised therein
WO2005029676A3 (en) Methods and apparatuses for generating electrical power in a rotating reference frame
WO2006111950A3 (en) Improved cipher system
TWI229441B (en) Semiconductor integrated circuit and functional block thereof
DE60140671D1 (en) DATA PROCESSING BY KEY
Bharadwaj et al. A design pattern for symmetric encryption
Sodagar et al. Reduced-memory direct digital frequency synthesizer using parabolic initial guess
WO2002093749A3 (en) Method for generating an internal clock pulse in an electric circuit and a corresponding electric circuit comprising a central clock-pulse generator
WO2003005584A3 (en) Random generator description
Widhalm et al. Augmenting pre-silicon simulation by embedding a scripting language in a SystemC environment
JP2005508581A5 (en)
Kajtazovic et al. Automatic generation of a verification platform for heterogeneous system designs
WO2002091173A3 (en) Frameworks for efficient representation of string objects in java programming environments

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)