WO2003017541A1 - Variable size first in first out (fifo) memory with head and tail caching - Google Patents

Variable size first in first out (fifo) memory with head and tail caching Download PDF

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Publication number
WO2003017541A1
WO2003017541A1 PCT/US2002/025425 US0225425W WO03017541A1 WO 2003017541 A1 WO2003017541 A1 WO 2003017541A1 US 0225425 W US0225425 W US 0225425W WO 03017541 A1 WO03017541 A1 WO 03017541A1
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WO
WIPO (PCT)
Prior art keywords
memory
fifo
head
data
tail
Prior art date
Application number
PCT/US2002/025425
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French (fr)
Inventor
Chris Haywood
Original Assignee
Internet Machines Corporation
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Filing date
Publication date
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Publication of WO2003017541A1 publication Critical patent/WO2003017541A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/108—Reading or writing the data blockwise, e.g. using an extra end-of-block pointer

Definitions

  • the present invention is structured to a variable size First In First Out (FIFO) memory with head and tail caching.
  • FIFO First In First Out
  • FIFO First In First Out
  • a variable size first in first out (FIFO) memory comprising a head FIFO memory for sequentially delivering data packets at a relatively slow rate to a plurality of switching elements whereby some latency occurs between data packets.
  • a tail FIFO memory stores an overflow of the data packets from the head memory. Both the head and tail memories operate at a relatively high data rate equivalent to the data rate of incoming data packets.
  • a large capacity buffer memory is provided having an effectively lower clock rate than the FIFO memories for temporarily storing data overflow from the tail memory whereby the FIFO memories in combination with the buffer memory form a variable size FIFO memory.
  • Fig. 1 is a block diagram of a memory embodying the present invention.
  • Fig. 2 is a diagrammatic portion of Fig. 1 illustrating its operation.
  • Fig. 3 is a flow chart of the operation of Fig. 1.
  • a relatively high data rate of, for example 10 Gbps may be accomplished.
  • a plurality of switching elements SE0-SE7 which operate at a much lower data rate, for example 2.5 Gbps.
  • a high data rate may be maintained.
  • Data packets arrive from a receiver 11 which would have a communications processor coupled to it on line 12 at 10 Gbps and via the variable
  • FIFO memory illustrated at 13 FIFO being First In First Out memory.
  • Data packets are routed to a sequential sprinkler engine 14 and then distributed at the lower data rate to various switching elements.
  • a variable FIFO memory is required where a sudden burst of input data may occur which would temporarily overwhelm an individual FIFO memory without a large scale buffer memory (which it can be assumed has almost unlimited memory capacity since it is remote or off the same semiconductor chip as the high speed memory).
  • Fig. 2 illustrates where some latency may occur; in other words, there would not be a continuous serial transmission of the high speed data packets through to the switch elements.
  • the data packets 1, 2, 3 are indicated in a line of data being received.
  • the first data packet is routed to the switching element 7. After this operation is started,, a short time later is indicated by the time lapse ⁇ L data packet two is distributed by the sprinkler engine; and then data packet three at a later time t 2 .
  • Some latency occurs which must be compensated for by some type of buffer apparatus. This is provided by the overall variable FIFO memory which is a combination of a tail FIFO memory 16, a head FIFO memory 17 and the large scale off chip buffer memory 18.
  • Variable blocks of data are formed by a receiver 11 and transferred through the tail FIFO memory to the head FIFO memory 17 until it is filled.
  • the tail or FIFO 16 routes data to the head FIFO memory 17 which then distributes data packets to the various switching elements. If the head FIFO memory becomes full, the tail FIFO memory will start filling. The tail FIFO will buffer enough data to keep the head FIFO filled. If the tail FIFO fills due to a sudden burst, data is then written on the line of 21 to the large scale off chip memory 18. This data will be read from the large scale memory into the head FIFO when the head FIFO starts to empty.
  • tail FIFO 16 and head FIFO 17 are located on a common semiconductor substrate or chip with the large scale buffer memory 18 being remotely located off chip. This is indicated by the dash line 22.
  • the large scale off chip buffer memory 18 is utilized.
  • Uniform blocks of data are stored indicated by the dash line 23.
  • 128 bytes is transferred on the line 21 into the memory 18.
  • This memory also includes a similar block size of 128 bytes.
  • optimization of the bus width in all of the FIFO and buffer memories provide, in effect, a 100 percent efficient transfer technique since for every clock cycle a maximum number of bits is transferred.
  • buffer memory 18 has a lower clock rate and therefore wider bus. In the present application this could be two read and two write cycles.
  • the various write pointers and read pointers (WP and RP) are so indicated on the various memories and the overall control is accomplished by the memory controller 26.
  • a multiplexer 27 connected to memory controller 26 provides for control of the various data routings. When a sudden burst of data packets ceases, the FIFO memory can then return to its ordinary mode of operation where the head FIFO memory 17 contains all of the inputted data packets as delivered by the tail FIFO memory.
  • step 41 the head FIFO memory is filled, and in step 42 if the head FIFO overflows, the tail FIFO memory is filled. Then in step 43 again when the tail FIFO is filled, data is stored in the buffer memory until the head FIFO begins to empty.
  • memory controller 26 monitors the FIFO depth and determines if a block of data needs to be stored to off chip memory. It also keeps track of how many blocks are written. As the FIFO memories empty, the memory controller is responsible for arbitrating and retrieving any stored blocks of data.
  • the larger external buffer memory 18 can be provisioned, using one of many allocation schemes, to support multiple head and tail FIFOs in the same manner as described.
  • variable FIFO memory with head and tail caching has been provided.

Abstract

A variable size FIFO memory (13) is provided by the use of head (17) and tail (16) FIFO memories operating at a very high data rate and then an off chip buffer memory (18), for example, of a dynamic RAM type, which temporarily stores data packets when both head (17) and tail (16) FIFO memories are filled. Data blocks of each of the memories are the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head (17) and tail (16) FIFO memories return to the initial functions with the head memory directly receiving high speed data and transmitting it to various switching elements and the tails (16) FIFO memory stores temporary overflows of data from the head (17) FIFO memory.

Description

VARIABLE SIZE FIRST IN FIRST OUT (FIFO) MEMORY WITH HEAD AND TAIL CACHING
The present invention is structured to a variable size First In First Out (FIFO) memory with head and tail caching.
BACKGROUND OF THE INVENTION
Communications networks now require handling of data at very high serial data rates. For example, 10 gigabits per second (Gbps) is common. When it is required to process at these speeds, high speed data parallel connections are used to increase the effective bandwidth. This may be unsatisfactory because of the resultant decrease in bandwidth due to increased overhead requirements. There is a need for effective high speed switching apparatus and the associated hardware to support such a apparatus.
OBJECT AND SUMMARY OF INVENTION
It is therefore an object of the present invention to provide a variable size First In First Out (FIFO) memory.
In accordance with the above object, there is provided a variable size first in first out (FIFO) memory comprising a head FIFO memory for sequentially delivering data packets at a relatively slow rate to a plurality of switching elements whereby some latency occurs between data packets. A tail FIFO memory stores an overflow of the data packets from the head memory. Both the head and tail memories operate at a relatively high data rate equivalent to the data rate of incoming data packets. A large capacity buffer memory is provided having an effectively lower clock rate than the FIFO memories for temporarily storing data overflow from the tail memory whereby the FIFO memories in combination with the buffer memory form a variable size FIFO memory. BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 is a block diagram of a memory embodying the present invention. Fig. 2 is a diagrammatic portion of Fig. 1 illustrating its operation. Fig. 3 is a flow chart of the operation of Fig. 1.
DETAILED DESCRDPTION OF PREFERRED EMBODIMENT
As disclosed in a co-pending application entitled High Speed Channels Using Multiple Parallel Lower Speed Channels attorney docket 0679/13 switching of input data arriving at a relatively high data rate of, for example 10 Gbps, may be accomplished. As illustrated in Fig. 1 a plurality of switching elements SE0-SE7 which operate at a much lower data rate, for example 2.5 Gbps. By the use of a sequential or successive sprinkling technique for complete data packets a high data rate may be maintained. Data packets arrive from a receiver 11 which would have a communications processor coupled to it on line 12 at 10 Gbps and via the variable
FIFO memory illustrated at 13, FIFO being First In First Out memory. Data packets are routed to a sequential sprinkler engine 14 and then distributed at the lower data rate to various switching elements. In general, a variable FIFO memory is required where a sudden burst of input data may occur which would temporarily overwhelm an individual FIFO memory without a large scale buffer memory (which it can be assumed has almost unlimited memory capacity since it is remote or off the same semiconductor chip as the high speed memory).
Fig. 2 illustrates where some latency may occur; in other words, there would not be a continuous serial transmission of the high speed data packets through to the switch elements. Thus the data packets 1, 2, 3 are indicated in a line of data being received. The first data packet is routed to the switching element 7. After this operation is started,, a short time later is indicated by the time lapse \L data packet two is distributed by the sprinkler engine; and then data packet three at a later time t2. Some latency occurs which must be compensated for by some type of buffer apparatus. This is provided by the overall variable FIFO memory which is a combination of a tail FIFO memory 16, a head FIFO memory 17 and the large scale off chip buffer memory 18. Variable blocks of data are formed by a receiver 11 and transferred through the tail FIFO memory to the head FIFO memory 17 until it is filled. Thus, the tail or FIFO 16 routes data to the head FIFO memory 17 which then distributes data packets to the various switching elements. If the head FIFO memory becomes full, the tail FIFO memory will start filling. The tail FIFO will buffer enough data to keep the head FIFO filled. If the tail FIFO fills due to a sudden burst, data is then written on the line of 21 to the large scale off chip memory 18. This data will be read from the large scale memory into the head FIFO when the head FIFO starts to empty.
From a practical standpoint to operate at the data rate of 10 Gbps, tail FIFO 16 and head FIFO 17 are located on a common semiconductor substrate or chip with the large scale buffer memory 18 being remotely located off chip. This is indicated by the dash line 22. When the tail FIFO memory becomes full then the large scale off chip buffer memory 18 is utilized. Uniform blocks of data are stored indicated by the dash line 23. For example, 128 bytes is transferred on the line 21 into the memory 18. This memory also includes a similar block size of 128 bytes. For example, line 21 may have a 64 bit width (meaning eight bytes) and thus, the data block of 128 bytes is transferred in 16 clock cycles (16x64=128 bytes). Optimization of the bus width in all of the FIFO and buffer memories provide, in effect, a 100 percent efficient transfer technique since for every clock cycle a maximum number of bits is transferred. However buffer memory 18 has a lower clock rate and therefore wider bus. In the present application this could be two read and two write cycles. The various write pointers and read pointers (WP and RP) are so indicated on the various memories and the overall control is accomplished by the memory controller 26. A multiplexer 27 connected to memory controller 26 provides for control of the various data routings. When a sudden burst of data packets ceases, the FIFO memory can then return to its ordinary mode of operation where the head FIFO memory 17 contains all of the inputted data packets as delivered by the tail FIFO memory. Of course, this doesn't occur until the large scale off chip buffer memory 18 is unloaded. The foregoing operation is shown in a flow chart of Fig. 3. In step 41 the head FIFO memory is filled, and in step 42 if the head FIFO overflows, the tail FIFO memory is filled. Then in step 43 again when the tail FIFO is filled, data is stored in the buffer memory until the head FIFO begins to empty. In general, memory controller 26 monitors the FIFO depth and determines if a block of data needs to be stored to off chip memory. It also keeps track of how many blocks are written. As the FIFO memories empty, the memory controller is responsible for arbitrating and retrieving any stored blocks of data.
The larger external buffer memory 18 can be provisioned, using one of many allocation schemes, to support multiple head and tail FIFOs in the same manner as described.
Thus a variable FIFO memory with head and tail caching has been provided.

Claims

CLAIMS:
1. A variable size first in first out (FIFO) memory comprising: a head FIFO memory for sequentially delivering data packets at a relatively slow rate to a plurality of switching elements whereby some latency occurs between data packets: a tail FIFO memory for storing an overflow of said data packets from said head memory; both said head and tail memories operating at a relatively high , data rate equivalent to the rate of incoming data packets; a large capacity buffer memory having an effectively lower clock rate than said FIFO memories for temporarily storing data overflow from said tail memory whereby said FIFO memories in combination with said buffer memory for a variable size FIFO memory.
2. A memory as in claim 1 where said head and tail memories have data blocks of a predetermined and same size and said buffer memory has the same size data block whereby high efficiency data transfer between memories is obtained.
3. A memory as in claim 1 where FIFO memories reside on a common semiconductor substrate and said buffer memory is remote.
4. A memory as in Claim 1 where said buffer memory has a wider bus than said head and tail FIFO memories.
PCT/US2002/025425 2001-08-15 2002-08-09 Variable size first in first out (fifo) memory with head and tail caching WO2003017541A1 (en)

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US20060072598A1 (en) 2006-04-06
US6987775B1 (en) 2006-01-17
US20030037210A1 (en) 2003-02-20
US6941426B2 (en) 2005-09-06
US7639707B2 (en) 2009-12-29
US20050265357A1 (en) 2005-12-01

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