WO2003019351A3 - Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability - Google Patents

Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability Download PDF

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Publication number
WO2003019351A3
WO2003019351A3 PCT/US2002/026516 US0226516W WO03019351A3 WO 2003019351 A3 WO2003019351 A3 WO 2003019351A3 US 0226516 W US0226516 W US 0226516W WO 03019351 A3 WO03019351 A3 WO 03019351A3
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WO
WIPO (PCT)
Prior art keywords
data rate
sdr
ddr
read
write
Prior art date
Application number
PCT/US2002/026516
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French (fr)
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WO2003019351A2 (en
Inventor
Jiann-Jeng Duh
Mario Fulam Au
Original Assignee
Integrated Device Tech
Jiann-Jeng Duh
Mario Fulam Au
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Device Tech, Jiann-Jeng Duh, Mario Fulam Au filed Critical Integrated Device Tech
Priority to EP02753502A priority Critical patent/EP1419433A2/en
Publication of WO2003019351A2 publication Critical patent/WO2003019351A2/en
Publication of WO2003019351A3 publication Critical patent/WO2003019351A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/062—Allowing rewriting or rereading data to or from the buffer

Abstract

First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation circuitry and retransmit circuitry are also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.
PCT/US2002/026516 2001-08-23 2002-08-20 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability WO2003019351A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP02753502A EP1419433A2 (en) 2001-08-23 2002-08-20 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US31439301P 2001-08-23 2001-08-23
US60/314,393 2001-08-23
US09/972,265 2001-10-05
US09/972,265 US6795360B2 (en) 2001-08-23 2001-10-05 Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes

Publications (2)

Publication Number Publication Date
WO2003019351A2 WO2003019351A2 (en) 2003-03-06
WO2003019351A3 true WO2003019351A3 (en) 2004-02-19

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Application Number Title Priority Date Filing Date
PCT/US2002/026516 WO2003019351A2 (en) 2001-08-23 2002-08-20 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability

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US (3) US6795360B2 (en)
EP (1) EP1419433A2 (en)
CN (1) CN100419667C (en)
WO (1) WO2003019351A2 (en)

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Also Published As

Publication number Publication date
CN100419667C (en) 2008-09-17
US6795360B2 (en) 2004-09-21
CN1571951A (en) 2005-01-26
US6778454B2 (en) 2004-08-17
US7158440B2 (en) 2007-01-02
WO2003019351A2 (en) 2003-03-06
US20050041450A1 (en) 2005-02-24
US20030206475A1 (en) 2003-11-06
US20030112685A1 (en) 2003-06-19
EP1419433A2 (en) 2004-05-19

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