WO2003021492A2 - Simulating a logic design - Google Patents
Simulating a logic design Download PDFInfo
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- WO2003021492A2 WO2003021492A2 PCT/US2002/026852 US0226852W WO03021492A2 WO 2003021492 A2 WO2003021492 A2 WO 2003021492A2 US 0226852 W US0226852 W US 0226852W WO 03021492 A2 WO03021492 A2 WO 03021492A2
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- logic
- state
- code
- computer code
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Definitions
- This invention relates to simulating a logic design comprised of combinatorial logic and state logic.
- Logic designs for computer chips typically include combinatorial elements and state elements.
- Combinatorial elements such as AND gates and OR gates, combine two or more logic states to produce an output.
- State elements such as latches and flip-flops (FFs) , hold a logic state for a period of time, usually until receipt of an external clock signal .
- Computer languages exist which allow designers to simulate logic designs, including combinatorial and state elements, prior to forming the logic on silicon. Examples of such languages include Verilog and Very High-Level Design Language (VHDL) . Using these languages, a designer can write code to simulate a logic design, then execute the code in order to determine if the logic design performs properly.
- VHDL Very High-Level Design Language
- Standard computer languages may also be used to simulate a logic design.
- Fig. 1 is a flowchart showing a process for generating simulation code for a logic design.
- Fig. 2 is a block diagram of a logic design containing individual state and combinatorial elements .
- Fig. 3 is a block diagram of an alternative logic design containing state and combinatorial elements .
- Fig. 4 shows a logic cone
- Fig. 5 shows clock domains of a logic design.
- Fig. 6 is a block diagram of an alternative logic design containing state and combinatorial elements.
- Fig. 7 is a block diagram of a computer system on which the process of Fig. 1 may be performed.
- a process 10 is shown for simulating a logic design comprised of combinatorial logic and state logic.
- Process 10 may be implemented using a computer program running on a computer or other type of machine, as described in more detail below.
- process 10 selects (101) , in response to a logic designer's input, graphic elements to generate a block diagram representation of a logic design.
- the graphics elements are selected from a graphics library and may include combinatorial logic and state logic elements .
- Graphics elements in the library may be definable or may have predefined functions.
- the library may contain software objects that perform the function of a flip flop (FF) or a latch.
- the library may also contain graphics elements that are undefined, i.e., that have no code associated with them.
- FIG. 2 shows a graphical representation of a logic design 12 containing combinatorial logic elements 14 to 19 and state logic elements 22 and 24.
- each block represents a single combinatorial element (e.g., multiplexers 18 and 19) or state element (e.g., FFs 22 and 24) .
- state element e.g., FFs 22 and 24
- logic design 26 Fig. 3
- the functionality of several combinatorial elements is contained in a single combinatorial block 28 and the function of several state elements is contained in a single state block 30.
- process 10 performs (102) an error check on the design to determine if there are any problems with the design. For example, process 10 determines if there are any unterminated or inconsistent connections in the design. If any such problems are detected (103) , process 10 issues (104) an error message to the logic designer. The error message may specify the nature of the problem and its location within the logic design. The logic designer is then given the opportunity to correct the problem before process 10 moves forward.
- process 10 associates (105) computer code that simulates the logic design with each of the graphic elements.
- process 10 associates computer code with combinatorial logic element 28 to define its function and with state logic element 30 to define its function. The same is true for the logic elements of Fig. 2.
- the computer code is generated as follows.
- Process 10 receives (106) intermediate computer code that is written by the logic designer.
- the computer code is "intermediate" in the sense that it is an application- specific code, from which simulation code, such as C++ or Verilog, may be generated.
- the intermediate computer code includes a netlist that defines logic elements and the interconnections of those elements .
- the intermediate code is entered by the designer for each graphic element.
- the designer may select a graphic element and, using an interactive tool, enter computer code to define the combinatorial (or state) logic represented by that element.
- the designer may use software objects from the library, such as FFs, latches, AND gates, etc., in the intermediate code.
- FFs FFs
- latches AND gates, etc.
- Several objects may be combined within a single graphic element by writing intermediate computer code to effect the combination.
- an array of FFs may be produced by combining objects from the library via the intermediate code.
- Graphic element 30 (Fig. 3) contains such an array of FFs.
- the logic designer is constrained by process 10 to represent combinatorial logic and state logic using separate graphic elements .
- process 10 performs (107) an error check to determine if the intermediate code written by the designer includes state logic in combinatorial graphic elements, or vice versa. If a state logic element contains combinatorial logic or a combinatorial logic element contains state logic, process 10 issues (108) an error message to the designer.
- the error message may define the problem (i.e., interleaved combinatorial and state logic) and the graphic element that contains the problem.
- process 10 requires the designer to correct the problem before process 10 proceeds further. To correct such a problem, the logic designer places the combinatorial logic and the state logic in different graphic elements (i.e., blocks) .
- process 10 generates simulation code for the design.
- process 10 generates either Verilog computer code or C++ computer code from the intermediate computer code.
- the simulation code is not limited to generating only these two types of simulation code. Any other type of suitable code, an example of which is VHDL, may be generated.
- GUI graphical user interface
- logic simulations include cycle-based simulations and event-driven simulations.
- An event-driven simulation converges on an output of the logic design through multiple cycles. Convergence requires several passes through "logic cones" defined by the computer code .
- a logic cone 32 is an ordered arrangement in which one logic element 34 passes its output 36 to multiple logic elements 38, which, in turn, pass their outputs 40 to other logic elements 42, and so on. Combining state and combinatorial logic elements within a single logic cone requires multiple passes (iterations) through that cone in order for the state elements to achieve the appropriate states and thus provide the proper output.
- cycle-based simulations assume that the computer code is ordered correctly, meaning that each logic cone can be traced, with only one iteration, to provide an output. Thus, cycle-based simulations require only a single pass through a logic cone in order to determine its output. As a result, cycle-based simulators are faster, e.g., an order of magnitude faster, than event-driven simulators
- cycle-based simulators require only one pass, versus multiple passes, through a logic cone
- a platform such as an Intel® Pentium® III microprocessor running at 700 MHz (megahertz)
- simulating 100 cycles of a complex logic design with an event-driven model might take 10 seconds, whereas performing the same simulation using a cycle-based simulator might take 1 second.
- cycle-based simulations are generally preferred over event-driven simulations. Since separating the combinatorial logic from the state logic facilitates cycle-based simulations, process 10 provides a significant advantage to logic designers.
- process 10 decides (109) whether to generate C++ simulation code or Verilog simulation code from the intermediate computer code. This decision (109) is typically made based on an input from the logic designer. If process 10 decides (109) that Verilog code is to be generated, process 10 generates (110) the Verilog code from the intermediate code.
- the Verilog code may be generated from the intermediate code using a translator program (not shown) and a database (not shown) that correlates the connections defined by the intermediate code to Verilog code. Parameters or values in the intermediate code are identified and input to the Verilog code .
- process 10 runs (111) the Verilog code through an event- driven simulator program.
- the event-driven simulator program runs, and provides inputs (e.g., clock signals), to the Verilog code to generate a simulation of the operation of the logic design.
- inputs e.g., clock signals
- process 10 runs (111) the Verilog code through an event- driven simulator program.
- the event-driven simulator program runs, and provides inputs (e.g., clock signals), to the Verilog code to generate a simulation of the operation of the logic design.
- inputs e.g., clock signals
- process 10 decides (109) to generate C++ code from the intermediate code (based, e.g., on an input from the logic designer) , process 10 generates (112a) a topology of each graphic element of the logic design based on the intermediate code.
- process 10 traces the logic gates through the intermediate code for each graphic element in order to determine how the logic gates are connected to one another. Essentially, process 10 obtains a gate topology from the intermediate code.
- Process 10 identifies (113) clock domains in the topology.
- a clock domain comprises a set of logic elements (gates) that are triggered in response to the same clock pulse. For example, referring to Fig.
- logic gates 50 to 60 are all triggered in response to clock pulse 62, which is initially applied to logic gates 50, 51.
- the intermediate code provided by the designer indicates which clock pulses trigger which logic gates.
- process 10 traces clock pulses through the logic gates in order to identify the clock domains. Once the clock domains are identified, process 10 determines (114a) the order in which the logic gates are to be simulated. This is referred to as "code ordering", since the order in which the gates are simulated dictates the order of the resulting C++ code.
- Process 10 performs code ordering by tracing through each clock domain separately and assigning numerical values to the logic gates.
- each clock domain 64, 66, 68 can be thought of as a tree having a trunk 70 and branches 72.
- Process 10 starts at the trunk, in this case logic gate 50, and traverses the tree through to the end of each branch. So, process 10 numbers the trunk (gate 50) "1", then, for branch 74, numbers gate 52 "2", gate 55 "3", gate 56 "4", and so forth. To number another branch, process 10 starts at the trunk and then proceeds in the foregoing manner.
- process 10 examines each clock domain and extracts, from each clock domain, the logic gates numbered "1". These gates are stored in an area of a database. Once this is done, process 10 examines each clock domain and extracts, from each domain, the logic gates numbered "2". These gates are stored in another area of the database. This is repeated then, for each set of logic gates numbered "3", "4", etc., until sets of all numbered logic gates are stored in different areas of the database. Using this database, process 10 generates simulation code (in this embodiment, C++ code) for the logic gates.
- C++ code simulation code
- process 10 generates C++ code. That is, process 10 defines the connections of the "1" gates, their states, clocks, and other dependencies in C++ code.
- process 10 generates C++ code to simulate the set of logic gates assigned number "2".
- process 10 generates C++ code to simulate the set of logic gates assigned number "3". This is repeated in sequence until C++ code is generated for all sets of logic gates (e.g., "4", "5", etc.) in the database .
- the C++ simulation code may be generated from the intermediate code using a translation program (not shown) and referencing a database (not shown) that correlates the connections and functions specified in the intermediate code to C++ code. Any parameters or values included in the intermediate code are identified and applied to the C++ code .
- process 10 may run (115) the C++ code through a cycle-based simulator program (this path is indicated by the dotted line in Fig. 1) .
- the cycle-based simulator program provides inputs to, and runs, the C++ code to provide a simulation of the operation of the logic design.
- To obtain an output of the logic design using the cycle-based simulation one pass through each logic gate defined by the C++ code is made.
- a C++ compiler may be unable to compile the C++ code due to its size (i.e., the generated
- C++ code may be too long for a standard C++ compiler) . In these instances, further processing may be required. This processing includes dividing (116) the C++ code into segments based on the numbered logic gates; writing (117) the divided C++ code into separate C++ files and batch files, and compiling the separate C++ files. Thus, in order to use a standard compiler, process 10 compiles C++ code for each set of numbered logic gates. The compiled C++ code may then be run through the cycle-based simulator program separately.
- Process 10 takes advantage of C++ inheritance capabilities to enable the C++ compiler to handle the large numbers of states that may result from a given logic model. That is, the state of an initial logic gate may be defined as a C++ class.
- the states of logic gates that depend from the initial logic gate may refer back to the state of the initial logic gate without actually including data for the state of the initial logic gate. This way, if the state of a subsequent gate depends on the state of a preceding gate, it is possible to obtain the state of the preceding gate without actually adding more data to the database.
- FIG. 6 shows a logic design 80 that contains both combinatorial logic elements (e.g., 82) and state logic elements (e.g., 84).
- relevant design information such as the number of pipeline stages in the design (in this case, there are eight such stages 85 to 92) . Other relevant information may also be obtained.
- FIG. 7 shows a computer 94 for performing simulations using process 10.
- Computer 94 includes a processor 96, a memory 98, and a storage medium 100 (e.g., a hard disk) (see view 102) .
- Storage medium 100 stores data 104 which defines a logic design, a graphics library 106 for implementing the logic design, intermediate code 108, simulation code 110 that represents the logic design, logic simulator programs 112 (e.g., event-driven and/or cycle-based), and machine- executable instructions 114, which are executed by processor 96 out of memory 98 to perform process 10 on data 104.
- Process 10 is not limited to use with the hardware and software of Fig. 7; it may find applicability in any computing or processing environment. Process 10 may be implemented in hardware, software, or a combination of the two.
- Process 10 may be implemented in computer programs executing on programmable computers or other machines that each includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements) , at least one input device, and one or more output devices .
- Program code may be applied to data entered using an input device, such as a mouse or a keyboard, to perform process 10 and to generate a simulation.
- Each such program may be implemented in a high level procedural or object-oriented programming language to communicate with a computer system.
- the programs can be implemented in assembly or machine language.
- the language may be a compiled or an interpreted language.
- Each computer program may be stored on an article of manufacture, such as a storage medium or device (e.g., CD- ROM, hard disk, or magnetic diskette) , that is readable by a general or special purpose programmable machine for configuring and operating the machine when the storage medium or device is read by the machine to perform process 10.
- Process 10 may also be implemented as a machine- readable storage medium, configured with a computer program, where, upon execution, instructions in the computer program cause the machine to operate in accordance with process 10.
- the invention is not limited to the specific embodiments set forth above. For example, process 10 is not limited to simulating only combinatorial and state logic elements. Other logic elements may be simulated.
- Process 10 is not limited to the computer languages set forth above, e.g., Verilog, C++, and VHDL. It may be implemented using any appropriate computer language. Process 10 is also not limited to the order set forth in Fig. 1. That is, the blocks of process 10 may be executed in a different order than that shown to produce an acceptable result.
Abstract
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EP02768673A EP1421526A2 (en) | 2001-08-29 | 2002-08-23 | Simulating a logic design |
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US09/941,952 US7107201B2 (en) | 2001-08-29 | 2001-08-29 | Simulating a logic design |
US09/941,952 | 2001-08-29 |
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US (1) | US7107201B2 (en) |
EP (1) | EP1421526A2 (en) |
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US8515727B2 (en) * | 2008-03-19 | 2013-08-20 | International Business Machines Corporation | Automatic logic model build process with autonomous quality checking |
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US20030046052A1 (en) | 2003-03-06 |
WO2003021492A3 (en) | 2004-02-19 |
TWI255411B (en) | 2006-05-21 |
EP1421526A2 (en) | 2004-05-26 |
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