WO2003021493A3 - Displaying information relating to a logic design - Google Patents
Displaying information relating to a logic design Download PDFInfo
- Publication number
- WO2003021493A3 WO2003021493A3 PCT/US2002/026856 US0226856W WO03021493A3 WO 2003021493 A3 WO2003021493 A3 WO 2003021493A3 US 0226856 W US0226856 W US 0226856W WO 03021493 A3 WO03021493 A3 WO 03021493A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- logic design
- information relating
- displaying information
- display
- information
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/941,923 | 2001-08-29 | ||
US09/941,923 US6643836B2 (en) | 2001-08-29 | 2001-08-29 | Displaying information relating to a logic design |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003021493A2 WO2003021493A2 (en) | 2003-03-13 |
WO2003021493A3 true WO2003021493A3 (en) | 2004-03-18 |
Family
ID=25477301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/026856 WO2003021493A2 (en) | 2001-08-29 | 2002-08-23 | Displaying information relating to a logic design |
Country Status (3)
Country | Link |
---|---|
US (1) | US6643836B2 (en) |
TW (1) | TWI231436B (en) |
WO (1) | WO2003021493A2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7130784B2 (en) * | 2001-08-29 | 2006-10-31 | Intel Corporation | Logic simulation |
US7107201B2 (en) * | 2001-08-29 | 2006-09-12 | Intel Corporation | Simulating a logic design |
JP4145642B2 (en) * | 2002-12-02 | 2008-09-03 | 株式会社ルネサステクノロジ | Logic simulation device |
JP4476831B2 (en) * | 2004-06-08 | 2010-06-09 | 株式会社リコー | Printed wiring board work related information display system, printed wiring board work related information display method, method for manufacturing printed circuit board product using this display method, computer program for executing this display method, and recording medium capable of recording this computer program |
TWI255998B (en) * | 2004-07-14 | 2006-06-01 | Airoha Tech Corp | Circuit design support method, system and machine-readable storage medium |
US7784005B1 (en) * | 2005-06-14 | 2010-08-24 | Xilinx, Inc. | Electronic circuit design viewer |
US7788623B1 (en) | 2007-11-29 | 2010-08-31 | Lattice Semiconductor Corporation | Composite wire indexing for programmable logic devices |
US7890913B1 (en) | 2008-03-25 | 2011-02-15 | Lattice Semiconductor Corporation | Wire mapping for programmable logic devices |
US8225269B2 (en) * | 2009-10-30 | 2012-07-17 | Synopsys, Inc. | Technique for generating an analysis equation |
US8782577B2 (en) * | 2010-07-24 | 2014-07-15 | Cadence Design Systems, Inc. | Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness |
US8689169B2 (en) * | 2010-07-24 | 2014-04-01 | Cadence Design Systems, Inc. | Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness |
US9633052B2 (en) | 2013-05-17 | 2017-04-25 | Oracle International Corporation | System and method for decomposition of code generation into separate physical units though execution units |
Citations (3)
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US5220512A (en) * | 1990-04-19 | 1993-06-15 | Lsi Logic Corporation | System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data |
US5937190A (en) * | 1994-04-12 | 1999-08-10 | Synopsys, Inc. | Architecture and methods for a hardware description language source level analysis and debugging system |
US6132109A (en) * | 1994-04-12 | 2000-10-17 | Synopsys, Inc. | Architecture and methods for a hardware description language source level debugging system |
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US5128871A (en) * | 1990-03-07 | 1992-07-07 | Advanced Micro Devices, Inc. | Apparatus and method for allocation of resoures in programmable logic devices |
US5553002A (en) * | 1990-04-06 | 1996-09-03 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface |
US5572437A (en) * | 1990-04-06 | 1996-11-05 | Lsi Logic Corporation | Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models |
US5258919A (en) * | 1990-06-28 | 1993-11-02 | National Semiconductor Corporation | Structured logic design method using figures of merit and a flowchart methodology |
US5615356A (en) * | 1992-04-21 | 1997-03-25 | Cpu Technology, Inc. | Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit |
US5666289A (en) | 1992-10-07 | 1997-09-09 | Lsi Logic Corporation | Flexible design system |
US5513119A (en) | 1993-08-10 | 1996-04-30 | Mitsubishi Semiconductor America, Inc. | Hierarchical floorplanner for gate array design layout |
US5506788A (en) * | 1994-01-13 | 1996-04-09 | Lsi Logic Corporation | Similarity-extraction force-oriented floor planner |
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JP2972540B2 (en) | 1994-03-24 | 1999-11-08 | 松下電器産業株式会社 | LSI automatic design system and LSI automatic design method |
US5629857A (en) | 1994-11-15 | 1997-05-13 | International Business Machines Corporation | Method and system for indicating a status of a circuit design |
JP3351651B2 (en) * | 1995-04-07 | 2002-12-03 | 富士通株式会社 | Interactive circuit design equipment |
JPH08287111A (en) | 1995-04-14 | 1996-11-01 | Nec Ic Microcomput Syst Ltd | Automatic layout system |
US6117183A (en) * | 1996-01-08 | 2000-09-12 | Fujitsu Limited | Interactive CAD apparatus for designing packaging of logic circuit design |
US6236956B1 (en) * | 1996-02-16 | 2001-05-22 | Avant! Corporation | Component-based analog and mixed-signal simulation model development including newton step manager |
US5963724A (en) * | 1996-02-16 | 1999-10-05 | Analogy, Inc. | Component-based analog and mixed-signal simulation model development |
US5949692A (en) * | 1996-08-28 | 1999-09-07 | Synopsys, Inc. | Hierarchical scan architecture for design for test applications |
JPH10222374A (en) | 1996-10-28 | 1998-08-21 | Altera Corp | Method for providing remote software technological support |
US6120549A (en) | 1997-01-06 | 2000-09-19 | Xilinx, Inc. | Method and apparatus for generating optimized functional macros |
US6053947A (en) | 1997-05-31 | 2000-04-25 | Lucent Technologies, Inc. | Simulation model using object-oriented programming |
US6152612A (en) | 1997-06-09 | 2000-11-28 | Synopsys, Inc. | System and method for system level and circuit level modeling and design simulation using C++ |
US6066179A (en) | 1997-06-13 | 2000-05-23 | University Of Edinburgh | Property estimation of an integrated circuit |
US6233723B1 (en) | 1997-08-28 | 2001-05-15 | Vlsi Technology, Inc. | Circuit behavioral information analysis apparatus and a method of analyzing behavioral information of a circuit |
JPH11126215A (en) * | 1997-10-22 | 1999-05-11 | Nec Corp | Delay analytical result display device |
US6135647A (en) | 1997-10-23 | 2000-10-24 | Lsi Logic Corporation | System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code |
JP4128251B2 (en) * | 1997-10-23 | 2008-07-30 | 富士通株式会社 | Wiring density prediction method and cell placement apparatus |
US6421815B1 (en) | 1998-01-09 | 2002-07-16 | Synopsys, Inc. | Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions |
US6243851B1 (en) * | 1998-03-27 | 2001-06-05 | Xilinx, Inc. | Heterogeneous method for determining module placement in FPGAs |
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US6219822B1 (en) * | 1998-08-05 | 2001-04-17 | International Business Machines Corporation | Method and system for tuning of components for integrated circuits |
US6480985B1 (en) | 1998-08-26 | 2002-11-12 | Mentor Graphics Corporation | Method and apparatus for graphically presenting an integrated circuit design |
US6272671B1 (en) * | 1998-09-11 | 2001-08-07 | Lsi Logic Corporation | Extractor and schematic viewer for a design representation, and associated method |
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US6298468B1 (en) * | 1999-05-04 | 2001-10-02 | Prosper Design Systems Pte. Ltd. | Placement-based pin optimization method and apparatus for computer-aided circuit design |
US6366874B1 (en) * | 1999-05-24 | 2002-04-02 | Novas Software, Inc. | System and method for browsing graphically an electronic design based on a hardware description language specification |
US6519755B1 (en) | 1999-08-16 | 2003-02-11 | Sequence Design, Inc. | Method and apparatus for logic synthesis with elaboration |
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US6769098B2 (en) | 2000-02-29 | 2004-07-27 | Matsushita Electric Industrial Co., Ltd. | Method of physical design for integrated circuit |
JP2002108960A (en) * | 2000-10-03 | 2002-04-12 | Fujitsu Ltd | Arrangement/wiring processing system |
JP2002117092A (en) | 2000-10-05 | 2002-04-19 | Fujitsu Ltd | Method and system for designing semiconductor integrated circuit device |
US6684379B2 (en) | 2000-10-18 | 2004-01-27 | Chipworks | Design analysis workstation for analyzing integrated circuits |
US6516452B2 (en) | 2001-05-01 | 2003-02-04 | Chipdata, Inc. | Method and apparatus for verifying design data |
US6487698B1 (en) | 2001-05-04 | 2002-11-26 | Lsi Logic Corporation | Process, apparatus and program for transforming program language description of an IC to an RTL description |
US6477689B1 (en) | 2001-06-13 | 2002-11-05 | The Boeing Company | Architectural structure of a process netlist design tool |
US20030005396A1 (en) * | 2001-06-16 | 2003-01-02 | Chen Michael Y. | Phase and generator based SOC design and/or verification |
US6868526B2 (en) | 2001-07-18 | 2005-03-15 | The Mathworks, Inc. | Graphical subclassing |
US7613716B2 (en) | 2001-07-20 | 2009-11-03 | The Mathworks, Inc. | Partitioning for model-based design |
-
2001
- 2001-08-29 US US09/941,923 patent/US6643836B2/en not_active Expired - Fee Related
-
2002
- 2002-08-23 WO PCT/US2002/026856 patent/WO2003021493A2/en not_active Application Discontinuation
- 2002-08-28 TW TW091119574A patent/TWI231436B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220512A (en) * | 1990-04-19 | 1993-06-15 | Lsi Logic Corporation | System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data |
US5937190A (en) * | 1994-04-12 | 1999-08-10 | Synopsys, Inc. | Architecture and methods for a hardware description language source level analysis and debugging system |
US6132109A (en) * | 1994-04-12 | 2000-10-17 | Synopsys, Inc. | Architecture and methods for a hardware description language source level debugging system |
Also Published As
Publication number | Publication date |
---|---|
US6643836B2 (en) | 2003-11-04 |
US20030046648A1 (en) | 2003-03-06 |
TWI231436B (en) | 2005-04-21 |
WO2003021493A2 (en) | 2003-03-13 |
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