WO2003021693A2 - Elevated pore phase-change memory - Google Patents

Elevated pore phase-change memory Download PDF

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Publication number
WO2003021693A2
WO2003021693A2 PCT/US2002/026375 US0226375W WO03021693A2 WO 2003021693 A2 WO2003021693 A2 WO 2003021693A2 US 0226375 W US0226375 W US 0226375W WO 03021693 A2 WO03021693 A2 WO 03021693A2
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WO
WIPO (PCT)
Prior art keywords
memory
phase
lower electrode
cup
change material
Prior art date
Application number
PCT/US2002/026375
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French (fr)
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WO2003021693A3 (en
Inventor
Tyler A. Lowrey
Original Assignee
Ovonyx, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ovonyx, Inc. filed Critical Ovonyx, Inc.
Priority to JP2003525922A priority Critical patent/JP4150667B2/en
Priority to KR10-2004-7002594A priority patent/KR100534530B1/en
Publication of WO2003021693A2 publication Critical patent/WO2003021693A2/en
Publication of WO2003021693A3 publication Critical patent/WO2003021693A3/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • Phase-change materials may exhibit at least two different states.
  • the states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated in response to temperature changes.
  • the states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state.
  • the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered atomic structure.
  • any phase-change material may be utilized, h some embodiments, however, thin-film chalcogenide alloy materials may be particularly suitable.
  • phase-change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter or vice versa, hi effect, each memory cell may be thought of as a programmable resistor that reversibly changes between higher and lower resistance states.
  • a cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance determined states may be possible, allowing the storage of multiple bits of data in a single cell.
  • phase-change alloys A variety of phase-change alloys are known.
  • chalcogenide alloys contain one or more elements from column NI of the periodic table.
  • One particularly suitable group of alloys are GeSbTe alloys.
  • a phase-change material may be formed within a passage or pore defined through a dielectric material.
  • the phase-change material may be coupled to contacts on either end of the passage. State transitions may be induced by applying a current to heat the phase-change material.
  • An access device may be defined in the substrate of a semiconductor integrated circuit to activate an overlying phase-change material.
  • Other phase-change memory components may also be integrated into the semiconductor substrate. Patterning features over integrated topography may adversely impact the underlying integrated features. Thus, it would be desirable to form the phase-change memory in a fashion, above the rest of the mtegrated circuit, that does not interfere with any of the previously fabricated integrated structures.
  • Another issue with phase-change memories is that the greater the heat loss from each memory cell, the greater the current that must be applied for device programming. Thus, it would be desirable to reduce the amount of heat loss from the heated phase-change material. Similarly, it is desirable to distribute the heat homogenously across the phase-change material.
  • many currently proposed techniques result in local variations in device resistance after a programming event. These local variations may also result in stress in local regions during the phase-change programming.
  • Figure 1 is an enlarged cross-sectional view of one embodiment of the present invention.
  • FIGS 2A through 21 are enlarged cross-sectional views of a process for manufacturing the device shown in Figure 1 in accordance with one embodiment of the present invention.
  • a phase-change memory cell 10 may include an elevated pore in accordance with one embodiment of the present invention.
  • a substrate 12 may include an mtegrated circuit including access transistors (not shown) that control the current through a base contact 16.
  • a shallow trench isolation structure 14 may isolate the memory cell 10 from the remainder of the structures formed in the substrate 12.
  • the liner conductor 18 may be tubular and cup-shaped and may define an open central region that may be filled with a fill insulator 20 in accordance with one embodiment of the present invention.
  • the liner conductor 18 conducts current from the base contact 16 upwardly to an elevated pore.
  • the elevated pore includes a resistive or lower electrode 22 that may also be tubular and cup-shaped. Within the interior of the lower electrode 22 is a pore defined by a pair of opposed spacers 24 and a phase-change layer 28.
  • the phase-change layer 28 also may be cup-shaped and may be filled with an upper electrode 30 in one embodiment of the present invention.
  • the upper electrode 30 and the phase-change material 28 may be patterned in one embodiment of the present invention.
  • the process of forming the structure shown in Figure 1 begins by forming a pore 34 through an etch stop layer 26 and a dielectric layer 32.
  • the etch stop layer 26 may be of a material that is less prone to being etched relative to a variety of surrounding layers.
  • the etch stop layer 26 may be silicon nitride or Si 3 N 4 .
  • a liner conductor 18 may be deposited within the pore 34 in one embodiment of the present invention.
  • the liner conductor 18 may be titanium, titanium nitride, Tungsten or a combination of these materials in some embodiments.
  • the liner conductor 18 lines the cylindrical pore 34 and may be filled with a fill material 20.
  • the liner conductor 18 is conformal, with consistent coverage on the sidewalls of the pore 34.
  • the fill material 20 provides thermal and electrical isolation, hi one embodiment, the fill material 20 may be silicon dioxide.
  • FIG. 2C the structure shown in Figure 2B may be planarized.
  • a chemical mechanical planarization (CMP) process may be utilized to create the planar surface indicated as S.
  • the etch stop layer 26 may be used to provide a well controlled final stopping point for the planarization.
  • the fill material 20 is subjected to an etch of controlled distance.
  • an opening 36 is formed of a controlled depth.
  • the etch of the fill material 20 may be done with a dry insulator etch. This may be followed by an etch of the liner conductor 18.
  • the liner conductor 18 may be etched isotropically with minimal overetch.
  • the liner conductor 18 may be etched using a wet etch following the etch of the fill material 20.
  • a resistive or lower electrode 22 may be deposited in one embodiment of the present invention, as shown in Figure 2E.
  • the opening 36 in the upper surface of the etch stop 26 may be covered with the lower electrode 22.
  • the electrode 22 may then be covered with an insulator 40.
  • the lower electrode 22 makes an electrical connection to the liner conductor 18 that in turn makes an electrical connection to the contact 16 in the substrate 12.
  • the structure shown in Figure 2E is then subjected to a planarization process such as CMP, to produce the planarized structure shown in Figure 2F.
  • the liner conductor 18 is then subjected to a recess etch to form the recessed regions indicated at E.
  • the recess etch may be a short wet etch.
  • the insulator 40 may be removed using an etching process, such as a dry or wet insulator etch, to produce the pore indicated as F, as shown in Figure 2G, with the lower electrode 22 exposed.
  • a sidewall spacer 24 may be formed as shown in Figure 2H.
  • the spacer 24 may be formed conventionally, for example by depositing an insulator material and then anisotropically etching the deposited insulator material.
  • the sidewall spacer 24 may be silicon nitride or silicon dioxide.
  • the structure shown in Figure 2H may be covered by a phase-change layer 28 and an upper electrode layer 30.
  • the phase- change layer 28 is cup-shaped and extends downwardly into the pore defined by the spacer 24 on the sides and the lower electrode 22 on the bottom.
  • the phase- change material maybe Ge Sb 2 Te 5 .
  • the upper electrode 28 may be a sandwich of a plurality of layers.
  • the sandwich may include, starting at the bottom, titanium, followed by titanium nitride followed by aluminum.
  • phase-change layer 28 and upper electrode 30 may be patterned to achieve the structure shown in Figure 1 in some embodiments.
  • elevating the pore above the substrate 12 facilitates the integration of the phase-change memory cell into standard complementary metal oxide semiconductor (CMOS) process flows, h particular, elevating the pore avoids patterning features on integrated circuit topography in the substrate 12.
  • Photolithographic steps may be on planarized surfaces as a result.
  • a thermally efficient device structure provides for improved device performance by reducing the required power for device programming.
  • the programmable media volume, represented by the phase-change layer 28, is nearly surrounded by thermal insulation.
  • the lower electrode 22 provides the heat for producing phase changes at lower currents.
  • the lower electrode 22 may be made relatively thin, reducing heat loss through the electrode 22 in some embodiments, hi addition, in some embodiments, temperature distribution is more homogeneous during programming providing for less local variation in device resistance after programming. This structure may also result in developing less stress in local regions when invoking a phase change, in some embodiments.
  • cell size may be reduced, thereby reducing product cost. Only two additional masking steps may be required to form the structure, in some embodiments, also reducing costs and shortening process cycle times.

Abstract

An elevated phase-change memory cell (10) facilitates manufacture of phase-change memories by physically separating the fabrication of the phase-change memory components from the rest of the semiconductor substrate (12). In one embodiment, a contact (16) in the substrate (12) may be electrically coupled to a cup-shaped conductor (18) filled with an insulator 20). The conductor (18) couples current up to the elevated pore while the insulator (20) thermally and electrically isolates the pore.

Description

Elevated Pore Phase-Change Memory Background
This invention relates generally to memories that use phase-change materials. Phase-change materials may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated in response to temperature changes. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered atomic structure. Generally, any phase-change material may be utilized, h some embodiments, however, thin-film chalcogenide alloy materials may be particularly suitable.
The phase-change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter or vice versa, hi effect, each memory cell may be thought of as a programmable resistor that reversibly changes between higher and lower resistance states.
In some situations, a cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance determined states may be possible, allowing the storage of multiple bits of data in a single cell.
A variety of phase-change alloys are known. Generally, chalcogenide alloys contain one or more elements from column NI of the periodic table. One particularly suitable group of alloys are GeSbTe alloys.
A phase-change material may be formed within a passage or pore defined through a dielectric material. The phase-change material may be coupled to contacts on either end of the passage. State transitions may be induced by applying a current to heat the phase-change material.
An access device may be defined in the substrate of a semiconductor integrated circuit to activate an overlying phase-change material. Other phase-change memory components may also be integrated into the semiconductor substrate. Patterning features over integrated topography may adversely impact the underlying integrated features. Thus, it would be desirable to form the phase-change memory in a fashion, above the rest of the mtegrated circuit, that does not interfere with any of the previously fabricated integrated structures. Another issue with phase-change memories is that the greater the heat loss from each memory cell, the greater the current that must be applied for device programming. Thus, it would be desirable to reduce the amount of heat loss from the heated phase-change material. Similarly, it is desirable to distribute the heat homogenously across the phase-change material. However, many currently proposed techniques result in local variations in device resistance after a programming event. These local variations may also result in stress in local regions during the phase-change programming.
It would be desirable to reduce the cell size as much as possible to thereby reduce product cost. Also it would be desirable to reduce the number of manufacturing steps to the greatest possible extent, to reduce costs.
Thus, there is a need for improved phase-change memories and techniques for making the same.
Brief Description of the Drawings Figure 1 is an enlarged cross-sectional view of one embodiment of the present invention; and
Figures 2A through 21 are enlarged cross-sectional views of a process for manufacturing the device shown in Figure 1 in accordance with one embodiment of the present invention.
Detailed Description
Referring to Figure 1, a phase-change memory cell 10 may include an elevated pore in accordance with one embodiment of the present invention. A substrate 12 may include an mtegrated circuit including access transistors (not shown) that control the current through a base contact 16. A shallow trench isolation structure 14 may isolate the memory cell 10 from the remainder of the structures formed in the substrate 12. Over the substrate 12, is a liner conductor 18 in accordance with one embodiment of the present invention. The liner conductor 18 may be tubular and cup-shaped and may define an open central region that may be filled with a fill insulator 20 in accordance with one embodiment of the present invention. The liner conductor 18 conducts current from the base contact 16 upwardly to an elevated pore. The elevated pore includes a resistive or lower electrode 22 that may also be tubular and cup-shaped. Within the interior of the lower electrode 22 is a pore defined by a pair of opposed spacers 24 and a phase-change layer 28. The phase-change layer 28 also may be cup-shaped and may be filled with an upper electrode 30 in one embodiment of the present invention. The upper electrode 30 and the phase-change material 28 may be patterned in one embodiment of the present invention.
Referring to Figure 2A, the process of forming the structure shown in Figure 1 begins by forming a pore 34 through an etch stop layer 26 and a dielectric layer 32. The etch stop layer 26 may be of a material that is less prone to being etched relative to a variety of surrounding layers. In one embodiment, the etch stop layer 26 may be silicon nitride or Si3N4.
Moving to Figure 2B, a liner conductor 18 may be deposited within the pore 34 in one embodiment of the present invention. The liner conductor 18 may be titanium, titanium nitride, Tungsten or a combination of these materials in some embodiments. The liner conductor 18 lines the cylindrical pore 34 and may be filled with a fill material 20. Advantageously, the liner conductor 18 is conformal, with consistent coverage on the sidewalls of the pore 34. The fill material 20 provides thermal and electrical isolation, hi one embodiment, the fill material 20 may be silicon dioxide.
Turning next to Figure 2C, the structure shown in Figure 2B may be planarized. In one embodiment of the present invention a chemical mechanical planarization (CMP) process may be utilized to create the planar surface indicated as S. The etch stop layer 26 may be used to provide a well controlled final stopping point for the planarization.
As shown in Figure 2D, the fill material 20 is subjected to an etch of controlled distance. Thus, an opening 36 is formed of a controlled depth. In one embodiment of the present invention, the etch of the fill material 20 may be done with a dry insulator etch. This may be followed by an etch of the liner conductor 18. In one embodiment, the liner conductor 18 may be etched isotropically with minimal overetch. In one embodiment, the liner conductor 18 may be etched using a wet etch following the etch of the fill material 20. Next, a resistive or lower electrode 22 may be deposited in one embodiment of the present invention, as shown in Figure 2E. The opening 36 in the upper surface of the etch stop 26 may be covered with the lower electrode 22. The electrode 22 may then be covered with an insulator 40. The lower electrode 22 makes an electrical connection to the liner conductor 18 that in turn makes an electrical connection to the contact 16 in the substrate 12. The structure shown in Figure 2E is then subjected to a planarization process such as CMP, to produce the planarized structure shown in Figure 2F. The liner conductor 18 is then subjected to a recess etch to form the recessed regions indicated at E. In one embodiment, the recess etch may be a short wet etch.
Thereafter, the insulator 40 may be removed using an etching process, such as a dry or wet insulator etch, to produce the pore indicated as F, as shown in Figure 2G, with the lower electrode 22 exposed. Thereafter, a sidewall spacer 24 may be formed as shown in Figure 2H. The spacer 24 may be formed conventionally, for example by depositing an insulator material and then anisotropically etching the deposited insulator material. In one embodiment, the sidewall spacer 24 may be silicon nitride or silicon dioxide.
Then, as shown in Figure 21, the structure shown in Figure 2H may be covered by a phase-change layer 28 and an upper electrode layer 30. hi one embodiment, the phase- change layer 28 is cup-shaped and extends downwardly into the pore defined by the spacer 24 on the sides and the lower electrode 22 on the bottom. In one embodiment, the phase- change material maybe Ge Sb2Te5.
The upper electrode 28 may be a sandwich of a plurality of layers. In one embodiment, the sandwich may include, starting at the bottom, titanium, followed by titanium nitride followed by aluminum.
An electrical connection may be established from the base contact 16 in the substrate 12 through the liner conductor 18 to the lower electrode 22 and then to the phase-change layer 28. Finally in some embodiments, the phase-change layer 28 and upper electrode 30 may be patterned to achieve the structure shown in Figure 1 in some embodiments. hi some embodiments, elevating the pore above the substrate 12 facilitates the integration of the phase-change memory cell into standard complementary metal oxide semiconductor (CMOS) process flows, h particular, elevating the pore avoids patterning features on integrated circuit topography in the substrate 12. Photolithographic steps may be on planarized surfaces as a result. hi some embodiments, a thermally efficient device structure provides for improved device performance by reducing the required power for device programming. The programmable media volume, represented by the phase-change layer 28, is nearly surrounded by thermal insulation.
The lower electrode 22 provides the heat for producing phase changes at lower currents. The lower electrode 22 may be made relatively thin, reducing heat loss through the electrode 22 in some embodiments, hi addition, in some embodiments, temperature distribution is more homogeneous during programming providing for less local variation in device resistance after programming. This structure may also result in developing less stress in local regions when invoking a phase change, in some embodiments.
Likewise, in some embodiments, cell size may be reduced, thereby reducing product cost. Only two additional masking steps may be required to form the structure, in some embodiments, also reducing costs and shortening process cycle times.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of tins present invention.

Claims

What is claimed is:
1. A method comprising: forming a base contact in a semiconductor structure; covering said semiconductor structure with a layer; forming an electrical connection through said layer to said contact; and forming a phase-change material over said layer, said material electrically coupled to said contact.
2. The method of claim 1 wherein covering said semiconductor structure with a layer includes covering said structure with at least one insulating layer.
3. The method of claim 2 including forming a passage through said insulating layer.
4. The method of claim 3 including forming the electrical connection through said passage.
5. The method of claim 4 wherein forming an electrical connection includes forming a cup-shaped electrical connection.
6. The method of claim 5 including filling said cup-shaped electrical connection with an insulator.
7. The method of claim 6 including forming a lower electrode coupled to said cup-shaped connection.
8. The method of claim 7 including forming a cup-shaped lower electrode.
9. The method of claim 8 including forming a sidewall spacer in said cup-shaped lower electrode.
10. The method of claim 9 wherein forming a phase-change material includes depositing a phase-change material over said insulating layer and said spacer and electrically contacting said lower electrode.
11. A memory comprising: a semiconductor structure; a base contact formed on said semiconductor structure; an insulating layer over said semiconductor structure; a passage formed through said insulating layer, said passage including an electrical connection; and a phase-change material electrically coupled to said electrical connection.
12. The memory of claim 11 wherein said electrical connection is cup-shaped.
13. The memory of claim 12 including a lower electrode.
14. The memory of claim 13 including a sidewall spacer on said lower electrode.
15. The memory of claim 14 wherein the phase-change material is formed over said sidewall spacer and in contact with said lower electrode.
16. The memory of claim 15 including an insulating material within said cup- shaped electrical connection.
17. The memory of claim 16 wherein said lower electrode is cup-shaped.
18. The memory of claim 17 wherein said lower electrode is recessed below the upper surface of said insulating layer.
19. The memory of claim 18 including an upper electrode over said phase-change material.
20. A memory comprising: a semiconductor structure; a phase-change material spaced above said semiconductor structure; and a tubular connector electrically coupling said phase-change material to said semiconductor structure.
21. The memory of claim 20 including an insulating layer over said semiconductor structure.
22. The memory of claim 21 including a passage formed through said insulating layer.
23. The memory of claim 22 wherein said passage is lined with said tubular connector.
24. The memory of claim 20 including a lower electrode electrically coupled to said phase-change material and said connector.
25. The memory of claim 24 wherein said lower electrode is tubular.
26. The memory of claim 20 wherein said connector is cup-shaped.
27. The memory of claim 26 wherein said lower electrode is cup-shaped.
28. The memory of claim 27 including a sidewall spacer over said electrode and between said electrode and said phase-change material.
29. The memory of claim 28 wherein said sidewall spacer is positioned within said passage and wherein said sidewall spacer is cylindrical.
30. The memory of claim 29 including an upper electrode over said phase-change material.
PCT/US2002/026375 2001-08-31 2002-08-20 Elevated pore phase-change memory WO2003021693A2 (en)

Priority Applications (2)

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JP2003525922A JP4150667B2 (en) 2001-08-31 2002-08-20 Phase change memory with higher pore position
KR10-2004-7002594A KR100534530B1 (en) 2001-08-31 2002-08-20 Elevated pore phase-change memory

Applications Claiming Priority (2)

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US09/944,478 2001-08-31
US09/944,478 US6764894B2 (en) 2001-08-31 2001-08-31 Elevated pore phase-change memory

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