WO2003025595A3 - Electronic device - Google Patents
Electronic device Download PDFInfo
- Publication number
- WO2003025595A3 WO2003025595A3 PCT/IB2002/003617 IB0203617W WO03025595A3 WO 2003025595 A3 WO2003025595 A3 WO 2003025595A3 IB 0203617 W IB0203617 W IB 0203617W WO 03025595 A3 WO03025595 A3 WO 03025595A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test
- chain
- test interface
- electronic device
- contact
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318563—Multiple simultaneous testing of subparts
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318561—Identification of the subpart
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020047004092A KR100896538B1 (en) | 2001-09-20 | 2002-09-04 | Electronic device |
DE60218498T DE60218498T2 (en) | 2001-09-20 | 2002-09-04 | ELECTRONIC DEVICE |
EP02762683A EP1430319B1 (en) | 2001-09-20 | 2002-09-04 | Electronic device |
JP2003529172A JP4249019B2 (en) | 2001-09-20 | 2002-09-04 | Electronic devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01203565.5 | 2001-09-20 | ||
EP01203565 | 2001-09-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003025595A2 WO2003025595A2 (en) | 2003-03-27 |
WO2003025595A3 true WO2003025595A3 (en) | 2003-08-28 |
Family
ID=8180950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2002/003617 WO2003025595A2 (en) | 2001-09-20 | 2002-09-04 | Electronic device |
Country Status (9)
Country | Link |
---|---|
US (1) | US6988230B2 (en) |
EP (1) | EP1430319B1 (en) |
JP (1) | JP4249019B2 (en) |
KR (1) | KR100896538B1 (en) |
CN (1) | CN100342241C (en) |
AT (1) | ATE355534T1 (en) |
DE (1) | DE60218498T2 (en) |
TW (1) | TWI232951B (en) |
WO (1) | WO2003025595A2 (en) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7222315B2 (en) | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
US7827510B1 (en) | 2002-06-07 | 2010-11-02 | Synopsys, Inc. | Enhanced hardware debugging with embedded FPGAS in a hardware description language |
KR20050084803A (en) * | 2002-08-14 | 2005-08-29 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Module, electronic device and evaluation tool |
US7010722B2 (en) * | 2002-09-27 | 2006-03-07 | Texas Instruments Incorporated | Embedded symmetric multiprocessor system debug |
JP2007500356A (en) * | 2003-05-28 | 2007-01-11 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Signal integrity self-test architecture |
US7246282B2 (en) * | 2003-06-25 | 2007-07-17 | Hewlett-Packard Development Company, L.P. | Bypassing a device in a scan chain |
ATE394683T1 (en) * | 2004-01-13 | 2008-05-15 | Nxp Bv | JTAG TEST ARCHITECTURE FOR A MULTI-CHIP PACK |
DE602005010215D1 (en) * | 2004-02-19 | 2008-11-20 | Nxp Bv | ELECTRONIC STREAM PROCESSING CIRCUIT WITH TEST ACCESS |
WO2005086940A2 (en) * | 2004-03-11 | 2005-09-22 | Interdigital Technology Corporation | Control of device operation within an area |
US20060137018A1 (en) * | 2004-11-29 | 2006-06-22 | Interdigital Technology Corporation | Method and apparatus to provide secured surveillance data to authorized entities |
US20060159440A1 (en) * | 2004-11-29 | 2006-07-20 | Interdigital Technology Corporation | Method and apparatus for disrupting an autofocusing mechanism |
TWI285742B (en) * | 2004-12-06 | 2007-08-21 | Interdigital Tech Corp | Method and apparatus for detecting portable electronic device functionality |
US7574220B2 (en) * | 2004-12-06 | 2009-08-11 | Interdigital Technology Corporation | Method and apparatus for alerting a target that it is subject to sensing and restricting access to sensed content associated with the target |
US20060227640A1 (en) * | 2004-12-06 | 2006-10-12 | Interdigital Technology Corporation | Sensing device with activation and sensing alert functions |
US20090307545A1 (en) * | 2004-12-20 | 2009-12-10 | Koninklijke Philips Electronics N.V. | Testable multiprocessor system and a method for testing a processor system |
JP4388903B2 (en) | 2005-02-09 | 2009-12-24 | 富士通マイクロエレクトロニクス株式会社 | JTAG test method |
TW200708750A (en) | 2005-07-22 | 2007-03-01 | Koninkl Philips Electronics Nv | Testable integrated circuit, system in package and test instruction set |
JP2009512873A (en) * | 2005-10-24 | 2009-03-26 | エヌエックスピー ビー ヴィ | IC testing method and apparatus |
WO2007069097A1 (en) * | 2005-11-02 | 2007-06-21 | Nxp B.V. | Ic testing methods and apparatus |
EP1791133A1 (en) * | 2005-11-29 | 2007-05-30 | STMicroelectronics Pvt. Ltd. | A method of sharing testing components for multiple embedded memories and the memory system incorporating the same |
US7579689B2 (en) * | 2006-01-31 | 2009-08-25 | Mediatek Inc. | Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package |
JP4791533B2 (en) * | 2006-03-16 | 2011-10-12 | パナソニック株式会社 | Terminal device |
US7546498B1 (en) * | 2006-06-02 | 2009-06-09 | Lattice Semiconductor Corporation | Programmable logic devices with custom identification systems and methods |
US7620864B2 (en) * | 2006-10-26 | 2009-11-17 | International Business Machines Corporation | Method and apparatus for controlling access to and/or exit from a portion of scan chain |
KR100829402B1 (en) * | 2006-11-01 | 2008-05-15 | 주식회사 유니테스트 | Sequential semiconductor test apparatus |
US7657854B2 (en) * | 2006-11-24 | 2010-02-02 | Freescale Semiconductor, Inc. | Method and system for designing test circuit in a system on chip |
US8108744B2 (en) * | 2006-11-28 | 2012-01-31 | Stmicroelectronics Pvt. Ltd. | Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces |
JP2008310792A (en) * | 2007-05-11 | 2008-12-25 | Nec Electronics Corp | Test circuit |
US7937631B2 (en) * | 2007-08-28 | 2011-05-03 | Qimonda Ag | Method for self-test and self-repair in a multi-chip package environment |
US7904770B2 (en) * | 2008-09-09 | 2011-03-08 | Qualcomm Incorporated | Testing circuit split between tiers of through silicon stacking chips |
EP2372379B1 (en) * | 2010-03-26 | 2013-01-23 | Imec | Test access architecture for TSV-based 3D stacked ICS |
KR101035399B1 (en) * | 2010-10-19 | 2011-05-20 | (주)청석엔지니어링 | Buthyl synthetic rubber sheets waterproof material of self-adhesion type containing used tire polymer and construction method for waterproofing by using the same |
KR101010358B1 (en) * | 2010-10-19 | 2011-01-25 | (주)청석엔지니어링 | Buthyl synthetic rubber sheets waterproof material containing nonwoven of vertical and horizontal direction and construction method for waterproofing by using the same |
TW201221981A (en) * | 2010-11-24 | 2012-06-01 | Inventec Corp | Multi-chip testing system and testing method thereof |
US20130086441A1 (en) * | 2011-09-30 | 2013-04-04 | Qualcomm Incorporated | Dynamically self-reconfigurable daisy-chain of tap controllers |
DE102012210408A1 (en) * | 2012-06-20 | 2013-12-24 | Robert Bosch Gmbh | Method for driving a state machine |
US9026872B2 (en) * | 2012-08-16 | 2015-05-05 | Xilinx, Inc. | Flexible sized die for use in multi-die integrated circuit |
US9063734B2 (en) | 2012-09-07 | 2015-06-23 | Atmel Corporation | Microcontroller input/output connector state retention in low-power modes |
US9250690B2 (en) * | 2012-09-10 | 2016-02-02 | Atmel Corporation | Low-power modes of microcontroller operation with access to configurable input/output connectors |
US9547034B2 (en) | 2013-07-03 | 2017-01-17 | Xilinx, Inc. | Monolithic integrated circuit die having modular die regions stitched together |
GB2518866A (en) * | 2013-10-03 | 2015-04-08 | St Microelectronics Res & Dev | Flexible interface |
US10151794B2 (en) * | 2014-06-19 | 2018-12-11 | X-Fab Semiconductor Foundries Ag | Sleek serial interface for a wrapper boundary register (device and method) |
US9557383B2 (en) | 2014-12-12 | 2017-01-31 | International Business Machines Corporation | Partitioned scan chain diagnostics using multiple bypass structures and injection points |
US9429621B2 (en) | 2015-01-27 | 2016-08-30 | International Business Machines Corporation | Implementing enhanced scan chain diagnostics via bypass multiplexing structure |
US9964597B2 (en) * | 2016-09-01 | 2018-05-08 | Texas Instruments Incorporated | Self test for safety logic |
KR101890030B1 (en) * | 2016-09-02 | 2018-08-20 | 주식회사 아이닉스 | Devices connected by chain-type and setup method therefor |
CN110825439B (en) * | 2018-08-10 | 2021-03-09 | 北京百度网讯科技有限公司 | Information processing method and processor |
US11249134B1 (en) * | 2020-10-06 | 2022-02-15 | Qualcomm Incorporated | Power-collapsible boundary scan |
CN112098818B (en) * | 2020-11-02 | 2021-02-02 | 创意电子(南京)有限公司 | SIP device testing system based on standard boundary scanning circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5673276A (en) * | 1993-12-27 | 1997-09-30 | Lucent Technologies Inc. | Boundary-scan-compliant multi-chip module |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5615217A (en) * | 1994-12-01 | 1997-03-25 | International Business Machines Corporation | Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components |
DE69734379T2 (en) * | 1996-08-30 | 2006-07-06 | Texas Instruments Inc., Dallas | Device for testing integrated circuits |
JPH1183956A (en) * | 1997-06-30 | 1999-03-26 | Texas Instr Inc <Ti> | Integrated circuit |
US6032279A (en) * | 1997-11-07 | 2000-02-29 | Atmel Corporation | Boundary scan system with address dependent instructions |
KR19990047438A (en) * | 1997-12-04 | 1999-07-05 | 윤종용 | Semiconductor device with bypass circuit using pin sharing |
-
2002
- 2002-09-04 CN CNB028182812A patent/CN100342241C/en not_active Expired - Fee Related
- 2002-09-04 JP JP2003529172A patent/JP4249019B2/en not_active Expired - Fee Related
- 2002-09-04 DE DE60218498T patent/DE60218498T2/en not_active Expired - Lifetime
- 2002-09-04 EP EP02762683A patent/EP1430319B1/en not_active Expired - Lifetime
- 2002-09-04 KR KR1020047004092A patent/KR100896538B1/en not_active IP Right Cessation
- 2002-09-04 AT AT02762683T patent/ATE355534T1/en not_active IP Right Cessation
- 2002-09-04 WO PCT/IB2002/003617 patent/WO2003025595A2/en active IP Right Grant
- 2002-09-17 US US10/245,489 patent/US6988230B2/en not_active Expired - Fee Related
- 2002-09-17 TW TW091121225A patent/TWI232951B/en active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5673276A (en) * | 1993-12-27 | 1997-09-30 | Lucent Technologies Inc. | Boundary-scan-compliant multi-chip module |
Also Published As
Publication number | Publication date |
---|---|
KR20040035848A (en) | 2004-04-29 |
DE60218498D1 (en) | 2007-04-12 |
ATE355534T1 (en) | 2006-03-15 |
CN1555491A (en) | 2004-12-15 |
TWI232951B (en) | 2005-05-21 |
EP1430319A2 (en) | 2004-06-23 |
US6988230B2 (en) | 2006-01-17 |
KR100896538B1 (en) | 2009-05-07 |
JP2005503563A (en) | 2005-02-03 |
JP4249019B2 (en) | 2009-04-02 |
WO2003025595A2 (en) | 2003-03-27 |
US20030079166A1 (en) | 2003-04-24 |
CN100342241C (en) | 2007-10-10 |
EP1430319B1 (en) | 2007-02-28 |
DE60218498T2 (en) | 2007-11-08 |
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