WO2003028091A2 - Copper interconnect barrier layer structure and formation method - Google Patents

Copper interconnect barrier layer structure and formation method Download PDF

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Publication number
WO2003028091A2
WO2003028091A2 PCT/US2002/029954 US0229954W WO03028091A2 WO 2003028091 A2 WO2003028091 A2 WO 2003028091A2 US 0229954 W US0229954 W US 0229954W WO 03028091 A2 WO03028091 A2 WO 03028091A2
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copper interconnect
tungsten
layer
barrier layer
substrate
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PCT/US2002/029954
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French (fr)
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WO2003028091A3 (en
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Ling Chen
Seshadri Ganguli
Christophe Marcadal
Cao Wei
Roderick C. Mosely
Mei Chang
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Applied Materials, Inc.
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Publication of WO2003028091A2 publication Critical patent/WO2003028091A2/en
Publication of WO2003028091A3 publication Critical patent/WO2003028091A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • a conventional copper interconnect structure formation process includes first depositing a tantalum or tantalum- nitride copper interconnect barrier layer on a substrate (e.g., a single or dual-damascene dielectric substrate) using Physical Vapor Deposition (PVD), followed by the deposition of a copper seed layer. A bulk copper layer is subsequently formed on the copper seed layer by electroplating.
  • PVD Physical Vapor Deposition
  • deposition processes can be characterized by sidewall step coverage and aspect ratio.
  • Sidewall step coverage is defined as the ratio of a layer's thickness on the sidewall of a feature to that on a horizontal surface adjacent to the feature and is generally expressed as a percentage.
  • Aspect ratio is defined as the height of a feature (e.g., a via or trench) versus the width of the feature.
  • a drawback of the conventional copper interconnect process described above is the low sidewall step coverage obtained for Ta and TaN copper interconnect barrier layers formed using PND techniques.
  • the sidewall step coverage obtained with PVD techniques is typically around 10%.
  • W X ⁇ Tungsten-nitride layers deposited using Chemical Vapor Deposition (CVD) have been investigated as potential copper interconnect barrier layers.
  • W X N layers deposited by CVD can also suffer from undesirably low sidewall step coverage, as well as from poor adhesion to underlying dielectric layers.
  • a copper interconnect barrier structure that includes a copper interconnect barrier layer with a high sidewall step coverage.
  • the present invention provides a method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [W X N] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage.
  • a tungsten-containing copper interconnect barrier layer e.g., a tungsten [W] or tungsten-nitride [W X N] copper interconnect barrier layer
  • the method also results in ample adhesion of the togsten-containing copper interconnect barrier layer to any underlying dielectric layers.
  • a process according to one exemplary embodiment of the present invention includes first depositing, on a substrate, a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer, followed by the formation of a tungsten-containing copper interconnect barrier layer (e.g., a W or W X N copper interconnect barrier layer) thereon.
  • a tungsten-containing copper interconnect barrier layer e.g., a W or W X N copper interconnect barrier layer
  • the tungsten-containing copper interconnect barrier layer can be formed, for example, using a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl W[CO] 6 ).
  • the tungsten-containing copper interconnect barrier layer can be formed using a WF 6 -based Atomic Layer Deposition (ALD) technique.
  • ALD Atomic Layer Deposition
  • a thin TiN (or TaN) nucleation layer on the substrate facilitates formation of a tungsten-containing copper interconnect barrier layer with a sidewall step coverage of greater than 30%.
  • a dielectric substrate e.g., a single or dual-damascene copper interconnect substrate
  • the presence of the thin TiN nucleation layer on the dielectric substrate enables ample adhesion of the tungsten- containing copper interconnect barrier layer to the dielectric substrate.
  • Exemplary embodiments of a copper interconnect barrier layer structure includes either a thin titanium-nitride (TiN) nucleation layer or a thin tantalum-nitride (TaN) nucleation layer disposed directly on a dielectric structure (e.g., a single or dual-damascene copper interconnect dielectric structure).
  • TiN titanium-nitride
  • TaN tantalum-nitride
  • the copper interconnect barrier layer structure also includes a tungsten-containing copper interconnect barrier layer (e.g., a W or W X N copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl (W[CO] 6 ) or a WTVbased ALD technique.
  • a tungsten-containing copper interconnect barrier layer e.g., a W or W X N copper interconnect barrier layer
  • a fluorine-free tungsten-containing gas e.g., tungsten hexacarbonyl (W[CO] 6
  • WTVbased ALD technique e.g., tungsten hexacarbonyl
  • FIGs. 1A-1C are simplified cross-sectional diagrams of a substrate as it is subjected to a sequence of steps in a process according to one exemplary embodiment of the present invention
  • FIG. 2 is a flow chart illustrating the process to which the substrate shown in FIGs. 1A-1C is subjected;
  • FIG. 3 is a cross-sectional diagram illustrating a resulting structure in a process according to another exemplary embodiment of the present invention.
  • FIG. 4 is a cross-sectional diagram illustrating an exemplary embodiment of a structure according to the present invention.
  • FIGs. 1A-1C and FIG. 2 are simplified cross-sectional diagrams of a substrate and a flow chart, respectively, illustrating a sequence of steps in a process for forming a copper interconnect barrier layer on a substrate 10 in accordance with an exemplary embodiment of the present invention.
  • a thin titanium-nitride (TiN) nucleation layer 12 is first deposited on substrate 10, as shown in FIG. 1 A and charted in step 50 of FIG. 2.
  • Thin TiN nucleation layer 12 is referred to as a "nucleation" layer since it serves to promote (e.g., by serving as a growth site) the subsequent formation of a tungsten-containing copper interconnect barrier layer (described in further detail below) thereon.
  • Substrate 10 can be any substrate employed in copper interconnect technology.
  • substrate 10 can be a single or dual-damascene copper interconnect substrate that includes a dielectric layer with a trench and/or via formed therein.
  • Substrate 10 is depicted in FIG. 1A as including a dielectric layer 14 (e.g., a silicon dioxide [SiO 2 ] layer or a low-k dielectric layer) overlying a metal layer 16 (e.g., a copper layer).
  • Dielectric layer 14 is also depicted in FIGs. 1A-1C as having a via and/or trench opening 18 formed therein.
  • the thickness of thin TiN nucleation layer 12 is predetermined to improve nucleation and, therefore, superior sidewall step coverage (i.e., greater than 30%) of the subsequently formed tungsten-containing copper interconnect barrier layer.
  • the thickness (measured on the sidewall of via and/or trench opening 18) can be, for example, in a range from 3 angstroms to 50 angstroms. A thickness in the range of 3 angstroms to 10 angstroms can, however, minimize deposition time, as well as the combined thickness of thin TiN nucleation layer 12 and the subsequently formed tungsten-containing copper interconnect barrier layer.
  • Thin TiN nucleation layer 12 can be deposited by conventional techniques, such as the thermal decomposition of a titanium and nitrogen-containing precursor (e.g., tetra-d ⁇ me yl-amino-titanium [TDMATj or tetra-diemyl-amino-titamum [TDEAT]).
  • a thin tantalum-nitride (TaN) nucleation layer is deposited on substrate 10m instead of TiN layer 12.
  • Such a thin TaN nucleation layer can be deposited by conventional techniques, such as the thermal decomposition of a tantalum and nitrogen- containing precursor (e.g., penta-dimethyl-amino-tantalum [PDMAT] or penta-ethyl-methyl- amino-tantalum [PEMAT]).
  • a tantalum and nitrogen- containing precursor e.g., penta-dimethyl-amino-tantalum [PDMAT] or penta-ethyl-methyl- amino-tantalum [PEMAT]
  • Conventional techniques for the deposition of a thin TiN nucleation layer using the thermal decomposition of TDMAT can be conducted at, for example, a temperature in the range of 300 °C to 450 °C and a pressure in the range of 0.1 Torr to 50 Torr.
  • the thin TiN nucleation layer can also be deposited using an Atomic Layer Deposition (ALD) technique employing TDMAT (or, alternatively, TDEAT) and NH 3 .
  • ALD Atomic Layer Deposition
  • Such an ALD technique is conducted using an alternating exposure of substrate 10 to TDAT (or TDEAT) and NH 3 at a temperature in the range of 100 °C to 350 °C and a pressure in the range of 0.1 Torr to 50 Torr.
  • conventional techniques for the deposition of a thin TaN nucleation layer using the thermal decomposition of PDMAT or PEMAT can be conducted.
  • the thin TaN can also be deposited using an ALD technique employing PDMAT or PEMAT.
  • tungsten-containing copper interconnect barrier layer 20 is formed on thin TiN nucleation layer 12, as illustrated in FIG. IB (see also step 52 of FIG. 2).
  • tungsten-containing copper interconnect barrier layer 20 can be beneficially formed using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl W(CO) 6 ).
  • CVD Chemical Vapor Deposition
  • tungsten-free tungsten-containing gas e.g., tungsten hexacarbonyl W(CO) 6
  • This embodiment employs a fluorine-free tungsten-containing gas is employed to avoid fluorine-induced corrosion of either copper layers in substrate 10 or subsequently deposited copper layers.
  • tungsten-containing copper interconnect barrier layer 20 can be a tungsten (W) copper interconnect barrier layer formed using a CVD technique that employs W(CO) 6 or a tungsten-nitride (W X N) copper interconnect barrier layer formed using a CVD technique that employs W(CO) 6 and ammonia (NH 3 ).
  • W and W X N layers are generally known in the field to be good barriers against the diffusion of copper.
  • tungsten-nitride (W X ) copper interconnect barrier layer employing W(CO) 6 and conducted at a temperature in the range of 250 °C to 400 °C, a pressure of approximately 100 milli-Torr to 50-Torr and with a W(CO) 6 flow rate in the range of 10 seem to 20 seem have also been demonstrated to provide a sidewall step coverage of greater than 30% in features with an aspect ratio of 4:1 and greater when utilized in processes according to the present invention.
  • tungsten-containing copper interconnect barrier layer 20 is formed using a WF ⁇ -based Atomic Layer Deposition (ALD) technique.
  • ALD Atomic Layer Deposition
  • tungsten-containing copper interconnect barrier layer 20 is formed using an alternating exposure of thin TiN nucleation layer 12 to tungsten hexafluoride (WF ⁇ ) and silane (S1H 4 ).
  • WF ⁇ -based ALD technique can employ an alternating exposure of thin TiN nucleation layer 12 to WFg and B 2 I ⁇ 6 .
  • WTVbased ALD techniques can be conducted, for example, at a temperature in the range of 200 °C to 400 °C and a pressure in the range of 0.1 Torr to 50 Torr.
  • alternating exposure refers to a process sequence wherein (a) thin TiN nucleation layer 12 is initially exposed to WF ⁇ ; (b) the WF 6 is purged from the reactor in which the WTVbased ALD technique is being conducted; (c) the thin TiN nucleation layer (which has been exposed to F ⁇ ) is exposed to SilL (or B 2 H 6 ); (d) the S1H 4 (or B 2 H 6 ) is purged from the reactor; and (e) steps (a) through (d) are then repeated as necessary to form the desired tungsten-containing copper interconnect barrier layer.
  • Tungsten- ⁇ ntaining copper interconnect barrier layer 20 can be of any thickness that serves as a suitable diffusion barrier to copper.
  • the combined thickness of thin TiN nucleation layer 12 and tungsten-containing copper interconnect barrier layer 20 (as measured on the sidewall of via and/or trench opening 18) can be, for example, in the range of 10 angstroms to 250 angstroms.
  • the thickness of tungsten-containing copper interconnect barrier layer 20 alone is, for example, in the range of 7 angstroms to 247 angstroms.
  • a copper interconnect layer 22 can be optionally deposited on tungsten- containing copper interconnect barrier layer 20 using conventional techniques (e.g., copper electroplating). See step 54 of FIG. 2 and the resultant structure illustrated in FIG. lC.
  • Processes according to the present invention provide several benefits over conventional processes for the formation of a copper interconnect barrier layer.
  • conventional CVD methods that deposit a copper interconnect barrier layer (e.g., a W X N layer) directly onto a substrate have poor sidewall step coverage.
  • One benefit of the present invention is the unexpected finding that preparing the substrate, by depositing a thin TiN nucleation layer thereon, facilitated the formation of a tungsten- containing copper interconnect barrier layer with a sidewall step coverage of greater than 30%.
  • Sidewall step coverage can be further improved by forming the tungsten-containing copper interconnect barrier layer immediately after the deposition of the thin TiN nucleation layer and without exposing the thin TiN nucleation layer to atmospheric conditions (e.g., air at atmospheric pressure).
  • a further benefit is that the presence of the thin TiN nucleation layer serves to improve the adhesion of the tungsten-containing copper interconnect barrier layer (e.g., a tungsten or tungsten-nitride copper interconnect barrier layer) to dielectric substrates. This is in sharp contrast to the relatively poor adhesion obtained by the conventional formation of a tungsten (W) or tungsten-nitride (W X N) copper interconnect barrier layer directly on a dielectric substrate.
  • W tungsten
  • W X N tungsten-nitride
  • the formation of the tungsten-containing copper interconnect barrier layer 20 results in the simultaneous formation of a titanium-nitride-tungsten interfacial layer 24 between tungsten-containing copper interconnect barrier layer and dielectric layer 14.
  • the resultant structure is illustrated in FIG. 3.
  • This ternary titanium-nitride-tungsten interfacial layer 24 provides an additional barrier to the unwanted diffusion of copper.
  • titanium-mtride-tungsten interfacial layer 24 is dependent on the thickness of thin TiN nucleation layer 12 and the process conditions used to form the tungsten-containing copper interconnect barrier layer 20. However, when a W copper interconnect barrier layer is formed using W(CO) 6 at a temperature in the range of 300 °C to 500 °C or when a W X N copper interconnect barrier layer is formed using W(CO) 6 and NH 3 at a temperature in the range of 250 °C to 400 °C, a titanium-mtride-tungsten interfacial layer will be formed.
  • FIG. 4 is a cross-sectional diagram illustrating an exemplary embodiment of a copper interconnect barrier layer structure 100 on a dielectric substrate according to the present invention.
  • Copper interconnect barrier layer structure 100 includes a thin titanium- nitride (TiN) nucleation layer 102 disposed directly on the dielectric substrate 106.
  • Thin TiN nucleation layer 102 can be formed using conventional techniques as described above in regard to FIGs. 1A-1C with a typical thickness in the range of 3 angstroms to 20 angstroms.
  • Copper interconnect barrier layer structure 100 also includes a tungsten- containing copper interconnect barrier layer 108 formed on thin TiN nucleation layer 102.
  • Tungsten-containing copper interconnect barrier layer 108 can be formed, for example, using a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl [W(CO) 6 ]) or a F ⁇ -based ALD deposition technique.
  • tungsten- containing copper interconnect barrier layer 108 can be, for example, a tungsten (W) or tungsten-nitride (W X N) copper interconnect barrier layer.
  • copper interconnect barrier layer structure 100 can also include a titanium-nitride-tungsten interfacial layer (not shown in FIG.
  • This ternary interfacial layer serves as an additional barrier to the unwanted diffusion of copper. Since copper interconnect barrier layer structure 100 is produced by forming tungsten-containing copper interconnect barrier layer 108 on thin TiN nucleation layer 102, the sidewall step coverage for features (e.g., vias and/or trenches) in the dielectric substrate can be greater than 30%.

Abstract

A method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [WxN] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage and ample adhesion to underlying dielectric layers. The method includes first depositing a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer (12) on the substrate, followed by the formation of a tungsten-containing copper interconnect barrier layer (20) (e.g., a W orWxN copper interconnect barrier layer) overlying the substrate. The tungsten-containing copper interconnect barrier layer can, for example, be formed using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl [W(CO)6]) or a WF6-based Atomic Layer Deposition (ALD) technique. The presence of a thin TiN (or TaN) nucleation layer facilitates the formation of a tungsten-­containing copper interconnect barrier layer with a sidewall step coverage of greater than 30% and ample adhesion to dielectric layers. A copper interconnect barrier layer structure includes a thin titanium-nitride (TiN) (or tantalum nitride [TAN]) nucleation layer disposed directly on the dielectric substrate (e.g., a single or dual-damascene copper interconnect dielectric substrate). The copper interconnect barrier layer structure also includes a tungsten-­containing copper interconnect barrier layer (e.g., a W or WxN copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., [W(CO)6]) or a WF6-based ALD technique.

Description

COPPER INTERCONNECT BARRIER LAYER STRUCTURE AND
FORMATION METHOD
BACKGROUND OF THE INVENTION
The use of single and dual-damascene copper interconnect structures in semiconductor device manufacturing has received a great deal of attention due to the decreased resistivity of copper interconnects in comparison to aluminum interconnects. In typical single and dual-damascene copper interconnect structures, a tantalum (Ta) or tantalum-nitride (TaN) copper interconnect barrier layer is employed to prevent the undesirable diffusion of copper into, for example, a dielectric layer. A conventional copper interconnect structure formation process includes first depositing a tantalum or tantalum- nitride copper interconnect barrier layer on a substrate (e.g., a single or dual-damascene dielectric substrate) using Physical Vapor Deposition (PVD), followed by the deposition of a copper seed layer. A bulk copper layer is subsequently formed on the copper seed layer by electroplating.
In the field of semiconductor device manufacturing, deposition processes can be characterized by sidewall step coverage and aspect ratio. Sidewall step coverage is defined as the ratio of a layer's thickness on the sidewall of a feature to that on a horizontal surface adjacent to the feature and is generally expressed as a percentage. Aspect ratio is defined as the height of a feature (e.g., a via or trench) versus the width of the feature. A drawback of the conventional copper interconnect process described above is the low sidewall step coverage obtained for Ta and TaN copper interconnect barrier layers formed using PND techniques. For high aspect ratio via and trench features (e.g., aspect ratios of 4: 1 and greater), the sidewall step coverage obtained with PVD techniques is typically around 10%. Tungsten-nitride (WXΝ) layers deposited using Chemical Vapor Deposition (CVD) have been investigated as potential copper interconnect barrier layers. WXN layers deposited by CVD, however, can also suffer from undesirably low sidewall step coverage, as well as from poor adhesion to underlying dielectric layers. Still needed in the field, therefore, is a method for forming a copper interconnect barrier layer with a high sidewall step coverage (i.e., a sidewall step coverage of greater than 30% to conformal) and ample adhesion to an underlying dielectric layer. Also needed is a copper interconnect barrier structure that includes a copper interconnect barrier layer with a high sidewall step coverage.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [WXN] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage. The method also results in ample adhesion of the togsten-containing copper interconnect barrier layer to any underlying dielectric layers.
A process according to one exemplary embodiment of the present invention includes first depositing, on a substrate, a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer, followed by the formation of a tungsten-containing copper interconnect barrier layer (e.g., a W or WXN copper interconnect barrier layer) thereon. The tungsten-containing copper interconnect barrier layer can be formed, for example, using a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl W[CO]6). Alternatively, the tungsten-containing copper interconnect barrier layer can be formed using a WF6-based Atomic Layer Deposition (ALD) technique.
The presence of a thin TiN (or TaN) nucleation layer on the substrate facilitates formation of a tungsten-containing copper interconnect barrier layer with a sidewall step coverage of greater than 30%. In addition, for the circumstance of a dielectric substrate (e.g., a single or dual-damascene copper interconnect substrate), the presence of the thin TiN nucleation layer on the dielectric substrate enables ample adhesion of the tungsten- containing copper interconnect barrier layer to the dielectric substrate.
Exemplary embodiments of a copper interconnect barrier layer structure according to the present invention includes either a thin titanium-nitride (TiN) nucleation layer or a thin tantalum-nitride (TaN) nucleation layer disposed directly on a dielectric structure (e.g., a single or dual-damascene copper interconnect dielectric structure). The copper interconnect barrier layer structure also includes a tungsten-containing copper interconnect barrier layer (e.g., a W or WXN copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl (W[CO]6) or a WTVbased ALD technique.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the invention are utilized, and the accompanying drawings (in which like numerals are used to designate like elements).
BRIEF DESCRIPTION OF THE DRAWINGS FIGs. 1A-1C are simplified cross-sectional diagrams of a substrate as it is subjected to a sequence of steps in a process according to one exemplary embodiment of the present invention;
FIG. 2 is a flow chart illustrating the process to which the substrate shown in FIGs. 1A-1C is subjected; FIG. 3 is a cross-sectional diagram illustrating a resulting structure in a process according to another exemplary embodiment of the present invention; and
FIG. 4 is a cross-sectional diagram illustrating an exemplary embodiment of a structure according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
FIGs. 1A-1C and FIG. 2 are simplified cross-sectional diagrams of a substrate and a flow chart, respectively, illustrating a sequence of steps in a process for forming a copper interconnect barrier layer on a substrate 10 in accordance with an exemplary embodiment of the present invention. A thin titanium-nitride (TiN) nucleation layer 12 is first deposited on substrate 10, as shown in FIG. 1 A and charted in step 50 of FIG. 2. Thin TiN nucleation layer 12 is referred to as a "nucleation" layer since it serves to promote (e.g., by serving as a growth site) the subsequent formation of a tungsten-containing copper interconnect barrier layer (described in further detail below) thereon.
Substrate 10 can be any substrate employed in copper interconnect technology. For example, substrate 10 can be a single or dual-damascene copper interconnect substrate that includes a dielectric layer with a trench and/or via formed therein. Substrate 10 is depicted in FIG. 1A as including a dielectric layer 14 (e.g., a silicon dioxide [SiO2] layer or a low-k dielectric layer) overlying a metal layer 16 (e.g., a copper layer). Dielectric layer 14 is also depicted in FIGs. 1A-1C as having a via and/or trench opening 18 formed therein.
The thickness of thin TiN nucleation layer 12 is predetermined to improve nucleation and, therefore, superior sidewall step coverage (i.e., greater than 30%) of the subsequently formed tungsten-containing copper interconnect barrier layer. The thickness (measured on the sidewall of via and/or trench opening 18) can be, for example, in a range from 3 angstroms to 50 angstroms. A thickness in the range of 3 angstroms to 10 angstroms can, however, minimize deposition time, as well as the combined thickness of thin TiN nucleation layer 12 and the subsequently formed tungsten-containing copper interconnect barrier layer.
Thin TiN nucleation layer 12 can be deposited by conventional techniques, such as the thermal decomposition of a titanium and nitrogen-containing precursor (e.g., tetra-d^me yl-amino-titanium [TDMATj or tetra-diemyl-amino-titamum [TDEAT]). In an alternative embodiment, a thin tantalum-nitride (TaN) nucleation layer is deposited on substrate 10m instead of TiN layer 12. Such a thin TaN nucleation layer can be deposited by conventional techniques, such as the thermal decomposition of a tantalum and nitrogen- containing precursor (e.g., penta-dimethyl-amino-tantalum [PDMAT] or penta-ethyl-methyl- amino-tantalum [PEMAT]). Conventional techniques for the deposition of a thin TiN nucleation layer using the thermal decomposition of TDMAT can be conducted at, for example, a temperature in the range of 300 °C to 450 °C and a pressure in the range of 0.1 Torr to 50 Torr. The thin TiN nucleation layer can also be deposited using an Atomic Layer Deposition (ALD) technique employing TDMAT (or, alternatively, TDEAT) and NH3. Such an ALD technique is conducted using an alternating exposure of substrate 10 to TDAT (or TDEAT) and NH3 at a temperature in the range of 100 °C to 350 °C and a pressure in the range of 0.1 Torr to 50 Torr. Similarly, conventional techniques for the deposition of a thin TaN nucleation layer using the thermal decomposition of PDMAT or PEMAT can be conducted. The thin TaN can also be deposited using an ALD technique employing PDMAT or PEMAT.
Next, a tungsten-containing copper interconnect barrier layer 20 is formed on thin TiN nucleation layer 12, as illustrated in FIG. IB (see also step 52 of FIG. 2). In one embodiment, tungsten-containing copper interconnect barrier layer 20 can be beneficially formed using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl W(CO)6). This embodiment employs a fluorine-free tungsten-containing gas is employed to avoid fluorine-induced corrosion of either copper layers in substrate 10 or subsequently deposited copper layers. In this embodiment, tungsten-containing copper interconnect barrier layer 20 can be a tungsten (W) copper interconnect barrier layer formed using a CVD technique that employs W(CO)6 or a tungsten-nitride (WXN) copper interconnect barrier layer formed using a CVD technique that employs W(CO)6 and ammonia (NH3). W and WXN layers are generally known in the field to be good barriers against the diffusion of copper. In addition, it has been determined that techniques for the formation of a tungsten (W) copper interconnect barrier layer employing W(CO)6 and conducted at a temperature in the range of 300 °C to 500 °C, a pressure in the range of 10 milli-Torr to 200 milli-Torr and with a W(CO)6 flow rate in the range of 2 seem to 20 seem result in a sidewall step coverage of greater than 30% for features with an aspect ratio of 4:1 and greater when utilized in processes according to the present invention. Further, techniques for the formation of a tungsten-nitride (WX ) copper interconnect barrier layer employing W(CO)6 and conducted at a temperature in the range of 250 °C to 400 °C, a pressure of approximately 100 milli-Torr to 50-Torr and with a W(CO)6 flow rate in the range of 10 seem to 20 seem have also been demonstrated to provide a sidewall step coverage of greater than 30% in features with an aspect ratio of 4:1 and greater when utilized in processes according to the present invention.
In another embodiment, tungsten-containing copper interconnect barrier layer 20 is formed using a WFβ-based Atomic Layer Deposition (ALD) technique. In such a F6- based ALD technique, tungsten-containing copper interconnect barrier layer 20 is formed using an alternating exposure of thin TiN nucleation layer 12 to tungsten hexafluoride (WFβ) and silane (S1H4). Alternatively, the WFβ-based ALD technique can employ an alternating exposure of thin TiN nucleation layer 12 to WFg and B2IΪ6. These WTVbased ALD techniques can be conducted, for example, at a temperature in the range of 200 °C to 400 °C and a pressure in the range of 0.1 Torr to 50 Torr. The phrase "alternating exposure" refers to a process sequence wherein (a) thin TiN nucleation layer 12 is initially exposed to WFβ; (b) the WF6 is purged from the reactor in which the WTVbased ALD technique is being conducted; (c) the thin TiN nucleation layer (which has been exposed to Fβ) is exposed to SilL (or B2H6); (d) the S1H4 (or B2H6) is purged from the reactor; and (e) steps (a) through (d) are then repeated as necessary to form the desired tungsten-containing copper interconnect barrier layer.
Tungsten-∞ntaining copper interconnect barrier layer 20 can be of any thickness that serves as a suitable diffusion barrier to copper. However, in order to accommodate copper interconnect structures with small feature sizes (e.g., trenches with a width of 0.30 microns or less), the combined thickness of thin TiN nucleation layer 12 and tungsten-containing copper interconnect barrier layer 20 (as measured on the sidewall of via and/or trench opening 18) can be, for example, in the range of 10 angstroms to 250 angstroms. Accordingly, to accommodate a thin TiN nucleation layer with a minimum thickness of 3 angstroms, the thickness of tungsten-containing copper interconnect barrier layer 20 alone is, for example, in the range of 7 angstroms to 247 angstroms.
Next, a copper interconnect layer 22 can be optionally deposited on tungsten- containing copper interconnect barrier layer 20 using conventional techniques (e.g., copper electroplating). See step 54 of FIG. 2 and the resultant structure illustrated in FIG. lC.
Processes according to the present invention provide several benefits over conventional processes for the formation of a copper interconnect barrier layer. As noted in the Background section, conventional CVD methods that deposit a copper interconnect barrier layer (e.g., a WXN layer) directly onto a substrate have poor sidewall step coverage. One benefit of the present invention is the unexpected finding that preparing the substrate, by depositing a thin TiN nucleation layer thereon, facilitated the formation of a tungsten- containing copper interconnect barrier layer with a sidewall step coverage of greater than 30%. Sidewall step coverage can be further improved by forming the tungsten-containing copper interconnect barrier layer immediately after the deposition of the thin TiN nucleation layer and without exposing the thin TiN nucleation layer to atmospheric conditions (e.g., air at atmospheric pressure). A further benefit is that the presence of the thin TiN nucleation layer serves to improve the adhesion of the tungsten-containing copper interconnect barrier layer (e.g., a tungsten or tungsten-nitride copper interconnect barrier layer) to dielectric substrates. This is in sharp contrast to the relatively poor adhesion obtained by the conventional formation of a tungsten (W) or tungsten-nitride (WXN) copper interconnect barrier layer directly on a dielectric substrate.
In a process for forming a copper interconnect barrier layer on a substrate 10 according to another exemplary embodiment of the present invention, the formation of the tungsten-containing copper interconnect barrier layer 20 results in the simultaneous formation of a titanium-nitride-tungsten interfacial layer 24 between tungsten-containing copper interconnect barrier layer and dielectric layer 14. The resultant structure is illustrated in FIG. 3. This ternary titanium-nitride-tungsten interfacial layer 24 provides an additional barrier to the unwanted diffusion of copper.
The thickness and composition of titanium-mtride-tungsten interfacial layer 24 is dependent on the thickness of thin TiN nucleation layer 12 and the process conditions used to form the tungsten-containing copper interconnect barrier layer 20. However, when a W copper interconnect barrier layer is formed using W(CO)6 at a temperature in the range of 300 °C to 500 °C or when a WXN copper interconnect barrier layer is formed using W(CO)6 and NH3 at a temperature in the range of 250 °C to 400 °C, a titanium-mtride-tungsten interfacial layer will be formed.
FIG. 4 is a cross-sectional diagram illustrating an exemplary embodiment of a copper interconnect barrier layer structure 100 on a dielectric substrate according to the present invention. Copper interconnect barrier layer structure 100 includes a thin titanium- nitride (TiN) nucleation layer 102 disposed directly on the dielectric substrate 106. Thin TiN nucleation layer 102 can be formed using conventional techniques as described above in regard to FIGs. 1A-1C with a typical thickness in the range of 3 angstroms to 20 angstroms. Copper interconnect barrier layer structure 100 also includes a tungsten- containing copper interconnect barrier layer 108 formed on thin TiN nucleation layer 102. Tungsten-containing copper interconnect barrier layer 108 can be formed, for example, using a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl [W(CO)6]) or a Fβ-based ALD deposition technique. Furthermore, tungsten- containing copper interconnect barrier layer 108 can be, for example, a tungsten (W) or tungsten-nitride (WXN) copper interconnect barrier layer. Depending on the process conditions used to form the tungsten-containing copper interconnect barrier layer, copper interconnect barrier layer structure 100 can also include a titanium-nitride-tungsten interfacial layer (not shown in FIG. 4) between the thin TiN nucleation layer and the tungsten- containing copper interconnect barrier layer. This ternary interfacial layer serves as an additional barrier to the unwanted diffusion of copper. Since copper interconnect barrier layer structure 100 is produced by forming tungsten-containing copper interconnect barrier layer 108 on thin TiN nucleation layer 102, the sidewall step coverage for features (e.g., vias and/or trenches) in the dielectric substrate can be greater than 30%.
The gas flow rates recited and described above are optimized for deposition processes run in a CVD xZ chamber manufactured by Applied Materials and outfitted for 200 mm wafers. A person of ordinary skill in the art will recognize that the rates at which various precursor gases in the process are introduced are in part chamber specific and will vary if chambers or other design and/or volume are employed.
It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

WHAT IS CLAIMED IS:
1. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin titanium-nitride nucleation layer and a thin tantalum- nitride nucleation layer on the substrate; and
forming a tungsten-containing copper interconnect barrier layer overlying the substrate.
2. The method of claim 1 wherein the forming step uses a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas.
3. The method of claim 1 wherein the forming step uses a WFβ-based Atomic Layer Deposition (ALD) technique.
4. The method of claim 1 , further comprising during the depositing step, depositing one of a titanium-nitride nucleation layer and a tantalum-nitride nucleation layer directly on a dual-damascene copper interconnect substrate.
5. The method of claim 4, further comprising during the depositing step, depositing one of a titanium-nitride nucleation layer and a tantalum-nitride nucleation layer directly on the dual-damascene copper interconnect substrate with at least one trench formed therein.
6. The method of claim 1 , further comprising during the depositing step, depositing one of a titanium-nitride nucleation layer and a tantalum-mtride nucleation layer directly on a single-damascene copper interconnect substrate.
7. The method of claim 1, further comprising after the forming step, depositing a copper interconnect layer on the tungsten-containing copper interconnect barrier layer.
8. The method of claim 1 , wherein the forming step forms a tungsten copper interconnect barrier layer.
9. The method of claim 8 wherein the depositing step deposits a thin titanium-nitride nucleation layer on the substrate.
10. The method of claim 9, wherein the forming step results in the formation of a titanium-nitride-tungsten interfacial layer between the tungsten layer and the substrate.
11. The method of claim 2, wherein the forming step uses a CVD technique that employs tungsten hexacarbonyl as the fluorine-free tungsten-containing gas to form the tungsten copper interconnect barrier layer.
12. The method of claim 11, wherein the forming step uses a CVD technique conducted at a temperature in the range of 300 °C to 500 °C and a pressure in the range of 10 milli-Torr to 200 milli-Torr.
13. The method of claim 1 , wherein the forming step forms a tungsten- nitride copper interconnect barrier layer.
14. The method of claim 13 wherein the depositing step deposits a thin titanium-nitride nucleation layer on the substrate.
15. The method of claim 14, wherein the forming step results in the formation of a titanium-nitride-tungsten interfacial layer between the tungsten-nitride copper interconnect barrier layer and the substrate.
16. The method of claim 13 , wherein the forming step uses a CVD technique that employs tungsten hexacarbonyl and ammonia to from the tungsten-nitride copper interconnect barrier layer.
17. The method of claim 16, wherein the forming step uses a CVD technique conducted at a temperature in the range of 250 °C to 400 °C and a pressure of approximately 100 milli-Torr to 50 Torr.
18. The method of claim 1 wherein the depositing step deposits a thin titanium-nitride nucleation layer on the substrate.
19. The method of claim 18, further comprising during the depositing step, depositing a thin titanium-nitride nucleation layer with a thickness in the range of 3 angstroms to 20 angstroms.
20. The method of claim 19, further comprising during the depositing step, depositing a thin titanium-nitride nucleation layer using thermal decomposition of a titanium and nitrogen-containing compound.
21. The method of claim 20, further comprising during the depositing step, depositing a thin titanium-nitride nucleation layer using thermal decomposition of tetra- dimethyl-amino-titanium (TDMAT).
22. The method of claim 20, further comprising during the depositing step, depositing a thin titanium-nitride nucleation layer using thermal decomposition of tetra- diethyl-ammo-titanium (TDEAT).
23. The method of claim 1 , wherein the depositing and forming steps are conducted without exposing the thin TiN nucleation layer to atmospheric conditions.
24. The method of claim 1 wherein the depositing step deposits a thin tantalum-mtride nucleation layer on the substrate.
25. The method of claim 24, further comprising during the depositing step, depositing a thin tantalum nitride nucleation layer using thermal decomposition of a tantalum and nitrogen-containing compound.
26. The method of claim 25, further comprising during the depositing step, depositing a thin tantalum-nitride nucleation layer using thermal decomposition of tantalum containing chemical selected from the group consisting of penta-dimethyl-amino-tantalum (PDMAT) and penta-ethyl-methyl-amino-tantalum (PEMAT).
27. A copper interconnect barrier layer structure on a dielectric substrate comprising:
a thin titanium-nitride nucleation layer disposed directly on the dielectric substrate;
a tungsten-containing copper interconnect barrier layer formed on the thin titanium-nitride nucleation layer; and a copper interconnect layer on the tungsten-containing copper interconnect barrier layer.
28. The copper interconnect barrier layer structure of claim 27, further comprising a titanium-nitride-tungsten transition layer between the titanium-nitride layer and the tungsten-containing copper interconnect barrier layer.
29. The copper interconnect barrier layer structure of claim 27, wherein the tungsten-containing layer is a tungsten copper interconnect barrier layer.
30. The copper interconnect barrier layer structure of claim 27, wherein the tungsten-containing layer is a tungsten-nitride copper interconnect barrier layer.
31. The copper interconnect barrier layer structure of claim 27, wherein the dielectric substrate has a feature with at least one sidewall and the tungsten-containing copper interconnect barrier layer has a sidewall step coverage of at least 30%.
32. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin tantalum-nitride nucleation layer and a thin titanium- nitride nucleation layer on the substrate; and
forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas.
33. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin tantalum-mtride nucleation layer and a thin titanium- nitride nucleation layer on the substrate; and
forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a Chemical Vapor Deposition (CVD) techmque that employs tungsten hexacarbonyl.
34. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin tantalum-nitride nucleation layer and a thin titanium- nitride nucleation layer on the substrate;
forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a Chemical Vapor Deposition (CVD) technique that employs tungsten hexacarbonyl; and depositing a copper interconnect layer on the timgsten-containing copper interconnect barrier layer.
35. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin tantalum-nitride nucleation layer and a thin titanium- nitride nucleation layer on the substrate; and
forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a WFβ-based Atomic Layer Deposition (ALD) technique.
36. A method for the formation of a copper interconnect barrier layer on a substrate comprising:
depositing one of a thin tantalum-nitride nucleation layer and a thin titanium- nitride nucleation layer on the substrate;
forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a WFβ-based Atomic Layer Deposition (ALD) technique; and
depositing a copper interconnect layer on the tungsten-containing copper interconnect barrier layer.
37. A method for the formation of a copper interconnect barrier layer on a substrate comprising: depositing one of a thin tantalum-nitride nucleation layer and a thin titanium- nitride nucleation layer on the substrate; forming a tungsten-containing copper interconnect barrier layer overlying the substrate using a WFβ-based Atomic Layer Deposition (ALD) technique conducted at a temperature in the range of 200 °C to 400 °C and a pressure in the range of 0.1 Torr to 50 Torr; and
depositing a copper interconnect layer on the tungsten-containing copper interconnect barrier layer.
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Families Citing this family (462)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7188142B2 (en) 2000-11-30 2007-03-06 Applied Materials, Inc. Dynamic subject information generation in message services of distributed object systems in a semiconductor assembly line facility
US6596643B2 (en) * 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US6649517B2 (en) * 2001-05-18 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Copper metal structure for the reduction of intra-metal capacitance
US7589017B2 (en) * 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7262125B2 (en) * 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7955972B2 (en) * 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7005372B2 (en) 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7141494B2 (en) 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7698012B2 (en) 2001-06-19 2010-04-13 Applied Materials, Inc. Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing
US7160739B2 (en) 2001-06-19 2007-01-09 Applied Materials, Inc. Feedback control of a chemical mechanical polishing device providing manipulation of removal rate profiles
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
WO2003029515A2 (en) 2001-07-16 2003-04-10 Applied Materials, Inc. Formation of composite tungsten films
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US6950716B2 (en) * 2001-08-13 2005-09-27 Applied Materials, Inc. Dynamic control of wafer processing paths in semiconductor manufacturing processes
US6984198B2 (en) * 2001-08-14 2006-01-10 Applied Materials, Inc. Experiment management system, method and medium
US20030037090A1 (en) * 2001-08-14 2003-02-20 Koh Horne L. Tool services layer for providing tool service functions in conjunction with tool functions
KR20030025494A (en) * 2001-09-21 2003-03-29 삼성전자주식회사 Semiconductor device having contact between ruthenium layer and metal layer and method for manufacturing the same
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
TW589684B (en) * 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US7204886B2 (en) 2002-11-14 2007-04-17 Applied Materials, Inc. Apparatus and method for hybrid chemical processing
US7780785B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
US6916398B2 (en) 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US7081271B2 (en) 2001-12-07 2006-07-25 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6911391B2 (en) * 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6972267B2 (en) 2002-03-04 2005-12-06 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US7279432B2 (en) 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US6716744B2 (en) * 2002-05-06 2004-04-06 Sharp Laboratories Of America, Inc. Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper
US7041335B2 (en) * 2002-06-04 2006-05-09 Applied Materials, Inc. Titanium tantalum nitride silicide layer
US6838125B2 (en) 2002-07-10 2005-01-04 Applied Materials, Inc. Method of film deposition using activated precursor gases
US7186385B2 (en) 2002-07-17 2007-03-06 Applied Materials, Inc. Apparatus for providing gas to a processing chamber
US20040074438A1 (en) * 2002-10-22 2004-04-22 Taiwan Semiconductor Manufacturing Company Novel method to reduce resistivity of atomic layer tungsten chemical vapor depositon
AU2003290932A1 (en) 2002-11-15 2004-06-15 Applied Materials, Inc. Method, system and medium for controlling manufacture process having multivariate input parameters
WO2004064147A2 (en) 2003-01-07 2004-07-29 Applied Materials, Inc. Integration of ald/cvd barriers with porous low k materials
US20040175926A1 (en) * 2003-03-07 2004-09-09 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having a barrier-lined opening
US6955986B2 (en) * 2003-03-27 2005-10-18 Asm International N.V. Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7211508B2 (en) 2003-06-18 2007-05-01 Applied Materials, Inc. Atomic layer deposition of tantalum based barrier materials
US7754604B2 (en) * 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
KR100528069B1 (en) * 2003-09-02 2005-11-15 동부아남반도체 주식회사 Semiconductor Device And Method For Manufacturing The Same
US6958291B2 (en) * 2003-09-04 2005-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect with composite barrier layers and method for fabricating the same
US20050252449A1 (en) 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US8323754B2 (en) 2004-05-21 2012-12-04 Applied Materials, Inc. Stabilization of high-k dielectric materials
KR100602087B1 (en) * 2004-07-09 2006-07-14 동부일렉트로닉스 주식회사 Semiconductor device and method of manufacturing the same
US7241686B2 (en) * 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA
US7166544B2 (en) * 2004-09-01 2007-01-23 Applied Materials, Inc. Method to deposit functionally graded dielectric films via chemical vapor deposition using viscous precursors
US7429402B2 (en) 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US20070066060A1 (en) * 2005-09-19 2007-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and fabrication methods thereof
TWI329135B (en) 2005-11-04 2010-08-21 Applied Materials Inc Apparatus and process for plasma-enhanced atomic layer deposition
US7658802B2 (en) * 2005-11-22 2010-02-09 Applied Materials, Inc. Apparatus and a method for cleaning a dielectric film
US7798096B2 (en) 2006-05-05 2010-09-21 Applied Materials, Inc. Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
KR100760920B1 (en) * 2006-07-25 2007-09-21 동부일렉트로닉스 주식회사 Method for forming copper metal lines in semiconductor integrated circuit devices
US7521379B2 (en) 2006-10-09 2009-04-21 Applied Materials, Inc. Deposition and densification process for titanium nitride barrier layers
US7655556B2 (en) 2007-03-23 2010-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for semiconductor devices
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
WO2009064530A2 (en) * 2007-08-30 2009-05-22 Washington State University Research Foundation Semiconductive materials and associated uses thereof
US7585762B2 (en) 2007-09-25 2009-09-08 Applied Materials, Inc. Vapor deposition processes for tantalum carbide nitride materials
US7678298B2 (en) 2007-09-25 2010-03-16 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US7824743B2 (en) 2007-09-28 2010-11-02 Applied Materials, Inc. Deposition processes for titanium nitride barrier and aluminum
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US7767572B2 (en) * 2008-02-21 2010-08-03 Applied Materials, Inc. Methods of forming a barrier layer in an interconnect structure
US7618893B2 (en) * 2008-03-04 2009-11-17 Applied Materials, Inc. Methods of forming a layer for barrier applications in an interconnect structure
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8291857B2 (en) 2008-07-03 2012-10-23 Applied Materials, Inc. Apparatuses and methods for atomic layer deposition
US7919409B2 (en) * 2008-08-15 2011-04-05 Air Products And Chemicals, Inc. Materials for adhesion enhancement of copper film on diffusion barriers
US8551885B2 (en) * 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US8491967B2 (en) 2008-09-08 2013-07-23 Applied Materials, Inc. In-situ chamber treatment and deposition process
US8146896B2 (en) 2008-10-31 2012-04-03 Applied Materials, Inc. Chemical precursor ampoule for vapor deposition processes
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
US20100151676A1 (en) * 2008-12-16 2010-06-17 Applied Materials, Inc. Densification process for titanium nitride layer for submicron applications
US8053861B2 (en) * 2009-01-26 2011-11-08 Novellus Systems, Inc. Diffusion barrier layers
KR101570044B1 (en) * 2009-03-17 2015-11-20 삼성전자주식회사 Semiconductor device having low resistance buried metal gate electrode structure and method of manufacturing the same
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US8623733B2 (en) * 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9653353B2 (en) 2009-08-04 2017-05-16 Novellus Systems, Inc. Tungsten feature fill
US8802201B2 (en) 2009-08-14 2014-08-12 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US8207062B2 (en) * 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US8709948B2 (en) * 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
CN103443906B (en) 2011-03-04 2016-03-30 应用材料公司 The method of contact clean
US8912096B2 (en) 2011-04-28 2014-12-16 Applied Materials, Inc. Methods for precleaning a substrate prior to metal silicide fabrication process
US9312155B2 (en) 2011-06-06 2016-04-12 Asm Japan K.K. High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
US10854498B2 (en) 2011-07-15 2020-12-01 Asm Ip Holding B.V. Wafer-supporting device and method for producing same
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US9218961B2 (en) 2011-09-19 2015-12-22 Applied Materials, Inc. Methods of forming a metal containing layer on a substrate with high uniformity and good profile control
WO2013063260A1 (en) 2011-10-28 2013-05-02 Applied Materials, Inc. High temperature tungsten metallization process
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US8927423B2 (en) 2011-12-16 2015-01-06 Applied Materials, Inc. Methods for annealing a contact metal layer to form a metal silicidation layer
US8586479B2 (en) 2012-01-23 2013-11-19 Applied Materials, Inc. Methods for forming a contact metal layer in semiconductor devices
US20130224964A1 (en) * 2012-02-28 2013-08-29 Asm Ip Holding B.V. Method for Forming Dielectric Film Containing Si-C bonds by Atomic Layer Deposition Using Precursor Containing Si-C-Si bond
US9330939B2 (en) 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
KR101306813B1 (en) 2012-05-09 2013-09-10 한국화학연구원 Novel tungsten aminoamide azide compounds, preparation method thereof and process for the formation of thin films using the same
KR101306811B1 (en) 2012-05-09 2013-09-10 한국화학연구원 Novel tungsten aminoamide halide compounds, preparation method thereof and process for the formation of thin films using the same
KR101306812B1 (en) 2012-05-09 2013-09-10 한국화학연구원 Novel tungsten silylamide compounds, preparation method thereof and process for the formation of thin films using the same
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9543163B2 (en) 2013-08-20 2017-01-10 Applied Materials, Inc. Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process
JP6488284B2 (en) 2013-09-27 2019-03-20 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ How to enable seamless cobalt gap filling
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US10179947B2 (en) 2013-11-26 2019-01-15 Asm Ip Holding B.V. Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US10683571B2 (en) 2014-02-25 2020-06-16 Asm Ip Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
US9508561B2 (en) 2014-03-11 2016-11-29 Applied Materials, Inc. Methods for forming interconnection structures in an integrated cluster system for semicondcutor applications
US10167557B2 (en) 2014-03-18 2019-01-01 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US10858737B2 (en) 2014-07-28 2020-12-08 Asm Ip Holding B.V. Showerhead assembly and components thereof
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US9528185B2 (en) 2014-08-22 2016-12-27 Applied Materials, Inc. Plasma uniformity control by arrays of unit cell plasmas
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US9657845B2 (en) 2014-10-07 2017-05-23 Asm Ip Holding B.V. Variable conductance gas distribution apparatus and method
KR102300403B1 (en) 2014-11-19 2021-09-09 에이에스엠 아이피 홀딩 비.브이. Method of depositing thin film
KR102263121B1 (en) 2014-12-22 2021-06-09 에이에스엠 아이피 홀딩 비.브이. Semiconductor device and manufacuring method thereof
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9478415B2 (en) 2015-02-13 2016-10-25 Asm Ip Holding B.V. Method for forming film having low resistance and shallow junction depth
US10529542B2 (en) 2015-03-11 2020-01-07 Asm Ip Holdings B.V. Cross-flow reactor and method
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10600673B2 (en) 2015-07-07 2020-03-24 Asm Ip Holding B.V. Magnetic susceptor to baseplate seal
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US9899291B2 (en) 2015-07-13 2018-02-20 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10087525B2 (en) 2015-08-04 2018-10-02 Asm Ip Holding B.V. Variable gap hard stop design
US9647114B2 (en) 2015-08-14 2017-05-09 Asm Ip Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US9892913B2 (en) 2016-03-24 2018-02-13 Asm Ip Holding B.V. Radial and thickness control via biased multi-port injection settings
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US10190213B2 (en) 2016-04-21 2019-01-29 Asm Ip Holding B.V. Deposition of metal borides
US10865475B2 (en) 2016-04-21 2020-12-15 Asm Ip Holding B.V. Deposition of metal borides and silicides
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
KR102592471B1 (en) 2016-05-17 2023-10-20 에이에스엠 아이피 홀딩 비.브이. Method of forming metal interconnection and method of fabricating semiconductor device using the same
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US10714385B2 (en) 2016-07-19 2020-07-14 Asm Ip Holding B.V. Selective deposition of tungsten
US10381226B2 (en) 2016-07-27 2019-08-13 Asm Ip Holding B.V. Method of processing substrate
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10177025B2 (en) 2016-07-28 2019-01-08 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR102532607B1 (en) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and method of operating the same
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel
US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10643904B2 (en) 2016-11-01 2020-05-05 Asm Ip Holdings B.V. Methods for forming a semiconductor device and related semiconductor device structures
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10435790B2 (en) 2016-11-01 2019-10-08 Asm Ip Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10134757B2 (en) 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
US10340135B2 (en) 2016-11-28 2019-07-02 Asm Ip Holding B.V. Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
KR20180068582A (en) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
KR20180070971A (en) 2016-12-19 2018-06-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10867788B2 (en) 2016-12-28 2020-12-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
KR20180087661A (en) 2017-01-25 2018-08-02 삼성전자주식회사 Semiconductor device including conductive structure having nucleation structure and method of forming the same
US10655221B2 (en) 2017-02-09 2020-05-19 Asm Ip Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10283353B2 (en) 2017-03-29 2019-05-07 Asm Ip Holding B.V. Method of reforming insulating film deposited on substrate with recess pattern
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10103040B1 (en) 2017-03-31 2018-10-16 Asm Ip Holding B.V. Apparatus and method for manufacturing a semiconductor device
USD830981S1 (en) 2017-04-07 2018-10-16 Asm Ip Holding B.V. Susceptor for semiconductor substrate processing apparatus
KR102457289B1 (en) 2017-04-25 2022-10-21 에이에스엠 아이피 홀딩 비.브이. Method for depositing a thin film and manufacturing a semiconductor device
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US10892156B2 (en) 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
US10446393B2 (en) 2017-05-08 2019-10-15 Asm Ip Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10504742B2 (en) 2017-05-31 2019-12-10 Asm Ip Holding B.V. Method of atomic layer etching using hydrogen plasma
US10886123B2 (en) 2017-06-02 2021-01-05 Asm Ip Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10199267B2 (en) 2017-06-30 2019-02-05 Lam Research Corporation Tungsten nitride barrier layer deposition
US10685834B2 (en) 2017-07-05 2020-06-16 Asm Ip Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10312055B2 (en) 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10605530B2 (en) 2017-07-26 2020-03-31 Asm Ip Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
WO2019036292A1 (en) 2017-08-14 2019-02-21 Lam Research Corporation Metal fill process for three-dimensional vertical nand wordline
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
KR102405723B1 (en) 2017-08-18 2022-06-07 어플라이드 머티어리얼스, 인코포레이티드 High pressure and high temperature annealing chamber
US10236177B1 (en) 2017-08-22 2019-03-19 ASM IP Holding B.V.. Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures
USD900036S1 (en) 2017-08-24 2020-10-27 Asm Ip Holding B.V. Heater electrical connector and adapter
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
KR102491945B1 (en) 2017-08-30 2023-01-26 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US10607895B2 (en) 2017-09-18 2020-03-31 Asm Ip Holdings B.V. Method for forming a semiconductor device structure comprising a gate fill metal
KR102630301B1 (en) 2017-09-21 2024-01-29 에이에스엠 아이피 홀딩 비.브이. Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same
US10844484B2 (en) 2017-09-22 2020-11-24 Asm Ip Holding B.V. Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10923344B2 (en) 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
SG11202003355QA (en) 2017-11-11 2020-05-28 Micromaterials Llc Gas delivery system for high pressure processing chamber
KR102443047B1 (en) 2017-11-16 2022-09-14 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US10910262B2 (en) 2017-11-16 2021-02-02 Asm Ip Holding B.V. Method of selectively depositing a capping layer structure on a semiconductor device structure
CN111432920A (en) 2017-11-17 2020-07-17 应用材料公司 Condenser system for high pressure processing system
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
JP7206265B2 (en) 2017-11-27 2023-01-17 エーエスエム アイピー ホールディング ビー．ブイ． Equipment with a clean mini-environment
CN111316417B (en) 2017-11-27 2023-12-22 阿斯莫Ip控股公司 Storage device for storing wafer cassettes for use with batch ovens
US10290508B1 (en) 2017-12-05 2019-05-14 Asm Ip Holding B.V. Method for forming vertical spacers for spacer-defined patterning
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TW202325889A (en) 2018-01-19 2023-07-01 荷蘭商Ａｓｍ 智慧財產控股公司 Deposition method
CN111630203A (en) 2018-01-19 2020-09-04 Asm Ip私人控股有限公司 Method for depositing gap filling layer by plasma auxiliary deposition
USD903477S1 (en) 2018-01-24 2020-12-01 Asm Ip Holdings B.V. Metal clamp
US11018047B2 (en) 2018-01-25 2021-05-25 Asm Ip Holding B.V. Hybrid lift pin
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US10535516B2 (en) 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
WO2019158960A1 (en) 2018-02-14 2019-08-22 Asm Ip Holding B.V. A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10731249B2 (en) 2018-02-15 2020-08-04 Asm Ip Holding B.V. Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
US10658181B2 (en) 2018-02-20 2020-05-19 Asm Ip Holding B.V. Method of spacer-defined direct patterning in semiconductor fabrication
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
WO2019173006A1 (en) 2018-03-09 2019-09-12 Applied Materials, Inc. High pressure annealing process for metal containing materials
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
CN111936664A (en) 2018-03-19 2020-11-13 应用材料公司 Method for depositing a coating on an aerospace component
KR102646467B1 (en) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
KR102501472B1 (en) 2018-03-30 2023-02-20 에이에스엠 아이피 홀딩 비.브이. Substrate processing method
EP3784815A4 (en) 2018-04-27 2021-11-03 Applied Materials, Inc. Protection of components from corrosion
JP2021523292A (en) 2018-05-03 2021-09-02 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ How to deposit tungsten and other metals in a 3D NAND structure
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
KR20190128558A (en) 2018-05-08 2019-11-18 에이에스엠 아이피 홀딩 비.브이. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
TW202349473A (en) 2018-05-11 2023-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
TW202013553A (en) 2018-06-04 2020-04-01 荷蘭商Ａｓｍ 智慧財產控股公司 Wafer handling chamber with moisture reduction
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
CN112292478A (en) 2018-06-27 2021-01-29 Asm Ip私人控股有限公司 Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
KR20200002519A (en) 2018-06-29 2020-01-08 에이에스엠 아이피 홀딩 비.브이. Method for depositing a thin film and manufacturing a semiconductor device
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10767789B2 (en) 2018-07-16 2020-09-08 Asm Ip Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US10883175B2 (en) 2018-08-09 2021-01-05 Asm Ip Holding B.V. Vertical furnace for processing substrates and a liner for use therein
US10829852B2 (en) 2018-08-16 2020-11-10 Asm Ip Holding B.V. Gas distribution device for a wafer processing apparatus
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11009339B2 (en) 2018-08-23 2021-05-18 Applied Materials, Inc. Measurement of thickness of thermal barrier coatings using 3D imaging and surface subtraction methods for objects with complex geometries
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
US10847365B2 (en) 2018-10-11 2020-11-24 Asm Ip Holding B.V. Method of forming conformal silicon carbide film by cyclic CVD
US10811256B2 (en) 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10559458B1 (en) 2018-11-26 2020-02-11 Asm Ip Holding B.V. Method of forming oxynitride film
US10636705B1 (en) 2018-11-29 2020-04-28 Applied Materials, Inc. High pressure annealing of metal gate structures
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
TW202037745A (en) 2018-12-14 2020-10-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming device structure, structure formed by the method and system for performing the method
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Ａｓｍ 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
CN111524788B (en) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 Method for topologically selective film formation of silicon oxide
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
TW202104632A (en) 2019-02-20 2021-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
US11482533B2 (en) 2019-02-20 2022-10-25 Asm Ip Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
JP2020136678A (en) 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー Method for filing concave part formed inside front surface of base material, and device
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
KR20200108243A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Structure Including SiOC Layer and Method of Forming Same
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
JP2020167398A (en) 2019-03-28 2020-10-08 エーエスエム・アイピー・ホールディング・ベー・フェー Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
EP3959356A4 (en) 2019-04-26 2023-01-18 Applied Materials, Inc. Methods of protecting aerospace components against corrosion and oxidation
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
US11794382B2 (en) 2019-05-16 2023-10-24 Applied Materials, Inc. Methods for depositing anti-coking protective coatings on aerospace components
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． Wafer boat handling device, vertical batch furnace, and method
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
KR20200141002A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Method of using a gas-phase reactor system including analyzing exhausted gas
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
US11697879B2 (en) 2019-06-14 2023-07-11 Applied Materials, Inc. Methods for depositing sacrificial coatings on aerospace components
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー．ブイ． Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
TW202121506A (en) 2019-07-19 2021-06-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming topology-controlled amorphous carbon polymer film
CN112309843A (en) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 Selective deposition method for achieving high dopant doping
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
CN112323048B (en) 2019-08-05 2024-02-09 Asm Ip私人控股有限公司 Liquid level sensor for chemical source container
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー．ブイ． Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210024420A (en) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11466364B2 (en) 2019-09-06 2022-10-11 Applied Materials, Inc. Methods for forming protective coatings containing crystallized aluminum oxide
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Ａｓｍ Ｉｐ控股公司 Substrate processing device, and substrate processing method
TW202115273A (en) 2019-10-10 2021-04-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
KR20210065848A (en) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー．ブイ． Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210078405A (en) 2019-12-17 2021-06-28 에이에스엠 아이피 홀딩 비.브이. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming structures including a vanadium or indium layer
TW202146882A (en) 2020-02-04 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
TW202146715A (en) 2020-02-17 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for growing phosphorous-doped silicon layer and system of the same
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Ａｓｍ Ｉｐ控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132605A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Vertical batch furnace assembly comprising a cooling gas supply
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
US11898243B2 (en) 2020-04-24 2024-02-13 Asm Ip Holding B.V. Method of forming vanadium nitride-containing layer
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
KR20210143653A (en) 2020-05-19 2021-11-29 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11519066B2 (en) 2020-05-21 2022-12-06 Applied Materials, Inc. Nitride protective coatings on aerospace components and methods for making the same
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing device
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing method
EP4175772A1 (en) 2020-07-03 2023-05-10 Applied Materials, Inc. Methods for refurbishing aerospace components
KR20220010438A (en) 2020-07-17 2022-01-25 에이에스엠 아이피 홀딩 비.브이. Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method and system for depositing molybdenum layers
TW202212623A (en) 2020-08-26 2022-04-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of depositing material on stepped structure
TW202217037A (en) 2020-10-22 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
TW202235675A (en) 2020-11-30 2022-09-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Injector, and substrate processing apparatus
US11946137B2 (en) 2020-12-16 2024-04-02 Asm Ip Holding B.V. Runout and wobble measurement fixtures
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
US20220270979A1 (en) * 2021-02-24 2022-08-25 Applied Materials, Inc. Formation of metal vias on metal lines
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
CN113690178A (en) * 2021-08-23 2021-11-23 长江先进存储产业创新中心有限责任公司 Method for manufacturing metal conductive structure
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994775A (en) * 1997-09-17 1999-11-30 Lsi Logic Corporation Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
WO2001027347A1 (en) * 1999-10-15 2001-04-19 Asm Microchemistry Oy Method of depositing transition metal nitride thin films
WO2001029891A1 (en) * 1999-10-15 2001-04-26 Asm America, Inc. Conformal lining layers for damascene metallization
US6258707B1 (en) * 1999-01-07 2001-07-10 International Business Machines Corporation Triple damascence tungsten-copper interconnect structure

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5429989A (en) 1994-02-03 1995-07-04 Motorola, Inc. Process for fabricating a metallization structure in a semiconductor device
US5789312A (en) 1996-10-30 1998-08-04 International Business Machines Corporation Method of fabricating mid-gap metal gates compatible with ultra-thin dielectrics
US5989623A (en) 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization
US5972179A (en) * 1997-09-30 1999-10-26 Lucent Technologies Inc. Silicon IC contacts using composite TiN barrier layer
US6130145A (en) 1998-01-21 2000-10-10 Siemens Aktiengesellschaft Insitu doped metal policide
JP2926132B1 (en) 1998-01-23 1999-07-28 セイコーインスツルメンツ株式会社 Secondary ion image observation method using focused ion beam
US6107199A (en) 1998-10-24 2000-08-22 International Business Machines Corporation Method for improving the morphology of refractory metal thin films
US6184138B1 (en) 1999-09-07 2001-02-06 Chartered Semiconductor Manufacturing Ltd. Method to create a controllable and reproducible dual copper damascene structure
US6191029B1 (en) 1999-09-09 2001-02-20 United Silicon Incorporated Damascene process
US6143641A (en) 2000-01-26 2000-11-07 National Semiconductor Corporation Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US6455421B1 (en) * 2000-07-31 2002-09-24 Applied Materials, Inc. Plasma treatment of tantalum nitride compound films formed by chemical vapor deposition
US6432821B1 (en) * 2000-12-18 2002-08-13 Intel Corporation Method of copper electroplating

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994775A (en) * 1997-09-17 1999-11-30 Lsi Logic Corporation Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
US6258707B1 (en) * 1999-01-07 2001-07-10 International Business Machines Corporation Triple damascence tungsten-copper interconnect structure
WO2001027347A1 (en) * 1999-10-15 2001-04-19 Asm Microchemistry Oy Method of depositing transition metal nitride thin films
WO2001029891A1 (en) * 1999-10-15 2001-04-26 Asm America, Inc. Conformal lining layers for damascene metallization

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BRAUD F ET AL: "Ultra thin diffusion barriers for Cu interconnections at the gigabit generation and beyond" MICROELECTRONIC ENGINEERING, ELSEVIER PUBLISHERS BV., AMSTERDAM, NL, vol. 33, no. 1, 1997, pages 293-300, XP004054524 ISSN: 0167-9317 *
PAULEAU Y: "CHEMICAL VAPOUR DEPOSITION OF TUNGSTEN FILMS FOR METALLIZATION OF INTEGRATED CIRCUITS" THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, vol. 122, no. 3, December 1984 (1984-12), pages 243-258, XP000837415 ISSN: 0040-6090 *

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