WO2003030262A2 - Silicon-on-insulator high voltage device structure - Google Patents

Silicon-on-insulator high voltage device structure Download PDF

Info

Publication number
WO2003030262A2
WO2003030262A2 PCT/IB2002/003737 IB0203737W WO03030262A2 WO 2003030262 A2 WO2003030262 A2 WO 2003030262A2 IB 0203737 W IB0203737 W IB 0203737W WO 03030262 A2 WO03030262 A2 WO 03030262A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
soi
silicon
stripe
insulator
Prior art date
Application number
PCT/IB2002/003737
Other languages
French (fr)
Other versions
WO2003030262A3 (en
Inventor
Theodore J. Letavic
Mark R. Simpson
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2003533349A priority Critical patent/JP2005505136A/en
Priority to AT02765227T priority patent/ATE440382T1/en
Priority to EP02765227A priority patent/EP1438752B1/en
Priority to DE60233422T priority patent/DE60233422D1/en
Priority to CN028193180A priority patent/CN1561548B/en
Priority to KR1020047004793A priority patent/KR100904785B1/en
Publication of WO2003030262A2 publication Critical patent/WO2003030262A2/en
Publication of WO2003030262A3 publication Critical patent/WO2003030262A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

  • a thin-layer silicon-on-insulator (SOI) high-voltage device structure is provided.
  • This invention relates to semiconductor devices, and more particularly to a thin-layer silicon-on-insulator (SOI) high-voltage device structure which employs multiple three-dimensional metal-oxide semiconductor (MOS) capacitor structures to achieve multidimensional depletion of the drift charge to improve the breakdown-voltage specific "on" resistance figure-of-merit across a wide range of application voltages.
  • SOI silicon-on-insulator
  • MOS metal-oxide semiconductor
  • the device could support high voltages with higher levels of charge in the drift region, without extensive thermal oxidation process steps.
  • a MOS dielectric can be used to support higher sustainable electric fields. Such a construction can be used to improve the breakdown voltage specific "on" resistance figure- of-merit.
  • the present invention contemplates a thin-layer silicon-on-insulator (SOI) high voltage device comprising a semiconductor substrate and a three-dimensional MOS multi-capacitor structure which forms a depletable drift region.
  • the three-dimensional MOS multi-capacitor structure includes a striped geometry of parallel thin, SOI stripes, wherein each SOI stripe is individually circumscribed longitudinally by a respective dielectric layer formed on the semiconductor substrate, and a conducting multi-capacitor field plate layer superimposed on top of the respective dielectric layer and between adjacent dielectric layers circumscribing longitudinally adjacent SOI stripes.
  • Fig. 2 illustrates a cross sectional view along the plane 1-1 of the embodiment of Fig. 1.
  • Fig. 3 A illustrates a top view of a lateral diffused metal-oxide semiconductor (LDMOS) device structure of the present invention employing the three-dimensional MOS multi-capacitor structure of Fig. 1.
  • LDMOS lateral diffused metal-oxide semiconductor
  • the exemplary MOS field plate multi-capacitor structure 10 as shown includes two parallel and juxtaposed MOS capacitors 20a and 20b. However, any number of parallel and juxtaposed MOS capacitors can be provided.
  • the MOS field plate multi-capacitor structure 110 of Fig. 3 A includes more than two MOS capacitors, as will be described in more detail later.
  • the dielectric layer 22a has a bottom periphery surface 24a disposed on the semiconductor substrate 12 and its interior periphery surfaces 26a, 26b, 26c and 26d circumscribing the top, bottom and longitudinal exterior periphery surfaces of the SOI stripe 16a.
  • dielectric layer 22b circumscribes the SOI stripe 16b.
  • the dielectric layers 22a and 22b are made of silicon dioxide, also referred to as "oxide.” However, any dielectric with a low dielectric constant could be used.
  • the dielectric layer 22a is comprised of a buried insulating layer 28a having the SOI stripe 16a disposed thereon and a top insulating layer 28b disposed over the top of and longitudinally along the SOI stripe 16a.
  • the SOI stripe 16a is in the form of a geometrically-shaped stripe or strip having a width which is shorter than the width of the buried insulating layer 28a and the top insulating layer 28b.
  • the thicknesses of the SOI stripe 16a, the buried insulating layer 28a and the top insulating layer 28b will be described below in relation to the fabrication process.
  • SOI stripe 16a has a shorter width than the buried insulating layer 28a and the top insulating layer 28b, the top and side periphery surfaces of the SOI stripe 16a are longitudinally circumscribed by the top insulating layer 28b while the bottom surface is interfaced by the buried insulating layer 28a.
  • dielectric layer 22b is comprised of buried insulating layer 28a' and top insulating layer 28b'.
  • the MOS field plate multi-capacitor structure 10 further includes a conducting multi-capacitor field plate layer 30 superimposed longitudinally on top of the dielectric layers 22a and 22b and between the adjacent dielectric layers 22a and 22b circumscribing longitudinally adjacent SOI stripes 16a and 16b.
  • the conducting multi-capacitor field plate layer 30 includes a plurality of longitudinal dividing field plates 32a, 32b and 32c and a top longitudinal field plate 38.
  • field plate 32b is shown dividing SOI stripe 16a and 16b and their respective dielectric layers 22a and 22b, respectively.
  • field plates 32a, and 32c would also divide other adjacent dielectric layers, as will be described in more detail with respect to Figs. GS. 3 A and 3B.
  • the number of longitudinal dividing field plates is dependent on the number of SOI stripes.
  • the length of the plurality of longitudinal dividing field plates 32a, 32b and 32c is slightly shorter than the length of the dielectric layers 22a and 22b.
  • the end edges of the plurality of longitudinal dividing field plates 32a, 32b and 32c are layered with dielectric which may be part of dielectric layer 22a and/or dielectric layer 22b, as best seen in Fig. 3A.
  • the MOS field plate multi- capacitor structure 10 includes MOS capacitor 20a, hich is embodied by the longitudinal dividing field plates 32a and 32b, SOI stripe 16a and dielectric layer 22a, and MOS capacitor 20b,which is embodied by the longitudinal dividing field plates 32b and 32c, SOI stripe 16b and dielectric layer 22b. Furthermore, since the MOS capacitors 20a and 20b are juxtaposed the common field plate, namely, the top longitudinal field plate 38 is shared thereby.
  • the field plates 32a, 32b, 32c and 38 are made of a metallic or a polysilicon material. In the embodiment of Figs.
  • the geometric shape of the SOI stripe 16a does not have to be square or rectangular. Instead, other geometries such as, without limitation, circular or cylindrical geometries are also usable as long as the cross-section of the SOI stripe 16a and the conducting multi-capacitor field plate layer 30 are of similar cross-section and are concentrically scaled.
  • the thickness Tl of the buried insulating layer 28a is substantially the same as the thickness T2 of the top insulating layer 28b.
  • the thickness T3 of the SOI stripe 16a centers it between the buried insulating layer 28a and the top insulating layer 28b.
  • the SOI stripe 16b is centered between the buried insulating layer 28a' and the top insulating layer 28b'.
  • An advantage of the three-dimensional MOS multi-capacitor structure 10 is a higher charge slope in the drift region as compared to the prior art for the same breakdown voltage. While not wishing to be bound by theory, the three-dimensional MOS multi- capacitor structure 10 leads to an improvement in specific "on" resistance and saturated current flow.
  • Step 2 of the fabrication process includes doping the SOI layer 16 with a graded charge profile to set a desired monotonic electric field in the drift region.
  • Step 3 of the fabrication process includes anisotropically etching the SOI layer 16 to form the individual SOI stripes 16a and 16b on the top surface (solid line 1) of the buried insulating layer 28 ' .
  • Step 4 of the fabrication process includes subsequent deposition of the dielectric to form a top insulating layer 28.
  • Step 6 of the fabrication process includes a refill process with a metal or polysilicon to create the conducting multi-capacitor field plate layer 30 which is superimposed on top of the dielectric layers 22a and 22b and between adjacent dielectric layers 22a and 22b which longitudmally circumscribe adjacent SOI stripes 16a and 16b.
  • the conduction electrode (conducting multi-capacitor field plate layer 30) of the MOS multi-capacitor structure 10 completely encapsulates, longitudinally, the graded- doped SOI stripes 16a and 16b, thus depleting the SOI stripes 16a or 16b from all sides upon application of a bias voltage.
  • Step 7 of the fabrication process includes electrically shorting the conducting multi-capacitor field plate layer 30 to the semiconductor substrate 12.
  • the resultant structure of the fabrication process is thin drift-region SOI stripes 16a and 16b which are completely enclosed longitudinally by a conducting multi- capacitor field plate layer 30, resulting in three-dimensional depletion upon application of a bias voltage between each individual SOI stripe 16a and 16b and the field plates 32a, 32b, 32c and 38 of their individual MOS capacitors 20a and 20b, respectively.
  • the three-dimensional MOS multi-capacitor structure 10 of the present invention is not limited to high voltage applications.
  • Appropriate selection of the dielectric layer thickness Tl and SOI layer thickness T3 results in three-dimensional structures which can be used for blocking voltages from 2 to 1000N.
  • the design as a function of application voltage, involves selecting a maximum electric field strength in the silicon (semiconductor substrate layer 12) and the dielectric layers.
  • Fig. 4 illustrates a simpler alternative embodiment for fabricating the MOS field plate multi-capacitor structure 10'.
  • the MOS field plate multi-capacitor structure 10' is similar to the MOS field plate multi-capacitor structure 10 of the embodiment of Figs. 1 and 2, except that vias are not etched through the buried insulating layer 28' to the substrate 12. Instead, the buried insulation layer 28' is a solid layer and does not have vias etched therethrough.
  • the MOS field plate multi-capacitor structure 10' includes MOS capacitors 20a' and 20b' which extend to the top surface of the buried insulating layer 28'.
  • the longitudinal dividing field plates 32a', 32b' and 32c' extend down to the top surface of the buried insulating layer 28'.
  • a via (route) 42' is created through the top insulating layer 28 forming the parallel top insulating layers 28b and 28b' down to the buried insulating layer 28'.
  • the embodiment of Fig. 4 is somewhat easier to construct than the one shown in Fig. 1, since the deposition of the conducting multi-capacitor field plate layer 30' is not extended to the substrate 12.
  • the thin-layer SOI device 100 is a lateral double- diffused metal-oxide semiconductor (LDMOS) device.
  • LDMOS metal-oxide semiconductor field effect transistor
  • the LDMOS device includes a three-dimensional MOS multi- capacitor structures 110.
  • the three-dimensional MOS multi-capacitor structure 110 is essentially the same as the three-dimensional MOS multi-capacitor structure 10 shown in Figs. 1 and 2, except that it includes SOI stripes 116a, 116b, 116c, and 116d and MOS capacitors 120a, 120b, 120c and 120d (MOS capacitors 120a and 120d shown in part). Furthermore, the top longitudinal field plate 138 of the conducting multi-capacitor field plate layer 130 is partially shown and the dielectric layers 122a,122b, 122c and 122d are shown cross-hatched and removed over the longitudinal top periphery surface of the SOI stripes 116a, 116b, 116c and 116d for clarity.
  • the LDMOS device includes an SOI layer 116 which extends from drain 160 to source 150 from which the SOI stripes 116a, 116b, 116c, and 116d.
  • the overall contour of the top view of the SOI layer 116 is an "I"-beam configuration.
  • the drain 160 is a shallow N layer which extends along the width Wc of the channel and is also elongated in a plane perpendicular to the longitudinal dividing field plates 132a, 132b, 132c at one end of the SOI stripes 116a, 116b, 116c, and 116d.
  • the LDMOS device further includes a polysilicon gate 140 which is disposed at the other end of the three-dimensional MOS multi-capacitor structure 110 and is elongated in a plane perpendicular to the longitudinal dividing field plates 132a, 132b, 132c.
  • the source 150 is formed by a first shallow N layer 152a and a second shallow P layer 152b, both of which have a width which is substantially the width Wc of the channel.
  • the a polysilicon gate 140, a polysilicon stripe is deposited over an un-etched or unpatterned portion of the SOI layer 116.
  • standard self-aligned process modules are used to form the active channel of the LDMOS device, diffusing a dopant under a self-aligned polysilicon stripe forming the polysilicon gate 140.
  • the three-dimensional MOS multi-capacitor structure 110 is confined to the drift region of the LDMOS device. Furthermore, the LDMOS device is self-terminated in a conventional manner.
  • the thin-layer SOI device 100 is not only limited to MOSFET active devices. Instead other semiconductor devices, such as, without limitation, JFETs, bipolar, merged MOS/bipolar, etc., can be fabricated with this high voltage handling drift region, described herein.
  • the three-dimensional MOS multi-capacitor structure 110' extends from the drain 160' under the polysilicon gate 140' to source 150'.
  • the SOI layer 116' extends through the drain 160' and the source 150'.
  • the polysilicon gate 140' is deposited over the etched SOI stripes 116a', 116b', 116c', and 116d'.
  • Dotted line 125 indicates the end of the dielectric layers 122a', 122b', 122c' and 122d' and the conducting multi-capacitor field plate layer 130.
  • the three-dimensional MOS multi-capacitor structures 110 and 110' of the embodiments of Figs. 3 A and 3B may be designed in accordance with the details of either Fig. 1 or Fig. 4.

Abstract

A thin layer SOI high-voltage device (100) in which the drift charge is depleted using a three-dimensional MOS capacitor structure (10). The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes (16a, 16b). Each SOI stripe (16a and 16b) is individually circumscribed longitudinally by a dielectric layer (22a, 22b) wherein each dielectric layer (22a, 22b) is longitudinally circumscribed by field platesof a conducting multi-capacitor field plate layer (30) which is electrically shorted to the substrate (12). The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe (16a and 16b) and its encapsulating field plates.

Description

A thin-layer silicon-on-insulator (SOI) high-voltage device structure
This invention relates to semiconductor devices, and more particularly to a thin-layer silicon-on-insulator (SOI) high-voltage device structure which employs multiple three-dimensional metal-oxide semiconductor (MOS) capacitor structures to achieve multidimensional depletion of the drift charge to improve the breakdown-voltage specific "on" resistance figure-of-merit across a wide range of application voltages.
There has been various SOI high voltage device structures in which a field plate construction and drift region doping are used to improve the breakdown voltage specific "on" resistance figure-of-merit. Improved "on" resistance for low voltage application has been obtained using trench device structures in bulk silicon technology. Other thin-layer high voltage devices have improved current driving capability.
Recently, multi-dimensional depletion in the drift region has been achieved by inserting shaped PN-junctions into the graded-doped drift region of the device. Thus, the device could support high voltages with higher levels of charge in the drift region, without extensive thermal oxidation process steps. However, there is an alternative structure in which a MOS dielectric can be used to support higher sustainable electric fields. Such a construction can be used to improve the breakdown voltage specific "on" resistance figure- of-merit.
The present invention contemplates a thin-layer silicon-on-insulator (SOI) high voltage device comprising a semiconductor substrate and a three-dimensional MOS multi-capacitor structure which forms a depletable drift region. The three-dimensional MOS multi-capacitor structure includes a striped geometry of parallel thin, SOI stripes, wherein each SOI stripe is individually circumscribed longitudinally by a respective dielectric layer formed on the semiconductor substrate, and a conducting multi-capacitor field plate layer superimposed on top of the respective dielectric layer and between adjacent dielectric layers circumscribing longitudinally adjacent SOI stripes. Embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein: Fig. 1 illustrates a three-dimensional MOS multi-capacitor structure of a drift region of the present invention.
Fig. 2 illustrates a cross sectional view along the plane 1-1 of the embodiment of Fig. 1.
Fig. 3 A illustrates a top view of a lateral diffused metal-oxide semiconductor (LDMOS) device structure of the present invention employing the three-dimensional MOS multi-capacitor structure of Fig. 1.
Fig. 3B illustrates an alternative embodiment of the top view of an LDMOS device structure of the present invention employing the three-dimensional MOS multi- capacitor structure of Fig. 1. Fig. 4 illustrates an alternate embodiment of the three-dimensional MOS multi-capacitor structure of the present invention.
Referring now to Fig. 3 A, an alternate way to achieve multi-dimensional depletion in a thin-layer SOI device 100, such as without limitation, a LDMOS device, is to insert a MOS field plate multi-capacitor structure 110 in the drift region which is biased to deplete the drift charge. This has the same effect on the device's performance as in the prior art, namely providing a higher level of doping in the drift region for a specified breakdown voltage. The MOS field plate multi-capacitor structure 110 has a benefit over the PN-junction depletion method in that the MOS dielectric can support higher electric field strengths prior to breakdown. This means that (ideally) the MOS field plate multi-capacitor scheme would have a better breakdown voltage specific "on" resistance figure-of-merit.
Referring now to Figs. 1 and 2, an exemplary MOS field plate multi-capacitor structure 10 will be described in detail below. The exemplary MOS field plate multi- capacitor structure 10 as shown includes two parallel and juxtaposed MOS capacitors 20a and 20b. However, any number of parallel and juxtaposed MOS capacitors can be provided. The MOS field plate multi-capacitor structure 110 of Fig. 3 A includes more than two MOS capacitors, as will be described in more detail later. The MOS field plate multi-capacitor structure 10 includes a plurality of SOI stripes 16a and 16b, each of which is individually encapsulated, sealed or circumscribed longitudinally by dielectric layers 22a and 22b, respectively, disposed on a semiconductor substrate 12, such as, without limitation, a silicon substrate. The semiconductor substrate 12 may have either a N-type conductivity or a P-type conductivity.
The dielectric layer 22a has a bottom periphery surface 24a disposed on the semiconductor substrate 12 and its interior periphery surfaces 26a, 26b, 26c and 26d circumscribing the top, bottom and longitudinal exterior periphery surfaces of the SOI stripe 16a. Likewise, dielectric layer 22b circumscribes the SOI stripe 16b. In the exemplary embodiment, the dielectric layers 22a and 22b are made of silicon dioxide, also referred to as "oxide." However, any dielectric with a low dielectric constant could be used.
The dielectric layer 22a is comprised of a buried insulating layer 28a having the SOI stripe 16a disposed thereon and a top insulating layer 28b disposed over the top of and longitudinally along the SOI stripe 16a. The SOI stripe 16a is in the form of a geometrically-shaped stripe or strip having a width which is shorter than the width of the buried insulating layer 28a and the top insulating layer 28b. The thicknesses of the SOI stripe 16a, the buried insulating layer 28a and the top insulating layer 28b will be described below in relation to the fabrication process. Since SOI stripe 16a has a shorter width than the buried insulating layer 28a and the top insulating layer 28b, the top and side periphery surfaces of the SOI stripe 16a are longitudinally circumscribed by the top insulating layer 28b while the bottom surface is interfaced by the buried insulating layer 28a. Likewise, dielectric layer 22b is comprised of buried insulating layer 28a' and top insulating layer 28b'.
The MOS field plate multi-capacitor structure 10 further includes a conducting multi-capacitor field plate layer 30 superimposed longitudinally on top of the dielectric layers 22a and 22b and between the adjacent dielectric layers 22a and 22b circumscribing longitudinally adjacent SOI stripes 16a and 16b.
More specifically, the conducting multi-capacitor field plate layer 30 includes a plurality of longitudinal dividing field plates 32a, 32b and 32c and a top longitudinal field plate 38. As can be appreciated, in this exemplary embodiment, field plate 32b is shown dividing SOI stripe 16a and 16b and their respective dielectric layers 22a and 22b, respectively. However, field plates 32a, and 32c would also divide other adjacent dielectric layers, as will be described in more detail with respect to Figs. GS. 3 A and 3B. Moreover, the number of longitudinal dividing field plates is dependent on the number of SOI stripes. The length of the plurality of longitudinal dividing field plates 32a, 32b and 32c is slightly shorter than the length of the dielectric layers 22a and 22b. Thus, the end edges of the plurality of longitudinal dividing field plates 32a, 32b and 32c are layered with dielectric which may be part of dielectric layer 22a and/or dielectric layer 22b, as best seen in Fig. 3A.
In view of the foregoing, it can be readily seen that the MOS field plate multi- capacitor structure 10 includes MOS capacitor 20a, hich is embodied by the longitudinal dividing field plates 32a and 32b, SOI stripe 16a and dielectric layer 22a, and MOS capacitor 20b,which is embodied by the longitudinal dividing field plates 32b and 32c, SOI stripe 16b and dielectric layer 22b. Furthermore, since the MOS capacitors 20a and 20b are juxtaposed the common field plate, namely, the top longitudinal field plate 38 is shared thereby. The field plates 32a, 32b, 32c and 38 are made of a metallic or a polysilicon material. In the embodiment of Figs. 1 and 2, the longitudinal dividing field plates 32a, 32b, and 32c extend down to the semiconductor substrate 12 in via (route) 42 and is electrically shorted to the semiconductor substrate 12. In general there is an ohmatic connection between the longitudinal dividing field plates 32a, 32b, and 32c extending down to the semiconductor substrate 12.
In summary, each SOI stripe 16a and 16b is completely enclosed longitudmally by the MOS field plate capacitor 20a and 20b defined by sequential deposition of a dielectric and a conducting multi-capacitor field plate layer 30. In other words, the end exterior periphery surfaces of both the SOI stripes 16a and 16b are not bounded by the dielectric layers 22a and 22b, respectively, and the conducting multi-capacitor field plate layer 30. Moreover, in the exemplary embodiment, the end exterior periphery surfaces of the dielectric layers 22a and 22b are not bounded by the conducting multi-capacitor field plate layer 30. In profile, the conducting multi-capacitor field plate layer 30 of a single MOS field plate capacitor 20a or 20b has a generally inverted "U"-shaped.
In the exemplary, embodiment, the geometric shape of the SOI stripe 16a (shown in cross-section in Fig. 2) does not have to be square or rectangular. Instead, other geometries such as, without limitation, circular or cylindrical geometries are also usable as long as the cross-section of the SOI stripe 16a and the conducting multi-capacitor field plate layer 30 are of similar cross-section and are concentrically scaled. In the exemplary embodiment, the thickness Tl of the buried insulating layer 28a is substantially the same as the thickness T2 of the top insulating layer 28b. The thickness T3 of the SOI stripe 16a centers it between the buried insulating layer 28a and the top insulating layer 28b. Likewise, the SOI stripe 16b is centered between the buried insulating layer 28a' and the top insulating layer 28b'.
An advantage of the three-dimensional MOS multi-capacitor structure 10 is a higher charge slope in the drift region as compared to the prior art for the same breakdown voltage. While not wishing to be bound by theory, the three-dimensional MOS multi- capacitor structure 10 leads to an improvement in specific "on" resistance and saturated current flow.
The fabrication process of the three-dimensional MOS multi-capacitor structure 10 will now be described in detail below. Step 1 of the fabrication process includes selecting the thicknesses Tl and T3 for the buried insulating layer 28' and the SOI layer 16 (which includes the area between the solid line 1 and the line 1' shown in phantom) for a specific application voltage. Initially the SOI layer 16 extends over the buried insulating layer 28'. In the exemplary embodiment, for a application voltage of 700N, the SOI layer 16 has a 1.0 micron thickness (T3) and the buried insulating layer 28' has a thickness of 3.0 microns (Tl).
Step 2 of the fabrication process includes doping the SOI layer 16 with a graded charge profile to set a desired monotonic electric field in the drift region.
Step 3 of the fabrication process includes anisotropically etching the SOI layer 16 to form the individual SOI stripes 16a and 16b on the top surface (solid line 1) of the buried insulating layer 28 ' .
Step 4 of the fabrication process includes subsequent deposition of the dielectric to form a top insulating layer 28.
Step 5 of the fabrication process includes etching in the center of the top insulating layer 28 and the buried insulating layer 28', between adjacent SOI stripes 16a and 16b, a trench-type geometry to create and expose a via (route) 42 to the substrate 12 thereby forming parallel top insulating layers 28b and 28b' and parallel buried insulating layers 28a and 28a' for MOS capacitors 20a and 20b, respectively. As can be appreciated, a via would be created in the top insulating layer 28 and the buried insulating layer 28' between any two adjacent SOI stripes. Thus, vias are created for field plates 32a and 32c to extend to substrate 12.
Step 6 of the fabrication process includes a refill process with a metal or polysilicon to create the conducting multi-capacitor field plate layer 30 which is superimposed on top of the dielectric layers 22a and 22b and between adjacent dielectric layers 22a and 22b which longitudmally circumscribe adjacent SOI stripes 16a and 16b. The conduction electrode (conducting multi-capacitor field plate layer 30) of the MOS multi-capacitor structure 10 completely encapsulates, longitudinally, the graded- doped SOI stripes 16a and 16b, thus depleting the SOI stripes 16a or 16b from all sides upon application of a bias voltage. Step 7 of the fabrication process includes electrically shorting the conducting multi-capacitor field plate layer 30 to the semiconductor substrate 12.
The resultant structure of the fabrication process is thin drift-region SOI stripes 16a and 16b which are completely enclosed longitudinally by a conducting multi- capacitor field plate layer 30, resulting in three-dimensional depletion upon application of a bias voltage between each individual SOI stripe 16a and 16b and the field plates 32a, 32b, 32c and 38 of their individual MOS capacitors 20a and 20b, respectively.
The three-dimensional MOS multi-capacitor structure 10 of the present invention is not limited to high voltage applications. Appropriate selection of the dielectric layer thickness Tl and SOI layer thickness T3 results in three-dimensional structures which can be used for blocking voltages from 2 to 1000N. In general, the design, as a function of application voltage, involves selecting a maximum electric field strength in the silicon (semiconductor substrate layer 12) and the dielectric layers.
Fig. 4 illustrates a simpler alternative embodiment for fabricating the MOS field plate multi-capacitor structure 10'. The MOS field plate multi-capacitor structure 10' is similar to the MOS field plate multi-capacitor structure 10 of the embodiment of Figs. 1 and 2, except that vias are not etched through the buried insulating layer 28' to the substrate 12. Instead, the buried insulation layer 28' is a solid layer and does not have vias etched therethrough.
The MOS field plate multi-capacitor structure 10' includes MOS capacitors 20a' and 20b' which extend to the top surface of the buried insulating layer 28'. The longitudinal dividing field plates 32a', 32b' and 32c' extend down to the top surface of the buried insulating layer 28'. A via (route) 42' is created through the top insulating layer 28 forming the parallel top insulating layers 28b and 28b' down to the buried insulating layer 28'. As can be appreciated, the embodiment of Fig. 4 is somewhat easier to construct than the one shown in Fig. 1, since the deposition of the conducting multi-capacitor field plate layer 30' is not extended to the substrate 12. In this embodiment, there is a metal- to-dielectric or insulator connection between the conducting multi-capacitor field plate layer 30' and the buried insulating layer 28'. Referring now to Fig. 3 A, a top view of the thin-layer SOI device 100, is shown. In the exemplary embodiment, the thin-layer SOI device 100 is a lateral double- diffused metal-oxide semiconductor (LDMOS) device. Hence, the description herein will be related to the structure of the LDMOS device which is a metal-oxide semiconductor field effect transistor (MOSFET). The LDMOS device includes a three-dimensional MOS multi- capacitor structures 110. The three-dimensional MOS multi-capacitor structure 110 is essentially the same as the three-dimensional MOS multi-capacitor structure 10 shown in Figs. 1 and 2, except that it includes SOI stripes 116a, 116b, 116c, and 116d and MOS capacitors 120a, 120b, 120c and 120d (MOS capacitors 120a and 120d shown in part). Furthermore, the top longitudinal field plate 138 of the conducting multi-capacitor field plate layer 130 is partially shown and the dielectric layers 122a,122b, 122c and 122d are shown cross-hatched and removed over the longitudinal top periphery surface of the SOI stripes 116a, 116b, 116c and 116d for clarity.
The LDMOS device includes an SOI layer 116 which extends from drain 160 to source 150 from which the SOI stripes 116a, 116b, 116c, and 116d. The overall contour of the top view of the SOI layer 116 is an "I"-beam configuration. The drain 160 is a shallow N layer which extends along the width Wc of the channel and is also elongated in a plane perpendicular to the longitudinal dividing field plates 132a, 132b, 132c at one end of the SOI stripes 116a, 116b, 116c, and 116d. The LDMOS device further includes a polysilicon gate 140 which is disposed at the other end of the three-dimensional MOS multi-capacitor structure 110 and is elongated in a plane perpendicular to the longitudinal dividing field plates 132a, 132b, 132c. The source 150 is formed by a first shallow N layer 152a and a second shallow P layer 152b, both of which have a width which is substantially the width Wc of the channel. In this embodiment, the a polysilicon gate 140, a polysilicon stripe is deposited over an un-etched or unpatterned portion of the SOI layer 116. hi the exemplary embodiment, standard self-aligned process modules (drain 160 and source 150) are used to form the active channel of the LDMOS device, diffusing a dopant under a self-aligned polysilicon stripe forming the polysilicon gate 140. In the embodiment of Fig. 3A, the three-dimensional MOS multi-capacitor structure 110 is confined to the drift region of the LDMOS device. Furthermore, the LDMOS device is self-terminated in a conventional manner.
As can be appreciated, the thin-layer SOI device 100 is not only limited to MOSFET active devices. Instead other semiconductor devices, such as, without limitation, JFETs, bipolar, merged MOS/bipolar, etc., can be fabricated with this high voltage handling drift region, described herein.
Referring now to Fig. 3B, in an alternate embodiment of the thin-layer SOI device 100', the three-dimensional MOS multi-capacitor structure 110' extends from the drain 160' under the polysilicon gate 140' to source 150'. The SOI layer 116' extends through the drain 160' and the source 150'. The polysilicon gate 140' is deposited over the etched SOI stripes 116a', 116b', 116c', and 116d'. Dotted line 125 indicates the end of the dielectric layers 122a', 122b', 122c' and 122d' and the conducting multi-capacitor field plate layer 130. The embodiment of Fig. 3B, such an arrangement has the benefit of higher channel periphery, as the polysilicon (PS) gate electrode is deposited conformally over patterned SOI stripes 116a', 116b', 116c', and 116d' giving sidewall contributions (sidewalls shown in phantom) to channel current. This arrangement is particularly advantageous for a lateral high- voltage device structure.
Referring still to Fig. 3B, the arrangement of the device 100' or the LSMOS device provides for a lower "on" resistance and the channel periphery is doubled as the polysilicon gate 140' is deposited conformally over the patterned SOI stripes 116a', 116b', 116c' and 116d' which extend beyond the three-dimensional MOS multi-capacitor structure 110'. Moreover, the channel conductivity is dropped by a factor of two (2).
In view of the foregoing, the three-dimensional MOS multi-capacitor structures 110 and 110' of the embodiments of Figs. 3 A and 3B may be designed in accordance with the details of either Fig. 1 or Fig. 4.
Numerous modifications to and alternative embodiments of the present invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. Details of the structure may be varied substantially without departing from the spirit of the invention and the exclusive use of all modifications which come within the scope of the appended claims is reserved.

Claims

CLAIMS:
1. A thin-layer silicon-on-insulator (SOI) device comprising: a semiconductor substrate (12); a three-dimensional metal-oxide semiconductor (MOS) multi-capacitor structure (10) formed on the substrate, wherein the MOS (10) forms a drift region patterned by a striped geometry of thin, silicon-on-insulator (SOI) stripes (116a, 116b, 116c and 116d) and each SOI stripe includes a respective dielectric layer (122a, 122b, 122c and 122d) disposed on the semiconductor substrate (12) and; a conducting field plate layer (130) superimposed on top of the respective dielectric layer and between adjacent dielectric layers.
2. The device according to Claim 1, wherein each of the dielectric layers (22a and 22b) includes a buried insulating layer (28a, 28a') interfacing a bottom periphery surface of a respective SOI stripe (16a, 16b), and a top insulating layer (28b, 28b') interfacing remaining periphery surfaces of the respective SOI stripe (16a, 16b).
3. The device according to Claim 2, wherein the buried insulating layer has a first thickness, each SOI stripe (16a, 16b) has a second thickness, and the first thickness and the second thickness are for a specific application voltage.
4. The device according to Claim 2 or Claim 3, wherein each SOI stripe (16a,
16b) is substantially in a center of the respective dielectric layer (22a, 22b).
5. The device according to any preceding Claim, wherein the conducting field plate layer (30) is electrically shorted to the semiconductor substrate (12).
6. The device according to any preceding Claim, further comprising: a silicon-on-insulator layer (116) extending from a drain (160) to a source (150) from which the silicon-on-insulator (SOI) stripes (116a, 116b, 116c and 116d) are formed; and, a gate (140) coupled across one end of the three-dimensional MOS multi- capacitor structures (110) and over an unpatterned portion of the silicon-on-insulator layer (116).
7. The device according to any of Claims 1 to 5, further comprising: a silicon-on-insulator layer (116') extending from a drain (160') to a source (150') from which the silicon-on-insulator (SOI) stripes (116a', 116b', 116c' and 116d') are formed; and, a gate (140') coupled over the silicon-on-insulator (SOI) stripes (116a', 116b', 116c' and 116d') extending beyond the three-dimensional MOS multi-capacitor structure.
8. The device according to Claim 7, wherein the drain (160') is comprised of a shallow N layer which extends along the width a channel, and the source (150') is comprised of a shallow N layer and a shallow P layer.
9. A thin-layer silicon-on-insulator (SOI) device comprising: a silicon-on-insulator (SOI) layer (116) extending from a drain (160) to a source (150); a three-dimensional metal-oxide semiconductor (MOS) field plate multi- capacitor structure (110) forming a drift region patterned by a striped geometry of thin, SOI stripes (116a, 116b, 116c and 116d) of the SOI layer (116) and biased to deplete a drift charge to achieve multi-dimensional depletion.
10. The device according to Claim 9, wherein each SOI stripe includes a respective dielectric layer (122a, 122b, 122c and 122d) disposed on a semiconductor substrate (12), and a conducting field plate layer (130) superimposed on top of the respective dielectric layer.
11. The device according to Claim 10, wherein each of the dielectric layers (22a and 22b) includes: a buried insulating layer (28a, 28a') interfacing a bottom periphery surface of a respective SOI stripe (16a, 16b); and a top insulating layer (28b, 28b') interfacing remaining periphery surfaces of the respective SOI stripe (16a, 16b).
12. The device according to Claim 11, wherein the buried insulating layer has a first thickness, each SOI stripe (16a, 16b) has a second thickness, and the first thickness and the second thickness are adapted for a specific application voltage.
13. The device according to Claim 12, wherein each SOI stripe (16a, 16b) is substantially in a center of the respective dielectric layer (22a, 22b).
14. The device according to any of Claims 10 to 13, wherein the conducting field plate layer (30) extends down to and is electrically shorted to the semiconductor substrate
(12).
15. The device according to any of Claims 10 to 13, wherein the conducting field plate layer (30') extends down to the buried insulating layer (28').
16. The device according to any of Claims 9 to 15, wherein the drain (160) is comprised of a shallow N layer which extends along the width a channel, and the source (150) is comprised of a shallow N layer and a shallow P layer.
17. The device according to any of Claims 9 to 16, further comprising: a gate (140) coupled across one end of the three-dimensional MOS multi- capacitor structures (110) and over an unpattemed portion of the silicon-on-insulator layer (116).
18. The device according to any of Claims 9 to 16, further comprising: a gate (140') coupled over the silicon-on-insulator (SOI) stripes (116a', 116b', 116c' and 116d') extending beyond the three-dimensional MOS multi-capacitor structure.
PCT/IB2002/003737 2001-10-01 2002-09-11 Silicon-on-insulator high voltage device structure WO2003030262A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2003533349A JP2005505136A (en) 2001-10-01 2002-09-11 Thin-film silicon-on-insulator (SOI) high-voltage device structure
AT02765227T ATE440382T1 (en) 2001-10-01 2002-09-11 SILICON-ON-INSULATOR HIGH VOLTAGE COMPONENT STRUCTURE
EP02765227A EP1438752B1 (en) 2001-10-01 2002-09-11 Silicon-on-insulator high-voltage device structure
DE60233422T DE60233422D1 (en) 2001-10-01 2002-09-11 SILICON-ON-INSULATOR HIGH VOLTAGE COMPONENT STRUCTURE
CN028193180A CN1561548B (en) 2001-10-01 2002-09-11 Silicon-on-insulator high-voltage device structure
KR1020047004793A KR100904785B1 (en) 2001-10-01 2002-09-11 Silicon-on-insulator high voltage device structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/968,121 2001-10-01
US09/968,121 US6414365B1 (en) 2001-10-01 2001-10-01 Thin-layer silicon-on-insulator (SOI) high-voltage device structure

Publications (2)

Publication Number Publication Date
WO2003030262A2 true WO2003030262A2 (en) 2003-04-10
WO2003030262A3 WO2003030262A3 (en) 2003-06-05

Family

ID=25513766

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/003737 WO2003030262A2 (en) 2001-10-01 2002-09-11 Silicon-on-insulator high voltage device structure

Country Status (8)

Country Link
US (1) US6414365B1 (en)
EP (1) EP1438752B1 (en)
JP (1) JP2005505136A (en)
KR (1) KR100904785B1 (en)
CN (1) CN1561548B (en)
AT (1) ATE440382T1 (en)
DE (1) DE60233422D1 (en)
WO (1) WO2003030262A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101980364A (en) * 2010-08-31 2011-02-23 电子科技大学 Thin-layer SOI composite power device
US8368144B2 (en) 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100843717B1 (en) * 2007-06-28 2008-07-04 삼성전자주식회사 Semiconductor device having floating body device and bulk body device and methods of fabricating the same
JP5154000B2 (en) * 2005-05-13 2013-02-27 ラピスセミコンダクタ株式会社 Semiconductor device
US7227233B2 (en) * 2005-09-12 2007-06-05 International Business Machines Corporation Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM
JP4830418B2 (en) * 2005-09-16 2011-12-07 株式会社デンソー Semiconductor device
US7790527B2 (en) * 2006-02-03 2010-09-07 International Business Machines Corporation High-voltage silicon-on-insulator transistors and methods of manufacturing the same
CN101916730B (en) * 2010-07-22 2012-07-11 中国科学院上海微系统与信息技术研究所 Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer
US8901676B2 (en) 2011-01-03 2014-12-02 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs
US8299547B2 (en) * 2011-01-03 2012-10-30 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates
US9245960B2 (en) 2013-02-08 2016-01-26 Globalfoundries Inc. Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates
US9768028B1 (en) 2016-08-10 2017-09-19 Globalfoundries Inc. Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure
KR102379040B1 (en) 2020-02-24 2022-03-25 삼육대학교산학협력단 Device and method of searching proper match

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001710A (en) * 1998-03-30 1999-12-14 Spectrian, Inc. MOSFET device having recessed gate-drain shield and method
EP1073123A2 (en) * 1999-07-29 2001-01-31 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04348068A (en) * 1991-03-18 1992-12-03 Toshiba Corp Semiconductor memory device
JP3251778B2 (en) * 1993-09-27 2002-01-28 三菱電機株式会社 Semiconductor storage device and method of manufacturing the same
KR100260560B1 (en) * 1998-03-18 2000-07-01 윤종용 Semiconductor memory device utiling silicon-on insulator structure and method for manufacturing the same
US6313489B1 (en) * 1999-11-16 2001-11-06 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device
US6400015B1 (en) * 2000-03-31 2002-06-04 Intel Corporation Method of creating shielded structures to protect semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001710A (en) * 1998-03-30 1999-12-14 Spectrian, Inc. MOSFET device having recessed gate-drain shield and method
EP1073123A2 (en) * 1999-07-29 2001-01-31 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368144B2 (en) 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials
CN101980364A (en) * 2010-08-31 2011-02-23 电子科技大学 Thin-layer SOI composite power device

Also Published As

Publication number Publication date
CN1561548A (en) 2005-01-05
KR20040037226A (en) 2004-05-04
EP1438752B1 (en) 2009-08-19
EP1438752A2 (en) 2004-07-21
CN1561548B (en) 2011-01-19
JP2005505136A (en) 2005-02-17
US6414365B1 (en) 2002-07-02
ATE440382T1 (en) 2009-09-15
WO2003030262A3 (en) 2003-06-05
KR100904785B1 (en) 2009-06-25
DE60233422D1 (en) 2009-10-01

Similar Documents

Publication Publication Date Title
JP5354808B2 (en) Method for fabricating a high voltage transistor on a substrate
JP5419913B2 (en) Method for fabricating a high voltage transistor having a multilayer extended drain structure
US6621132B2 (en) Semiconductor device
JP4564793B2 (en) High voltage vertical transistor with multilayer extended drain structure
JP3365984B2 (en) MOS gate device and its manufacturing process
KR100761179B1 (en) Semiconductor device
US6600194B2 (en) Field-effect semiconductor devices
EP1170803A2 (en) Trench gate MOSFET and method of making the same
EP1051757B1 (en) Lateral thin-film silicon-on-insulator (soi) device having multiple zones in the drift region
EP1438752B1 (en) Silicon-on-insulator high-voltage device structure
JP2010062557A (en) Semiconductor device with trench-gate structure, and method of manufacturing the same
EP2884540B1 (en) Vertical transistor device structure with cylindrically-shaped regions
US6955970B1 (en) Process for manufacturing a low voltage MOSFET power device having a minimum figure of merit
US7968938B2 (en) High-voltage device structure
US9257517B2 (en) Vertical DMOS-field effect transistor
JP2006505932A (en) Semiconductor device and manufacturing method thereof
CN111180339B (en) LDMOS device and manufacturing method thereof
CN115642182B (en) Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit
CN111883515A (en) Trench gate device and manufacturing method thereof
US6222232B1 (en) Asymmetric MOS technology power device
WO2001031711A2 (en) Vertical insulated gate field-effect device and method of making the same
JP7314827B2 (en) semiconductor equipment
CN115548119A (en) Semiconductor device and method for manufacturing the same
CN115881785A (en) LDMOS device and preparation method thereof
CN113690299A (en) Trench gate VDMOS device and preparation method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FR GB GR IE IT LU MC NL PT SE SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003533349

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2002765227

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 20028193180

Country of ref document: CN

Ref document number: 1020047004793

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2002765227

Country of ref document: EP