WO2003032568A3 - Verfahren und vorrichtung zur synchronisation der datenübertragung zwischen zwei schaltungen - Google Patents

Verfahren und vorrichtung zur synchronisation der datenübertragung zwischen zwei schaltungen Download PDF

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Publication number
WO2003032568A3
WO2003032568A3 PCT/EP2002/009508 EP0209508W WO03032568A3 WO 2003032568 A3 WO2003032568 A3 WO 2003032568A3 EP 0209508 W EP0209508 W EP 0209508W WO 03032568 A3 WO03032568 A3 WO 03032568A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
phase
circuits
data transmission
clocks
Prior art date
Application number
PCT/EP2002/009508
Other languages
English (en)
French (fr)
Other versions
WO2003032568A2 (de
Inventor
Josef Hoelzle
Original Assignee
Infineon Technologies Ag
Josef Hoelzle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Josef Hoelzle filed Critical Infineon Technologies Ag
Priority to US10/491,947 priority Critical patent/US7428287B2/en
Priority to AU2002333709A priority patent/AU2002333709A1/en
Publication of WO2003032568A2 publication Critical patent/WO2003032568A2/de
Publication of WO2003032568A3 publication Critical patent/WO2003032568A3/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Abstract

Zur Synchronisation der Datenübertragung zwischen einer CMOS-Schaltung (1) und einer Bipolar-Schaltung (2) ist eine DLL-Schaltung ('Delay Locked Loop') vorgesehen, welche eine Phasenabweichung zwischen den Betriebstakten (CLK1, CLK2) der beiden Schaltungen (1, 2) feststellt und davon abhängig die Phase mindestens eines der beiden Takte (CLK1, CLK2) solange verändert, bis die beiden Takte phasengleich sind, so dass anschließend die von der ersten Schaltung (1) bereitgestellten Daten (DATA1) von der zweiten Schaltung (2) übernommen werden können. Die DLL-Schaltung umfasst hierzu einen Phasendetektor (6), ein Schleifenfilter (7) und ein einstellbares Verzögerungselement (8).
PCT/EP2002/009508 2001-10-08 2002-08-26 Verfahren und vorrichtung zur synchronisation der datenübertragung zwischen zwei schaltungen WO2003032568A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/491,947 US7428287B2 (en) 2001-10-08 2002-08-26 Method and device for synchronizing data transmission between two circuits
AU2002333709A AU2002333709A1 (en) 2001-10-08 2002-08-26 Method and device for the synchronisation of data transmission between two circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10149512.9 2001-10-08
DE10149512A DE10149512B4 (de) 2001-10-08 2001-10-08 Verfahren und Vorrichtung zur Synchronisation der Datenübertragung zwischen zwei Schaltungen

Publications (2)

Publication Number Publication Date
WO2003032568A2 WO2003032568A2 (de) 2003-04-17
WO2003032568A3 true WO2003032568A3 (de) 2003-12-04

Family

ID=7701751

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/009508 WO2003032568A2 (de) 2001-10-08 2002-08-26 Verfahren und vorrichtung zur synchronisation der datenübertragung zwischen zwei schaltungen

Country Status (4)

Country Link
US (1) US7428287B2 (de)
AU (1) AU2002333709A1 (de)
DE (1) DE10149512B4 (de)
WO (1) WO2003032568A2 (de)

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JP3870942B2 (ja) * 2003-10-20 2007-01-24 ソニー株式会社 データ伝送システム及びデータ伝送装置
US7509515B2 (en) * 2005-09-19 2009-03-24 Ati Technologies, Inc. Method and system for communicated client phase information during an idle period of a data bus
WO2007113945A1 (ja) 2006-04-05 2007-10-11 Panasonic Corporation リムーバブルメモリデバイス、位相同期方法、位相同期プログラム、その記録媒体及びホスト端末
US9025714B2 (en) * 2013-04-30 2015-05-05 Raytheon Company Synchronous data system and method for providing phase-aligned output data
US10447461B2 (en) * 2015-12-01 2019-10-15 Infineon Technologies Austria Ag Accessing data via different clocks
US11262786B1 (en) * 2020-12-16 2022-03-01 Silicon Laboratories Inc. Data delay compensator circuit

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Publication number Priority date Publication date Assignee Title
EP0379279A2 (de) * 1989-01-17 1990-07-25 Marconi Instruments Limited Datenvermittlungssynchronisator
EP0419161A2 (de) * 1989-09-22 1991-03-27 Nec Corporation Schaltung zur Unterdrückung eines Taktflatterns
EP0704975A1 (de) * 1994-09-29 1996-04-03 Nec Corporation Digitaler phasenverriegelter Kreis mit grob- und feinstufig variabel einstellbaren Verzögerungsleitungen
US5572557A (en) * 1993-06-02 1996-11-05 Nec Corporation Semiconductor integrated circuit device including PLL circuit
EP0810508A2 (de) * 1996-05-28 1997-12-03 Sun Microsystems, Inc. Datenübertragung mit Sendersynchronisation ohne Zeitstrafe wegen Resynchronisation
US6242954B1 (en) * 1998-10-15 2001-06-05 Fujitsu Limited Timing clock generation circuit using hierarchical DLL circuit

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US5644605A (en) * 1990-11-13 1997-07-01 Dallas Semiconductor Corp. Jitter attenuator
KR0157952B1 (ko) 1996-01-27 1999-03-20 문정환 위상 지연 보정 장치
KR100212139B1 (ko) * 1996-07-22 1999-08-02 윤종용 클럭공급장치
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JP3840731B2 (ja) * 1997-03-21 2006-11-01 富士通株式会社 半導体集積回路
US5905391A (en) * 1997-07-14 1999-05-18 Intel Corporation Master-slave delay locked loop for accurate delay or non-periodic signals
US5949262A (en) * 1998-01-07 1999-09-07 International Business Machines Corporation Method and apparatus for coupled phase locked loops
US6072743A (en) * 1998-01-13 2000-06-06 Mitsubishi Denki Kabushiki Kaisha High speed operable semiconductor memory device with memory blocks arranged about the center
US6005426A (en) * 1998-05-06 1999-12-21 Via Technologies, Inc. Digital-type delay locked loop with expanded input locking range
JP3763673B2 (ja) * 1998-06-11 2006-04-05 富士通株式会社 Ｄｌｌ回路
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KR100416695B1 (ko) * 2000-06-30 2004-02-05 주식회사 하이닉스반도체 노이즈 제어가 가능한 지연고정루프
KR100399941B1 (ko) * 2001-06-30 2003-09-29 주식회사 하이닉스반도체 디디알 에스디램의 레지스터 제어 지연고정루프
KR100422572B1 (ko) * 2001-06-30 2004-03-12 주식회사 하이닉스반도체 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자
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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379279A2 (de) * 1989-01-17 1990-07-25 Marconi Instruments Limited Datenvermittlungssynchronisator
EP0419161A2 (de) * 1989-09-22 1991-03-27 Nec Corporation Schaltung zur Unterdrückung eines Taktflatterns
US5572557A (en) * 1993-06-02 1996-11-05 Nec Corporation Semiconductor integrated circuit device including PLL circuit
EP0704975A1 (de) * 1994-09-29 1996-04-03 Nec Corporation Digitaler phasenverriegelter Kreis mit grob- und feinstufig variabel einstellbaren Verzögerungsleitungen
EP0810508A2 (de) * 1996-05-28 1997-12-03 Sun Microsystems, Inc. Datenübertragung mit Sendersynchronisation ohne Zeitstrafe wegen Resynchronisation
US6242954B1 (en) * 1998-10-15 2001-06-05 Fujitsu Limited Timing clock generation circuit using hierarchical DLL circuit

Also Published As

Publication number Publication date
DE10149512A1 (de) 2003-04-24
AU2002333709A1 (en) 2003-04-22
US7428287B2 (en) 2008-09-23
DE10149512B4 (de) 2006-08-03
US20040247065A1 (en) 2004-12-09
WO2003032568A2 (de) 2003-04-17

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