WO2003036793A1 - Operational transconductance amplifier circuit - Google Patents
Operational transconductance amplifier circuit Download PDFInfo
- Publication number
- WO2003036793A1 WO2003036793A1 PCT/IB2002/004321 IB0204321W WO03036793A1 WO 2003036793 A1 WO2003036793 A1 WO 2003036793A1 IB 0204321 W IB0204321 W IB 0204321W WO 03036793 A1 WO03036793 A1 WO 03036793A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ramp
- liquid crystal
- crystal display
- transconductance amplifier
- pixel
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2011—Display of intermediate tones by amplitude modulation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
Definitions
- the present invention relates to an operational transconductance amplifier circuit, a ramp source comprising such an operational transconductance amplifier, and to a liquid crystal display.
- each image frame is composed of color sub-frames, usually red, green and blue sub-frames.
- Such LCD systems employ a liquid crystal display panel that is comprised of a large number of individual liquid crystal pixel elements. Those pixel elements are beneficially organized in a matrix comprised of pixel rows and pixel columns. To produce a desired image, the individual pixel elements are modulated in accordance with image information. Typically, the image information is applied to the individual pixel elements by rows, with each pixel row being addressed in each frame period.
- Pixel element matrix arrays are preferably "active" in that each pixel element is connected to an active switching element of a matrix of such switching elements.
- One particularly useful active matrix liquid crystal display is the reflective active-matrix liquid crystal display (further also referred to as RLCD).
- An RLCD display is typically produced on a silicon substrate and is often based on the twisted nematic (TN) effect.
- Thin film transistors (TFTs) are usually used as the active switching elements.
- TFTs Thin film transistors
- Such RLCD displays can support a high pixel density because the TFTs and their interconnections can be integrated onto the silicon substrate.
- Figure 1 schematically illustrates a single pixel element 10 of atypical prior art RLCD.
- the pixel element 10 is comprised of a twisted nematic liquid crystal layer 12 that is disposed between a transparent electrode 14 and a pixel electrode 16.
- Figure 1 shows the transparent electrode 14 applied to a common ground.
- a storage element 18 is connected to complementary data terminals 20 and 22.
- the storage element 18 receives control signals on a control terminal 24.
- the storage element 18 selectively latches the data signal on one of the data terminals 20 and 22, and applies that latched signal to the pixel electrode 16 via a signal line 26.
- the data signals on the data terminals 20 and 22 are complementary. That is, when one line is at +2 volts, the other is at -2 volts.
- the liquid crystal layer 12 rotates the polarization of the light 30, with the amount of polarization rotation dependent on the voltage across the liquid crystal layer 12.
- the pixel element 10 is symmetrical in that the polarization rotation depends only on the magnitude of the latched signal on the signal line 26. By alternating complementary signals in consecutive frames, unwanted charges across the liquid crystal layer 12 are prevented. If only one polarity was used, ions would build up across the capacitance formed by the transparent electrode 14, the liquid crystal layer 12, and the pixel electrode 16. Such charges would bias the pixel element 10.
- the light 30 is derived from incident non-polarized light 32 from an external light source (which is not shown).
- the non-polarized light 32 is polarized by a first polarizer 34 to form the light 30.
- the light 30 passes through the transparent electrode 14, through the liquid crystal layer 12, reflects off the pixel electrode 16, passes back through the liquid crystal layer 12, passes out of the transparent electrode 14, and then is directed onto a second polarizer 36.
- the polarization of the light beam is rotated in accord with the magnitude of the voltage on the signal line 26. Only the portion of the light 30 that is parallel with the polarization direction of the second polarizer 36 passes through that polarizer 36. Since the passed portion depends on the amount of polarization rotation, which in turn depends on the voltage on the signal line 26, the voltage on the signal line 26 controls the intensity of the light that leaves the pixel element 10.
- the storage element 18 is typically a capacitor connected to a thin film transistor switch.
- a control signal is applied to the gate electrode of the thin film transistor that transistor turns on. Then, the voltage applied to the source of the thin film transistor passes through the thin film transistor and charges the capacitor.
- the control signal is removed, the thin film transistor opens and the capacitor potential is stored on the pixel electrode 16.
- Figure 2 schematically illustrates a prior art pixel element matrix. As shown, a plurality of pixel elements 10, each having an associated switching thin film transistor and a storage capacitor, are arranged in a matrix of rows (horizontal) and columns (vertical). For simplicity, only a small portion of a matrix array is shown. In practice there are numerous rows, say 1290, and numerous columns, say 1024.
- the pixel elements 10 of a row are selected together by applying a gate (switch) control signal on a gate line, specifically the gate lines 40a, 40b, and 40c.
- a constant voltage (which is shared by all of the pixel elements 10) is applied to the transparent electrode 14 from a ramp source 41 via a line 42.
- the ramp source 41 applies complementary ramp signals on lines 20 and 22 (which are also shared by all of the pixel elements 10).
- column lines 46a, 46b, and 46c control the operation of the pixel elements 10 in that they determine the optical state of the pixel elements 10.
- a row of pixel elements is selected by the application of a signal on an appropriate one of the gate lines 40a-40c. This turns on all of the pixel elements 10 in that row. Then, the ramp source 41 applies a ramp to either line 20 or line 22 (which line is used is varied in each frame). The ramp begins charging all of the storage capacitors in the selected row. As the other rows are not energized, the ramp source only charges the OFF- state capacitance of the other pixels 10. When the ramp voltage reaches the desired state for a particular pixel 10, the column line (46a-46c) voltage for that particular pixel element 10 turns the pixel switch OFF. Then, the ramp voltage that existed when the particular pixel element 10 was turned OFF is stored on that element's storage capacitor.
- the ramp voltage continues to increase until all of the column lines (46a-46c) cause a ramp voltage to be HELD on an associated pixel element 10. After that, a new row of pixel elements 10 is selected and the process starts over. After all rows have been selected, the process starts over again in a new frame period, this time using the complement of the previous ramp.
- OTA Operational Transconductance Amplifier
- ramp sources are commonly used.
- Reasons for this include the wide dynamic range and operational bandwidths of OTAs.
- An OTA is a current controlled resistance amplifier that is similar to operational amplifiers, except that an OTA uses differential input current to control an output, rather than a differential voltage.
- an OTA includes differential inputs.
- RLCD displays are generally successful, they have problems. For example, driving a row of pixel elements 10 using a relatively slowly changing voltage ramp, and then rapidly discharging that ramp to prepare for driving the next row of pixel elements 10 can lead to various problems, including ramp overshoot and high power dissipation.
- a first aspect of the invention provides an operational transconductance amplifier circuit as claimed in claim 1.
- a second aspect of the invention provides a ramp source comprising such an operational transconductance amplifier as claimed in claim 4.
- a third aspect of the invention provides a liquid crystal display as claimed in claim 9.
- Advantageous embodiments are defined in the dependent claims.
- the RLCD display can be modeled as a capacitance C RLCD+ -
- the + designates that pixel elements 10 are switched on such that current must flow into the storage elements 18.
- the OTA that produces the ramp must have a minimum slew-rate of:
- IRLCD+ (SRRLCD+)(CRLCD+) where:
- SR R L CD + is the required slew rate when charging the storage elements of a row; is an amplification factor determined by the required gain; V m ax_ramp is the maximum ramp voltage;
- Vmin amp is the minimum ramp voltage
- tramp is the ramp up time
- I L CD+ is the maximum charging current during ramp up
- SRR CD+ is the minimum required slew rate during ramp up; and CRLCD+ is the maximum capacitance of the RLCD during ramp up.
- SRRLCD- is the required slew rate when discharging the ramp;
- t fb is the ramp down (fly back) time;
- IRL CD - is the maximum charging (discharge) current during fly back
- SRRL CD - is the minimum required slew rate during fly back
- C R L CD - is the maximum capacitance of the RLCD during fly back.
- the ramp source 41 is usually designed to handle the greater signal slew (and thus current) over the entire ramp cycle, in spite of the fact that the greater current handling capability is only needed for a relatively small part of each ramp cycle. This leads to high power dissipation and to inherent instabilities (such as ramp signal overshoot). Therefore, a ramp source 41 having a faster slew rate during ramp fly back would be beneficial. Even more beneficial would be an OTA circuit having a slew rate controlled by an external signal. Such ramp sources and circuits would be particularly useful in liquid crystal display devices.
- the principles of the present invention provide for operational transconductance amplifier (OTA) circuits having slew rates controlled by external signals, for ramp sources having increased slew capability during ramp fly back, and for liquid crystal display devices having ramp sources with controlled slew rates.
- OTA operational transconductance amplifier
- a circuit according to the principles of the present invention includes an operational transconductance amplifier (OTA).
- the OTA has an output that drives a load, which is beneficially a liquid crystal display panel.
- the OTA circuit includes a first current source that sinks a first tail current, and a second current source that selectively sinks a second tail current.
- the second current source is selected by a control signal applied to a switch. When the second current source sinks the additional second tail current the slew rate of the OTA is increased.
- the OTA circuit receives a ramp input that is applied to the non-inverting input of the OTA. Then, the slew rate is increased during ramp fly back.
- the OTA circuit drives a liquid crystal display panel with a ramp such that the ramp's slew rate is increased during fly back.
- Figure 2 schematically illustrates a prior art pixel element matrix
- Figure 3 illustrates exemplary ramp potentials
- Figure 4 schematically illustrates a ramp source for a liquid crystal display that incorporates the principles of the present invention.
- FIG 5 schematically illustrates time base signals associated with the ramp source illustrated in Figure 4.
- That embodiment includes an OTA ramp source 41 having increased drive capability during ramp fly back. Furthermore, that ramp source 41 is used to drive a liquid crystal display.
- the ramp source 41 of Figure 2 produces voltage ramps on lines 20 and 22.
- Figure 3 illustrates one of those voltage ramps 100 (positive going). Since the other voltage ramp is an inverted (negative going) version of the voltage ramp of Figure 3, it should be understood that the following refers to both ramps.
- the voltage ramp 100 begins at a minimum voltage 102 ( min_ramp) and increases over time (horizontal axis) t ramP to a maximum voltage 104 ( m a x _ra m p) at an instant 106. During that time t ram p the voltage ramp 100 changes at a maximum rate 108 (SR RLCD +).
- the ramp source 41 must be able to provide the required output power at the maximum rate 108. Otherwise, the desired ramp profile cannot be obtained, resulting in an incorrect profile, which produces illumination distortion. Still referring to Figure 3, after the ramp period t ramp the maximum voltage is maintained for a short period of time.
- the voltage ramp drops from V max _ ramp 104 to V m ; n _ ramp 102 in a fly back time tft, 112.
- the voltage profile 100 changes at a maximum rate of SR RLCD - 114.
- the ramp source 41 must be able to provide the required fly back output power at the rate SR RLCD - 114.
- An OTA based ramp source 120 that can provide the required power at the required slew rate SR RLCD + 108 while dissipating limited power, and that can provide the required power at the required slew rate SR RLCD - 114 is illustrated in Figure 4.
- An OTA 122 receives a ramp input having the desired shape on a line 124 from a ramp generator 123.
- the OTA 122 drives the RLCD display 126, which is modeled as a capacitor C.
- the capacitance of the RLCD display 126 will vary in accord with the image produced by a given row of pixel elements 10.
- the slew rate of the OTA 122 is a function of the "tail current" I ta ii through the OTA mirror. That tail current I a n is output on a tail current line 128.
- the slew rate SR rampS ource of the OTA based ramp source 120 is a function of the tail current Itaii and of the capacitance C d i s pi a y of the RLCD display 126. That slew rate is: Cmc(lt a ii / .displ y where cmc is a current multiplication coefficient that is associated with the OTA topology.
- a first OTA tail current 204 on the tail current line 128 is constantly drawn through a current source I max _ S ampie 132.
- the current source I m ax_sampie 1 2 is selected such that the slew rate of the OTA ramp source S rampsource is sufficient to meet the maximum required slew rate of the ramp source SRrampsource 108.
- a second current source I_ ⁇ y _back 134 is selectively switched so as to draw additional OTA tail current 205 on the tail current line 128 during the fly back time t ft , 112 (reference Figure 3).
- the switch 136 that selectively connects the current source Ifly_bac 134 is beneficially a digitally controlled analog switch, with the digital control applied on a control line 138, beneficially form the ramp generator 123.
- the tail current is at the first OTA tail current 204 of the current source I ma ⁇ _sampie 132.
- the tail current increases to the value 206, which is the sum of the currents 204 and 205 of the current source I ma ⁇ _satnpie 132 and of the current source Ifi y _back 134, respectively.
- the tail current value 204 enables the OTA ramp source to have a maximum slew rate 108.
- the digital control signal goes HIGH, the tail current increases, which enables the OTA ramp source to have a maximum slew rate 114.
- the maximum OTA ramp source slew rate is digitally controlled by the signal on the control line 138 of Figure 4.
- any reference signs placed between parentheses shall not be construed as limiting the claim.
- the word “comprising” does not exclude the presence of elements or steps other than those listed in a claim.
- the word "a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
- the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-7005890A KR20040045894A (en) | 2001-10-22 | 2002-10-17 | Operational transconductance amplifier circuit |
EP02775112A EP1440508A1 (en) | 2001-10-22 | 2002-10-17 | Operational transconductance amplifier circuit |
JP2003539164A JP2005506792A (en) | 2001-10-22 | 2002-10-17 | Operational transconductance amplifier circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/982,893 US6670941B2 (en) | 2001-10-22 | 2001-10-22 | Slow rate controlled ramp and its use in liquid crystal displays |
US09/982,893 | 2001-10-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003036793A1 true WO2003036793A1 (en) | 2003-05-01 |
Family
ID=25529607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2002/004321 WO2003036793A1 (en) | 2001-10-22 | 2002-10-17 | Operational transconductance amplifier circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US6670941B2 (en) |
EP (1) | EP1440508A1 (en) |
JP (1) | JP2005506792A (en) |
KR (1) | KR20040045894A (en) |
CN (1) | CN1575545A (en) |
WO (1) | WO2003036793A1 (en) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910854A (en) | 1993-02-26 | 1999-06-08 | Donnelly Corporation | Electrochromic polymeric solid films, manufacturing electrochromic devices using such solid films, and processes for making such solid films and devices |
US5668663A (en) | 1994-05-05 | 1997-09-16 | Donnelly Corporation | Electrochromic mirrors and devices |
US6891563B2 (en) | 1996-05-22 | 2005-05-10 | Donnelly Corporation | Vehicular vision system |
US6326613B1 (en) | 1998-01-07 | 2001-12-04 | Donnelly Corporation | Vehicle interior mirror assembly adapted for containing a rain sensor |
US8294975B2 (en) | 1997-08-25 | 2012-10-23 | Donnelly Corporation | Automotive rearview mirror assembly |
US6124886A (en) | 1997-08-25 | 2000-09-26 | Donnelly Corporation | Modular rearview mirror assembly |
US6172613B1 (en) | 1998-02-18 | 2001-01-09 | Donnelly Corporation | Rearview mirror assembly incorporating vehicle information display |
US8288711B2 (en) | 1998-01-07 | 2012-10-16 | Donnelly Corporation | Interior rearview mirror system with forwardly-viewing camera and a control |
US6445287B1 (en) | 2000-02-28 | 2002-09-03 | Donnelly Corporation | Tire inflation assistance monitoring system |
US6477464B2 (en) | 2000-03-09 | 2002-11-05 | Donnelly Corporation | Complete mirror-based global-positioning system (GPS) navigation solution |
US6329925B1 (en) | 1999-11-24 | 2001-12-11 | Donnelly Corporation | Rearview mirror assembly with added feature modular display |
US6693517B2 (en) | 2000-04-21 | 2004-02-17 | Donnelly Corporation | Vehicle mirror assembly communicating wirelessly with vehicle accessories and occupants |
US7370983B2 (en) | 2000-03-02 | 2008-05-13 | Donnelly Corporation | Interior mirror assembly with display |
US7855755B2 (en) | 2005-11-01 | 2010-12-21 | Donnelly Corporation | Interior rearview mirror assembly with display |
WO2001064481A2 (en) | 2000-03-02 | 2001-09-07 | Donnelly Corporation | Video mirror systems incorporating an accessory module |
US7167796B2 (en) | 2000-03-09 | 2007-01-23 | Donnelly Corporation | Vehicle navigation system for use with a telematics system |
JP2002123226A (en) * | 2000-10-12 | 2002-04-26 | Hitachi Ltd | Liquid crystal display device |
US7581859B2 (en) | 2005-09-14 | 2009-09-01 | Donnelly Corp. | Display device for exterior rearview mirror |
US7255451B2 (en) | 2002-09-20 | 2007-08-14 | Donnelly Corporation | Electro-optic mirror cell |
DE60220379T2 (en) | 2001-01-23 | 2008-01-24 | Donnelly Corp., Holland | IMPROVED VEHICLE LIGHTING SYSTEM |
US6918674B2 (en) | 2002-05-03 | 2005-07-19 | Donnelly Corporation | Vehicle rearview mirror system |
US7329013B2 (en) | 2002-06-06 | 2008-02-12 | Donnelly Corporation | Interior rearview mirror system with compass |
EP1514246A4 (en) | 2002-06-06 | 2008-04-16 | Donnelly Corp | Interior rearview mirror system with compass |
KR100486254B1 (en) * | 2002-08-20 | 2005-05-03 | 삼성전자주식회사 | Circuit and Method for driving Liquid Crystal Display Device using low power |
US7310177B2 (en) | 2002-09-20 | 2007-12-18 | Donnelly Corporation | Electro-optic reflective element assembly |
WO2004026633A2 (en) | 2002-09-20 | 2004-04-01 | Donnelly Corporation | Mirror reflective element assembly |
WO2004103772A2 (en) | 2003-05-19 | 2004-12-02 | Donnelly Corporation | Mirror assembly for vehicle |
US7446924B2 (en) | 2003-10-02 | 2008-11-04 | Donnelly Corporation | Mirror reflective element assembly including electronic component |
US7308341B2 (en) | 2003-10-14 | 2007-12-11 | Donnelly Corporation | Vehicle communication system |
DE10360816A1 (en) * | 2003-12-23 | 2005-07-28 | Deutsche Thomson-Brandt Gmbh | Circuit and driving method for a light-emitting display |
US7626749B2 (en) | 2005-05-16 | 2009-12-01 | Donnelly Corporation | Vehicle mirror assembly with indicia at reflective element |
KR100717278B1 (en) * | 2005-05-31 | 2007-05-15 | 삼성전자주식회사 | Source driver capable of controlling slew rate |
KR100832894B1 (en) * | 2005-10-06 | 2008-05-28 | 삼성전기주식회사 | Output buffer circuit |
KR101215027B1 (en) * | 2005-12-21 | 2012-12-26 | 삼성디스플레이 주식회사 | Transreflective liquid crystal display and driving method thereof |
TWI320167B (en) * | 2006-09-07 | 2010-02-01 | Display device and method capable of adjusting slew rate | |
US8154418B2 (en) | 2008-03-31 | 2012-04-10 | Magna Mirrors Of America, Inc. | Interior rearview mirror system |
JP2013026647A (en) * | 2011-07-15 | 2013-02-04 | Sony Corp | Amplifier, liquid crystal display drive circuit, and liquid crystal display device |
US9681207B2 (en) * | 2013-01-24 | 2017-06-13 | Finisar Corporation | Local buffers in a liquid crystal on silicon chip |
US8975962B2 (en) | 2013-06-19 | 2015-03-10 | Synaptics Incorporated | Slew-enhanced operational transconductance amplifier |
US9356562B2 (en) | 2014-01-30 | 2016-05-31 | Apple Inc. | Family of slew-enhanced operational transconductance amplifiers |
KR20220093787A (en) * | 2020-12-28 | 2022-07-05 | 엘지디스플레이 주식회사 | Low-Power Driving Display Device and Driving Method of the same |
CN114023234B (en) * | 2021-11-10 | 2023-07-04 | Tcl华星光电技术有限公司 | Display device and electronic apparatus |
US11735085B1 (en) * | 2022-04-15 | 2023-08-22 | Ying-Neng Huang | Output buffer capable of reducing power consumption of a display driver |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006739A (en) * | 1987-06-15 | 1991-04-09 | Hitachi, Ltd. | Capacitive load drive circuit |
US5363059A (en) * | 1993-06-17 | 1994-11-08 | Texas Instruments Incorporated | Transconductance amplifier |
US5502410A (en) * | 1994-03-14 | 1996-03-26 | Motorola, Inc. | Circuit for providing a voltage ramp signal |
US6049252A (en) * | 1997-06-30 | 2000-04-11 | Nec Corporation | Programmable-gain amplifier |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3329077B2 (en) * | 1993-07-21 | 2002-09-30 | セイコーエプソン株式会社 | Power supply device, liquid crystal display device, and power supply method |
JPH07130193A (en) * | 1993-09-10 | 1995-05-19 | Toshiba Corp | Buffer circuit and liquid crystal display device using it |
JP3506219B2 (en) * | 1998-12-16 | 2004-03-15 | シャープ株式会社 | DA converter and liquid crystal driving device using the same |
US6222418B1 (en) * | 2000-02-29 | 2001-04-24 | Lucent Technologies, Inc. | Feed-forward compensation scheme for feedback circuits |
US6384679B1 (en) * | 2000-11-15 | 2002-05-07 | National Semiconductor Corporation | Rail-to-rail amplifier with reduced GM and compensating cap |
US6433637B1 (en) * | 2001-03-23 | 2002-08-13 | National Semiconductor Corporation | Single cell rail-to-rail input/output operational amplifier |
-
2001
- 2001-10-22 US US09/982,893 patent/US6670941B2/en not_active Expired - Fee Related
-
2002
- 2002-10-17 EP EP02775112A patent/EP1440508A1/en not_active Withdrawn
- 2002-10-17 KR KR10-2004-7005890A patent/KR20040045894A/en not_active Application Discontinuation
- 2002-10-17 WO PCT/IB2002/004321 patent/WO2003036793A1/en not_active Application Discontinuation
- 2002-10-17 CN CNA028208749A patent/CN1575545A/en active Pending
- 2002-10-17 JP JP2003539164A patent/JP2005506792A/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006739A (en) * | 1987-06-15 | 1991-04-09 | Hitachi, Ltd. | Capacitive load drive circuit |
US5363059A (en) * | 1993-06-17 | 1994-11-08 | Texas Instruments Incorporated | Transconductance amplifier |
US5502410A (en) * | 1994-03-14 | 1996-03-26 | Motorola, Inc. | Circuit for providing a voltage ramp signal |
US6049252A (en) * | 1997-06-30 | 2000-04-11 | Nec Corporation | Programmable-gain amplifier |
Also Published As
Publication number | Publication date |
---|---|
CN1575545A (en) | 2005-02-02 |
US20030076285A1 (en) | 2003-04-24 |
US6670941B2 (en) | 2003-12-30 |
KR20040045894A (en) | 2004-06-02 |
EP1440508A1 (en) | 2004-07-28 |
JP2005506792A (en) | 2005-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6670941B2 (en) | Slow rate controlled ramp and its use in liquid crystal displays | |
US6384817B1 (en) | Apparatus for applying voltages to individual columns of pixels in a color electro-optic display device | |
US8159484B2 (en) | Liquid crystal device, pixel circuit, active matrix substrate, and electronic apparatus | |
US8497831B2 (en) | Electro-optical device, driving method therefor, and electronic apparatus | |
US6911964B2 (en) | Frame buffer pixel circuit for liquid crystal display | |
JP5646283B2 (en) | display | |
KR101413872B1 (en) | Liquid crystal device and electronic apparatus | |
JP4271441B2 (en) | Display driver and liquid crystal display device | |
US6940482B2 (en) | Electrooptic device and electronic apparatus | |
US6844874B2 (en) | Device for controlling a matrix display cell | |
US4152626A (en) | Compensation for half selection in a drive system for a thin-film EL display | |
US7423619B2 (en) | Refresh pixel circuit for active matrix | |
US7508367B2 (en) | Drive circuit for improved brightness control in liquid crystal displays and method therefor | |
JPH07281641A (en) | Active matrix type liquid crystal display | |
JP2001022315A (en) | Opto-electronic device, driving method and electronic device therefor | |
JPH0572995A (en) | Liquid crystal display device | |
US20030112211A1 (en) | Active matrix liquid crystal display devices | |
WO2004102521A2 (en) | Low voltage frame buffer for high contrast lcd microdisplay and method therefor | |
KR100453186B1 (en) | Ferroelectric liquid crystal display device and its driving method | |
TW200530982A (en) | Pixel array driving method | |
JPH0990915A (en) | Liquid crystal display device | |
KR20050024391A (en) | Refresh pixel circuit for active matrix | |
JP2006267359A (en) | Electro-optical device and electronic equipment | |
JPH04241382A (en) | Gradation driving circuit for flat display | |
JPS5875193A (en) | Display |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2002775112 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2003539164 Country of ref document: JP Ref document number: 20028208749 Country of ref document: CN Ref document number: 1020047005890 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2002775112 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2002775112 Country of ref document: EP |