WO2003038889A3 - Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring - Google Patents

Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring Download PDF

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Publication number
WO2003038889A3
WO2003038889A3 PCT/US2002/034140 US0234140W WO03038889A3 WO 2003038889 A3 WO2003038889 A3 WO 2003038889A3 US 0234140 W US0234140 W US 0234140W WO 03038889 A3 WO03038889 A3 WO 03038889A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch process
interferometry endpoint
interferometry
situ
nitride spacer
Prior art date
Application number
PCT/US2002/034140
Other languages
French (fr)
Other versions
WO2003038889A2 (en
Inventor
Wen-Ben Chou
Shih-Yuan Cheng
Wayne Tu
Original Assignee
Lam Res Corp
Wen-Ben Chou
Shih-Yuan Cheng
Wayne Tu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp, Wen-Ben Chou, Shih-Yuan Cheng, Wayne Tu filed Critical Lam Res Corp
Priority to AU2002353877A priority Critical patent/AU2002353877A1/en
Publication of WO2003038889A2 publication Critical patent/WO2003038889A2/en
Publication of WO2003038889A3 publication Critical patent/WO2003038889A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A method for fabricating a spacer of a gate structure is provided. The method performing a first etch process implementing a first etchant gas. The first etch process is configured to implement an interferometry endpoint (IEP) detection method to detect a removal of a portion of a spacer layer having a specific thickness from over the surface of the substrate, thus leaving a thin spacer layer. The method further includes performing a second etch process for a predetermined period of time implementing a second etchant gas. The second etch process is configured to remove the thin spacer layer, leaving the spacer for the gate structure.
PCT/US2002/034140 2001-10-31 2002-10-23 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring WO2003038889A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002353877A AU2002353877A1 (en) 2001-10-31 2002-10-23 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/998,858 US6977184B1 (en) 2001-10-31 2001-10-31 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring
US09/998,858 2001-10-31

Publications (2)

Publication Number Publication Date
WO2003038889A2 WO2003038889A2 (en) 2003-05-08
WO2003038889A3 true WO2003038889A3 (en) 2003-10-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/034140 WO2003038889A2 (en) 2001-10-31 2002-10-23 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring

Country Status (5)

Country Link
US (2) US6977184B1 (en)
CN (1) CN100468677C (en)
AU (1) AU2002353877A1 (en)
TW (1) TW567572B (en)
WO (1) WO2003038889A2 (en)

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TWI240326B (en) * 2002-10-31 2005-09-21 Tokyo Electron Ltd Method and apparatus for determining an etch property using an endpoint signal
KR100583143B1 (en) * 2004-10-29 2006-05-23 주식회사 하이닉스반도체 Method for fabricating semiconductor device with gate spacer
FR2880470B1 (en) * 2004-12-31 2007-04-20 Cit Alcatel DEVICE AND METHOD FOR CONTROLLING THE ETCH DEPTH DURING PLASMA ALTERNATE ETCHING OF SEMICONDUCTOR SUBSTRATES
US7833381B2 (en) 2005-08-18 2010-11-16 David Johnson Optical emission interferometry for PECVD using a gas injection hole
US8158017B2 (en) * 2008-05-12 2012-04-17 Lam Research Corporation Detection of arcing events in wafer plasma processing through monitoring of trace gas concentrations
CN101465289B (en) * 2009-01-14 2011-04-27 北京北方微电子基地设备工艺研究中心有限责任公司 End-point control method and device of semiconductor etching technology
US8808559B2 (en) 2011-11-22 2014-08-19 Applied Materials, Inc. Etch rate detection for reflective multi-material layers etching
CN102637588A (en) * 2012-05-04 2012-08-15 上海华力微电子有限公司 Grid electrode compensation isolation area etching method
CN103529643B (en) * 2012-07-05 2017-01-18 中国科学院物理研究所 Nano graphical system and light response characteristic detection device thereof
CN103280408B (en) * 2013-05-31 2016-08-10 上海华力微电子有限公司 The manufacture method of side wall in semiconductor device
JP2016134530A (en) * 2015-01-20 2016-07-25 株式会社東芝 Processing control apparatus, processing control program, and processing control method
CN105097456B (en) * 2015-08-24 2018-09-11 泰科天润半导体科技（北京）有限公司 A kind of Alignment Method for silicon carbide device
CN106816393A (en) * 2015-11-27 2017-06-09 中微半导体设备(上海)有限公司 Processing method for substrate and equipment
CN105632937A (en) * 2016-03-25 2016-06-01 上海华虹宏力半导体制造有限公司 Formation method of semiconductor structure
JP2019004029A (en) * 2017-06-14 2019-01-10 キヤノン株式会社 Semiconductor device manufacturing method
KR102587626B1 (en) * 2018-09-10 2023-10-11 삼성전자주식회사 Dry cleaning apparatus and dry cleaning method
US20240120209A1 (en) * 2021-06-17 2024-04-11 Lam Research Corporation Systems and methods for etching a high aspect ratio structure

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US5756216A (en) * 1993-07-09 1998-05-26 Micron Technology, Inc. Highly selective nitride spacer etch
US6180535B1 (en) * 1999-09-03 2001-01-30 Taiwan Semiconductors Manufacturing Company Approach to the spacer etch process for CMOS image sensor
US6225203B1 (en) * 1999-05-03 2001-05-01 Taiwan Semiconductor Manufacturing Company PE-SiN spacer profile for C2 SAC isolation window
US6228277B1 (en) * 1998-10-14 2001-05-08 Lucent Technologies Inc. Etch endpoint detection
US20010009245A1 (en) * 1998-05-18 2001-07-26 Allen Tuman Earl Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers

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US4618262A (en) * 1984-04-13 1986-10-21 Applied Materials, Inc. Laser interferometer system and method for monitoring and controlling IC processing
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US5741396A (en) * 1994-04-29 1998-04-21 Texas Instruments Incorporated Isotropic nitride stripping
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US5912188A (en) * 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6051504A (en) * 1997-08-15 2000-04-18 International Business Machines Corporation Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma
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US5756216A (en) * 1993-07-09 1998-05-26 Micron Technology, Inc. Highly selective nitride spacer etch
US20010009245A1 (en) * 1998-05-18 2001-07-26 Allen Tuman Earl Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers
US6228277B1 (en) * 1998-10-14 2001-05-08 Lucent Technologies Inc. Etch endpoint detection
US6225203B1 (en) * 1999-05-03 2001-05-01 Taiwan Semiconductor Manufacturing Company PE-SiN spacer profile for C2 SAC isolation window
US6180535B1 (en) * 1999-09-03 2001-01-30 Taiwan Semiconductors Manufacturing Company Approach to the spacer etch process for CMOS image sensor

Also Published As

Publication number Publication date
US6977184B1 (en) 2005-12-20
TW567572B (en) 2003-12-21
CN1633707A (en) 2005-06-29
US20060040415A1 (en) 2006-02-23
CN100468677C (en) 2009-03-11
AU2002353877A1 (en) 2003-05-12
WO2003038889A2 (en) 2003-05-08

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