WO2003044856A1 - Protective layer in memory device and method therefor - Google Patents
Protective layer in memory device and method therefor Download PDFInfo
- Publication number
- WO2003044856A1 WO2003044856A1 PCT/IL2002/000922 IL0200922W WO03044856A1 WO 2003044856 A1 WO2003044856 A1 WO 2003044856A1 IL 0200922 W IL0200922 W IL 0200922W WO 03044856 A1 WO03044856 A1 WO 03044856A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- protective layer
- nitride
- polysilicon
- fonning
- Prior art date
Links
- 239000011241 protective layer Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000010410 layer Substances 0.000 claims abstract description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 150000004767 nitrides Chemical class 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000006097 ultraviolet radiation absorber Substances 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 230000005641 tunneling Effects 0.000 description 6
- 238000007667 floating Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000006096 absorbing agent Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/954—Making oxide-nitride-oxide device
Definitions
- the present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
- the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased.
- the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon
- SONOS non-volatile memory metal oxide semiconductor
- MOS metal oxide semiconductor
- Fig. 1 illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer. It is typically formed of a gate oxide 10 over which is a polysilicon element 12. On either side of the gate oxide 10 are field oxides 14 which are much thicker than the gate oxide 10. Typically, the polysilicon element 12 also spreads over the field oxides 14. A more advanced process may have trench isolation instead of field oxides, but the effects discussed hereinbelow are the same in such a case.
- CMOS complementary MOS
- the field oxides 14 are first produced on a substrate 8, after which the gate oxides 10 are grown.
- a layer of polysilicon is laid over the oxides 10 and 14, and then etched to the desired shapes, such as by employing a shaped photoresist layer 15.
- the etching process typically involves placing a plasma 16, as is now explained.
- the etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CND) and reactive ion etching (RIE) are veiy common.
- energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a plasma 16.
- the RF energy may be supplied by an RF generator coupled to a power supply, h Fig. 1, the etching process involves placing plasma 16 between the transistor and a electrified plate 18 connected to a high voltage source, and electrically connecting a second electrified plate 20 to the substrate 8.
- Plasma may generate ultraviolet (UN) photons. UV photons may also be generated during deposition of metal layers, such as in sputtering techniques.
- High energy electrons associated with the UN photons may charge the transistor. More specifically, since polysilicon is a conductive material, the polysilicon element 12 may become charged by the high energy photons. This is known as the "charging effect". The charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade the gate oxide as is now explained.
- the extent of the F-N tunneling is a function of the size of the polysilicon element 12, the area of the gate oxide 10 and its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times the area over the thin gate oxides 10 (where K, called the "antenna ratio", varies according to the specific manufacturing process), the F-N tunneling will not occur. Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the amount of F-N tunneling may be reduced by reducing the area of the field oxide relative to the area of the gate.
- NROM devices similar to the CMOS and floating gate memory devices, the abovementioned chargmg effect may be reduced by various techniques, such as the reduction of the antenna ratio K and adding discharge devices along the poly lines.
- Such techniques are discussed in applicant/assignee's US Patent Application 09/336,666, filed June 18, 1999 and entitled "Method and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devices".
- excess charge may accumulate along the edges of word lines. The excess charge is not uniform, and increases the threshold voltage V t of the cell. The increase in threshold voltage being non-unifonn across the device width, may degrade the reliability and endurance of the cell.
- the present invention seeks to provide methods and apparatus for protecting against
- the invention may be used in any combination
- non- volatile memory device particularly a memory device with a non-conducting charge layer.
- a protective layer is formed in the NROM device over a polycide structure (e.g., a word line).
- the protective layer is formed in the NROM device over a polycide structure (e.g., a word line).
- Nitride is a good absorber of UV
- One preferred nitride comprises a thick silicon-rich silicon nitride alloy. Additionally or alternatively, the
- protective layer may comprise a layer of highly resistive undoped polysilicon.
- invention a method for protecting a non- volatile memory device, the method including fonning a
- non- volatile memory device including a polycide structure formed over a non-conducting charge
- protective layer being adapted to absorb electromagnetic wave energy having a wavelength
- non-volatile memory device including a polycide structure formed over a
- non-conducting charge trapping layer and a protective layer formed over at least a portion of the
- the protective layer being adapted to absorb electromagnetic wave energy
- the protective layer includes an ultraviolet absorber.
- the protective layer includes a nitride layer.
- the nitride layer includes a silicon-rich silicon nitride alloy.
- the nitride layer includes Si 3+X N 4 , wherein x > 0.
- the nitride l o layer includes a hydrogenated silicon-rich silicon nitride alloy.
- the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
- the protective layer includes a mtride layer with a thickness of 50-1000 A. 15 Further in accordance with a preferred embodiment of the present invention the protective layer includes a layer of resistive undoped polysilicon.
- protective layer of undoped polysilicon includes a resistivity of at least 1 G ⁇ .
- the protective 0 layer of undoped polysilicon includes a thickness of 30-600 A.
- Furtlier in accordance with a preferred embodiment of the present invention at least one additional layer is formed over the protective layer.
- the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer.
- the polycide structure includes a polysilicon layer and a metal silicide film.
- the polysilicon layer includes a polycrystalline silicon (polysilicon).
- the polysilicon layer may or may not be doped with a dopant.
- the metal silicide film mcludes at least one of a tungsten silicide film and a titanium silicide fihn.
- the non- volatile memory device mcludes a nitride, read only memory (NROM) device, and the non-conducting charge trapping layer mcludes a nitride charge trapping layer.
- NROM read only memory
- Fig. 1 is a schematic illustration of a prior art metal oxide semiconductor (MOS) transistor in a semiconductor chip during an etching operation;
- MOS metal oxide semiconductor
- Fig. 2 is a simplified illustration of a chargmg effect in an NROM non- volatile memory device
- Figs. 3 and 4 are simplified cross-sectional illustrations of application of a protective layer over portions of the NROM device of Fig. 2, in accordance with a preferced embodiment of the present invention, wherem Fig. 3 is a cross-section along poly lines and Fig. 4 is a cross-section of word lines between bit lines.
- Fig. 2 illustrates a charging effect in an NROM non- volatile memory device 43, which includes one or more word lines (WL) 40 and bit lines (BL) 42.
- Bit lines 42 may be separated from each other by a distance LD.
- portions of device 43 such as but not limited to, edges 50 of word line 40, may accumulate charge (indicated by dots along edges 50 in Fig. 2) due to the deleterious charge effect mentioned hereinabove.
- WL 40 may comprise a polycide structure, comprising for example, a lower polysilicon layer 44 and an upper layer formed of a metal silicide film 48.
- Polysilicon layer 44 may comprise without limitation a polycrystalline silicon (polysilicon), which may or may not be doped with a dopant such as phosphorus, for example.
- Metal silicide film 48 may comprise without limitation a tungsten silicide film or a titanium sihcide fihn, for example.
- the polycide structure of polysilicon layer 44 and metal silicide film 48 may be formed over an ONO layer 46.
- ONO layer 46 is also referred to as a nitride charge trapping layer.
- bit line 42 may include a BL oxide layer 54 and a BL junction 56.
- Additional layers may be formed over polysilicon layer 44 and metal silicide film 48.
- Such layers may include, without limitation, a layer of undoped glass 60 (silicon dioxide), a layer of doped glass 62, and a metal layer 64.
- the doped glass layer 62 may comprise borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG), for example.
- the additional layers may be grown, or deposited by physical deposition (e.g., sputtering) or fonned by any other suitable technique, and are generally etched to their final dimensions and form by plasma etching. As mentioned hereinabove, high energy electrons from UN light photons generated by the sputtering and etching may cause charge to be accumulated in the edges 50.
- a protective layer 52 is applied over at least a portion of the polycide structure of polysilicon layer 44 and metal silicide film 48.
- the protective layer 52 may be applied prior to the formation of the additional layers 60 and 62.
- the protective layer 52 may be applied over additional layers 60 and 62, and prior to the fonnation of the metal layer 64, as seen in Fig. 3.
- the protective layer 52 has the property of absorbing electromagnetic wave energy, such as but not lhnited to UN light, and serves as a protective mask that may prevent high energy photons from reaching the polycide structure of polysilicon layer 44 and metal silicide film 48 while sputtering and etching the additional layers 60 and 62, or metal layer 64. h general, protective layer 52 may absorb electromagnetic wave energy having a wavelength shorter than visible light.
- the protective layer 52 comprises an ultraviolet absorber, e.g., a nitride layer.
- Nitride is a good absorber of UV energy, and accordingly may prevent UN photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48, or gate stress in the O ⁇ O layer 46.
- One preferred nitride comprises a silicon-rich silicon nitride alloy, such as Si 3+X ⁇ 4 , wherein x > 0.
- the silicon-rich silicon mtride alloy may be hydrogenated and/or amorphous.
- the mtride layer is preferably relatively very thick, such as witliout limitation, in the range of 50-1000 A.
- the nitride layer may be fonned using any suitable technique, such as but not limited to, a low pressure chemical vapor deposition technique (LPCVD).
- the protective layer 52 may comprise a layer of highly resistive undoped polysilicon.
- the layer of undoped polysilicon may be deposited using any suitable technique, such as but not limited to, CND methods.
- the undoped polysilicon layer is preferably relatively very thin, such as without limitation, in the range of 30-600 A.
- polysilicon layer preferably has a high resistance, such as without limitation, at least 1 G ⁇ .
- the additional layers 60 and 62 may be formed over protective layer 52, such as but not limited to, by sputtering and etching. If the protective layer 52 has been formed over the additional layers 60 and 62, the metal layer 64 may be deposited or etched over protective layer 52, for example.
- the protective layer 52 may have a high electrical resistivity so as to prevent leakage from one contact to another contact (or from one via to another via) formed in the device 43. The protective layer 52 may thus prevent electrical stress and gate stress problems, as well as prevent leakage between contacts in device 43.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002353459A AU2002353459A1 (en) | 2001-11-19 | 2002-11-19 | Protective layer in memory device and method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/988,122 US7098107B2 (en) | 2001-11-19 | 2001-11-19 | Protective layer in memory device and method therefor |
US09/988,122 | 2001-11-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003044856A1 true WO2003044856A1 (en) | 2003-05-30 |
Family
ID=25533873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2002/000922 WO2003044856A1 (en) | 2001-11-19 | 2002-11-19 | Protective layer in memory device and method therefor |
Country Status (6)
Country | Link |
---|---|
US (3) | US7098107B2 (en) |
EP (1) | EP1313138A3 (en) |
JP (1) | JP2003243545A (en) |
AU (1) | AU2002353459A1 (en) |
IL (1) | IL152913A0 (en) |
WO (1) | WO2003044856A1 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004193585A (en) * | 2002-11-29 | 2004-07-08 | Fujitsu Ltd | Method for manufacturing semiconductor device and semiconductor device |
US6774432B1 (en) * | 2003-02-05 | 2004-08-10 | Advanced Micro Devices, Inc. | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
US7060554B2 (en) * | 2003-07-11 | 2006-06-13 | Advanced Micro Devices, Inc. | PECVD silicon-rich oxide layer for reduced UV charging |
US6869844B1 (en) * | 2003-11-05 | 2005-03-22 | Advanced Micro Device, Inc. | Method and structure for protecting NROM devices from induced charge damage during device fabrication |
US6989563B1 (en) | 2004-02-02 | 2006-01-24 | Advanced Micro Devices, Inc. | Flash memory cell with UV protective layer |
US7157331B2 (en) * | 2004-06-01 | 2007-01-02 | Macronix International Co., Ltd. | Ultraviolet blocking layer |
US7091088B1 (en) | 2004-06-03 | 2006-08-15 | Spansion Llc | UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing |
JP2005347589A (en) | 2004-06-04 | 2005-12-15 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor memory device and method for manufacturing the same |
JP4813778B2 (en) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP2006032797A (en) | 2004-07-20 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor storage device and its manufacturing method |
US7335610B2 (en) * | 2004-07-23 | 2008-02-26 | Macronix International Co., Ltd. | Ultraviolet blocking layer |
US20060141804A1 (en) * | 2004-12-28 | 2006-06-29 | Goodman Cathryn E | Method and apparatus to facilitate electrostatic discharge resiliency |
US8022468B1 (en) * | 2005-03-29 | 2011-09-20 | Spansion Llc | Ultraviolet radiation blocking interlayer dielectric |
JP2007158289A (en) * | 2005-11-11 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor storage device and manufacturing method of the same |
US7662712B2 (en) * | 2006-02-10 | 2010-02-16 | Macronix International Co., Ltd. | UV blocking and crack protecting passivation layer fabricating method |
US7755197B2 (en) * | 2006-02-10 | 2010-07-13 | Macronix International Co., Ltd. | UV blocking and crack protecting passivation layer |
US7498228B2 (en) * | 2007-07-09 | 2009-03-03 | United Microelectronics Corp. | Method for fabricating SONOS a memory |
JP2009021319A (en) * | 2007-07-11 | 2009-01-29 | Panasonic Corp | Nonvolatile semiconductor storage device and manufacturing method thereof |
JP2010212454A (en) * | 2009-03-10 | 2010-09-24 | Panasonic Corp | Nonvolatile semiconductor memory device |
JP2011003600A (en) * | 2009-06-16 | 2011-01-06 | Panasonic Corp | Method of fabricating semiconductor memory device |
US8866213B2 (en) | 2013-01-30 | 2014-10-21 | Spansion Llc | Non-Volatile memory with silicided bit line contacts |
TWI708373B (en) * | 2016-10-11 | 2020-10-21 | 聯華電子股份有限公司 | Flash memory structure |
CN109659275B (en) * | 2017-10-10 | 2020-11-03 | 联华电子股份有限公司 | Method for manufacturing dynamic random access memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4665426A (en) * | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
US5120672A (en) * | 1989-02-22 | 1992-06-09 | Texas Instruments Incorporated | Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region |
US5334555A (en) * | 1991-11-06 | 1994-08-02 | Sony Corporation | Method of determining conditions for plasma silicon nitride film growth and method of manufacturing semiconductor device |
Family Cites Families (187)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2004A (en) * | 1841-03-12 | Improvement in the manner of constructing and propelling steam-vessels | ||
US596929A (en) * | 1898-01-04 | James godfrey wilson | ||
GB1297899A (en) | 1970-10-02 | 1972-11-29 | ||
US3895360A (en) | 1974-01-29 | 1975-07-15 | Westinghouse Electric Corp | Block oriented random access memory |
US4016588A (en) | 1974-12-27 | 1977-04-05 | Nippon Electric Company, Ltd. | Non-volatile semiconductor memory device |
US4016688A (en) * | 1975-05-27 | 1977-04-12 | Fmc Corporation | Extensible crane boom structure |
US4017888A (en) | 1975-12-31 | 1977-04-12 | International Business Machines Corporation | Non-volatile metal nitride oxide semiconductor device |
US4151021A (en) | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
US4145703A (en) * | 1977-04-15 | 1979-03-20 | Supertex, Inc. | High power MOS device and fabrication method therefor |
US4173766A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory cell |
US4173791A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory array |
US4373248A (en) * | 1978-07-12 | 1983-02-15 | Texas Instruments Incorporated | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like |
DE2832388C2 (en) | 1978-07-24 | 1986-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Process for the production of MNOS and MOS transistors in silicon gate technology on a semiconductor substrate |
US4360900A (en) | 1978-11-27 | 1982-11-23 | Texas Instruments Incorporated | Non-volatile semiconductor memory elements |
US4247861A (en) * | 1979-03-09 | 1981-01-27 | Rca Corporation | High performance electrically alterable read-only memory (EAROM) |
DE2923995C2 (en) | 1979-06-13 | 1985-11-07 | Siemens AG, 1000 Berlin und 8000 München | Process for the production of integrated MOS circuits with MOS transistors and MNOS memory transistors in silicon gate technology |
JPS56501146A (en) | 1979-09-13 | 1981-08-13 | ||
JPS5656677A (en) * | 1979-10-13 | 1981-05-18 | Toshiba Corp | Semiconductor memory device |
DE2947350A1 (en) | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING MNOS STORAGE TRANSISTORS WITH A VERY SHORT CHANNEL LENGTH IN SILICON GATE TECHNOLOGY |
JPS56120166A (en) | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
US4380057A (en) | 1980-10-27 | 1983-04-12 | International Business Machines Corporation | Electrically alterable double dense memory |
US4521796A (en) | 1980-12-11 | 1985-06-04 | General Instrument Corporation | Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device |
US4435786A (en) * | 1981-11-23 | 1984-03-06 | Fairchild Camera And Instrument Corporation | Self-refreshing memory cell |
US4494016A (en) * | 1982-07-26 | 1985-01-15 | Sperry Corporation | High performance MESFET transistor for VLSI implementation |
US4527257A (en) | 1982-08-25 | 1985-07-02 | Westinghouse Electric Corp. | Common memory gate non-volatile transistor memory |
JPS6021531A (en) * | 1983-07-15 | 1985-02-02 | Hitachi Micro Comput Eng Ltd | Nonvolatile semiconductor memory |
US4769340A (en) | 1983-11-28 | 1988-09-06 | Exel Microelectronics, Inc. | Method for making electrically programmable memory device by doping the floating gate by implant |
US4725984A (en) * | 1984-02-21 | 1988-02-16 | Seeq Technology, Inc. | CMOS eprom sense amplifier |
JPS60182174A (en) | 1984-02-28 | 1985-09-17 | Nec Corp | Non-volatile semiconductor memory |
GB2157489A (en) | 1984-03-23 | 1985-10-23 | Hitachi Ltd | A semiconductor integrated circuit memory device |
US4667217A (en) | 1985-04-19 | 1987-05-19 | Ncr Corporation | Two bit vertically/horizontally integrated memory cell |
JPH0831789B2 (en) * | 1985-09-04 | 1996-03-27 | 沖電気工業株式会社 | Output circuit |
US4742491A (en) | 1985-09-26 | 1988-05-03 | Advanced Micro Devices, Inc. | Memory cell having hot-hole injection erase mode |
JPH0828431B2 (en) | 1986-04-22 | 1996-03-21 | 日本電気株式会社 | Semiconductor memory device |
US4758869A (en) * | 1986-08-29 | 1988-07-19 | Waferscale Integration, Inc. | Nonvolatile floating gate transistor structure |
US5168334A (en) | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
US4780424A (en) | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
US4870470A (en) | 1987-10-16 | 1989-09-26 | International Business Machines Corporation | Non-volatile memory cell having Si rich silicon nitride charge trapping layer |
JPH07120720B2 (en) | 1987-12-17 | 1995-12-20 | 三菱電機株式会社 | Nonvolatile semiconductor memory device |
US5159570A (en) | 1987-12-22 | 1992-10-27 | Texas Instruments Incorporated | Four memory state EEPROM |
US5268870A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Flash EEPROM system and intelligent programming and erasing methods therefor |
US4941028A (en) | 1988-08-10 | 1990-07-10 | Actel Corporation | Structure for protecting thin dielectrics during processing |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US5104819A (en) | 1989-08-07 | 1992-04-14 | Intel Corporation | Fabrication of interpoly dielctric for EPROM-related technologies |
US5095968A (en) * | 1990-04-09 | 1992-03-17 | Didion Manufacturing Co. | Rotary media drum with cooling component |
US5075245A (en) | 1990-08-03 | 1991-12-24 | Intel Corporation | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps |
US5289406A (en) | 1990-08-28 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Read only memory for storing multi-data |
KR920006991A (en) * | 1990-09-25 | 1992-04-28 | 김광호 | High Voltage Generation Circuit of Semiconductor Memory Device |
US5081371A (en) * | 1990-11-07 | 1992-01-14 | U.S. Philips Corp. | Integrated charge pump circuit with back bias voltage reduction |
JP3002309B2 (en) * | 1990-11-13 | 2000-01-24 | ウエハスケール インテグレーション, インコーポレイテッド | High-speed EPROM array |
US5086325A (en) * | 1990-11-21 | 1992-02-04 | Atmel Corporation | Narrow width EEPROM with single diffusion electrode formation |
JPH0725489Y2 (en) * | 1990-11-24 | 1995-06-07 | 株式会社堀場製作所 | Pinch valve |
JP2612969B2 (en) | 1991-02-08 | 1997-05-21 | シャープ株式会社 | Method for manufacturing semiconductor device |
US5424567A (en) | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
GB9111947D0 (en) * | 1991-06-04 | 1991-07-24 | Telsis Limited | Apparatus for voice services equipment |
JP3109537B2 (en) | 1991-07-12 | 2000-11-20 | 日本電気株式会社 | Read-only semiconductor memory device |
JP2965415B2 (en) | 1991-08-27 | 1999-10-18 | 松下電器産業株式会社 | Semiconductor storage device |
ES2197905T3 (en) | 1991-08-29 | 2004-01-16 | Hyundai Electronics Industries Co., Ltd. | EEPROM MEMORY CELL FLASH DOOR DIVIDED DOUBLE BIT (DSG) SELF-ALIGNED. |
US5305262A (en) | 1991-09-11 | 1994-04-19 | Kawasaki Steel Corporation | Semiconductor integrated circuit |
US5175120A (en) | 1991-10-11 | 1992-12-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
JPH05110114A (en) | 1991-10-17 | 1993-04-30 | Rohm Co Ltd | Nonvolatile semiconductor memory device |
JP3358663B2 (en) | 1991-10-25 | 2002-12-24 | ローム株式会社 | Semiconductor storage device and storage information reading method thereof |
US5338954A (en) | 1991-10-31 | 1994-08-16 | Rohm Co., Ltd. | Semiconductor memory device having an insulating film and a trap film joined in a channel region |
JP2564067B2 (en) * | 1992-01-09 | 1996-12-18 | 株式会社東芝 | Readout output circuit having sense circuit |
US5293328A (en) | 1992-01-15 | 1994-03-08 | National Semiconductor Corporation | Electrically reprogrammable EPROM cell with merged transistor and optiumum area |
US5654568A (en) | 1992-01-17 | 1997-08-05 | Rohm Co., Ltd. | Semiconductor device including nonvolatile memories |
JP2851962B2 (en) * | 1992-01-21 | 1999-01-27 | シャープ株式会社 | Semiconductor read-only memory |
EP0552531B1 (en) * | 1992-01-22 | 2000-08-16 | Macronix International Co., Ltd. | Non-volatile memory cell and array architecture |
US5324675A (en) | 1992-03-31 | 1994-06-28 | Kawasaki Steel Corporation | Method of producing semiconductor devices of a MONOS type |
JPH05290584A (en) * | 1992-04-08 | 1993-11-05 | Nec Corp | Semiconductor memory |
EP0597124B1 (en) | 1992-05-29 | 1998-12-09 | Citizen Watch Co. Ltd. | Method of fabricating a semiconductor nonvolatile storage device |
US5289412A (en) * | 1992-06-19 | 1994-02-22 | Intel Corporation | High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories |
GB9217743D0 (en) | 1992-08-19 | 1992-09-30 | Philips Electronics Uk Ltd | A semiconductor memory device |
US5412238A (en) | 1992-09-08 | 1995-05-02 | National Semiconductor Corporation | Source-coupling, split-gate, virtual ground flash EEPROM array |
US5280420A (en) * | 1992-10-02 | 1994-01-18 | National Semiconductor Corporation | Charge pump which operates on a low voltage power supply |
US5418743A (en) * | 1992-12-07 | 1995-05-23 | Nippon Steel Corporation | Method of writing into non-volatile semiconductor memory |
US5319593A (en) | 1992-12-21 | 1994-06-07 | National Semiconductor Corp. | Memory array with field oxide islands eliminated and method |
JPH07114792A (en) * | 1993-10-19 | 1995-05-02 | Mitsubishi Electric Corp | Semiconductor memory |
US5436481A (en) | 1993-01-21 | 1995-07-25 | Nippon Steel Corporation | MOS-type semiconductor device and method of making the same |
US5393701A (en) | 1993-04-08 | 1995-02-28 | United Microelectronics Corporation | Layout design to eliminate process antenna effect |
US5350710A (en) | 1993-06-24 | 1994-09-27 | United Microelectronics Corporation | Device for preventing antenna effect on circuit |
US5477499A (en) | 1993-10-13 | 1995-12-19 | Advanced Micro Devices, Inc. | Memory architecture for a three volt flash EEPROM |
US5983412A (en) * | 1993-11-29 | 1999-11-16 | Lordahl; Var E. | Toilet tank ball flapper and plastic chain assembly formed as a unitary structures |
JPH07193151A (en) | 1993-12-27 | 1995-07-28 | Toshiba Corp | Non-volatile semiconductor storage and its storage method |
FR2715758B1 (en) * | 1994-01-31 | 1996-03-22 | Sgs Thomson Microelectronics | Source-programmable, non-volatile flip-flop, especially for memory redundancy circuits. |
FR2715782B1 (en) * | 1994-01-31 | 1996-03-22 | Sgs Thomson Microelectronics | Programmable non-volatile bistable flip-flop, with predefined initial state, in particular for memory redundancy circuit. |
US5418176A (en) | 1994-02-17 | 1995-05-23 | United Microelectronics Corporation | Process for producing memory devices having narrow buried N+ lines |
US5467308A (en) | 1994-04-05 | 1995-11-14 | Motorola Inc. | Cross-point eeprom memory array |
US5553081A (en) * | 1994-04-08 | 1996-09-03 | Echelon Corporation | Apparatus and method for detecting a signal in a communications system |
TW241394B (en) * | 1994-05-26 | 1995-02-21 | Aplus Integrated Circuits Inc | Flat-cell ROM and decoder |
JP3725911B2 (en) | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | Semiconductor device |
EP0691729A3 (en) * | 1994-06-30 | 1996-08-14 | Sgs Thomson Microelectronics | Charge pump circuit with feedback control |
EP0696050B1 (en) | 1994-07-18 | 1998-10-14 | STMicroelectronics S.r.l. | EPROM and Flash-EEPROM non-volatile memory and method of manufacturing the same |
JPH08181284A (en) | 1994-09-13 | 1996-07-12 | Hewlett Packard Co <Hp> | Protective element and manufacture thereof |
JP3730272B2 (en) * | 1994-09-17 | 2005-12-21 | 株式会社東芝 | Nonvolatile semiconductor memory device |
DE4434725C1 (en) | 1994-09-28 | 1996-05-30 | Siemens Ag | Fixed value memory cell arrangement and method for the production thereof |
US5619052A (en) | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
US5523251A (en) | 1994-10-05 | 1996-06-04 | United Microelectronics Corp. | Method for fabricating a self aligned mask ROM |
JP3670321B2 (en) * | 1994-10-18 | 2005-07-13 | 住友化学株式会社 | Crosshead die and method for producing long fiber reinforced resin structure |
US5599727A (en) | 1994-12-15 | 1997-02-04 | Sharp Kabushiki Kaisha | Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed |
DE19504398A1 (en) * | 1995-02-10 | 1996-08-14 | Beiersdorf Ag | Tocopherylglycoside, their preparation and their use as surfactants, as antioxidants and as a cell aging preventive agent in cosmetic or pharmaceutical preparations |
DE19505293A1 (en) | 1995-02-16 | 1996-08-22 | Siemens Ag | Multi-value read-only memory cell with improved signal-to-noise ratio |
US5801076A (en) | 1995-02-21 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of making non-volatile memory device having a floating gate with enhanced charge retention |
US5518942A (en) | 1995-02-22 | 1996-05-21 | Alliance Semiconductor Corporation | Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant |
KR100187656B1 (en) | 1995-05-16 | 1999-06-01 | 김주용 | Method for manufacturing a flash eeprom and the programming method |
US5656513A (en) | 1995-06-07 | 1997-08-12 | Advanced Micro Devices, Inc. | Nonvolatile memory cell formed using self aligned source implant |
EP0751560B1 (en) | 1995-06-30 | 2002-11-27 | STMicroelectronics S.r.l. | Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC |
AU6185196A (en) | 1995-07-03 | 1997-02-05 | Elvira Gulerson | Method of fabricating a fast programming flash e2prm cell |
US5903031A (en) | 1995-07-04 | 1999-05-11 | Matsushita Electric Industrial Co., Ltd. | MIS device, method of manufacturing the same, and method of diagnosing the same |
US5721781A (en) * | 1995-09-13 | 1998-02-24 | Microsoft Corporation | Authentication system and method for smart card transactions |
US5604804A (en) * | 1996-04-23 | 1997-02-18 | Micali; Silvio | Method for certifying public keys in a digital signature scheme |
JP2982670B2 (en) | 1995-12-12 | 1999-11-29 | 日本電気株式会社 | Nonvolatile semiconductor storage device and storage method |
KR100223747B1 (en) * | 1995-12-28 | 1999-10-15 | 김영환 | Output buffer with fast speed and low noise |
US5712815A (en) * | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
US5847441A (en) | 1996-05-10 | 1998-12-08 | Micron Technology, Inc. | Semiconductor junction antifuse circuit |
US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
JP2882370B2 (en) * | 1996-06-28 | 1999-04-12 | 日本電気株式会社 | Semiconductor storage device |
US6156149A (en) * | 1997-05-07 | 2000-12-05 | Applied Materials, Inc. | In situ deposition of a dielectric oxide layer and anti-reflective coating |
US5793079A (en) | 1996-07-22 | 1998-08-11 | Catalyst Semiconductor, Inc. | Single transistor non-volatile electrically alterable semiconductor memory device |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US5787484A (en) * | 1996-08-08 | 1998-07-28 | Micron Technology, Inc. | System and method which compares data preread from memory cells to data to be written to the cells |
US5717635A (en) * | 1996-08-27 | 1998-02-10 | International Business Machines Corporation | High density EEPROM for solid state file |
US5873113A (en) * | 1996-09-24 | 1999-02-16 | Altera Corporation | System and method for programming eprom cells using shorter duration pulse(s) in repeating the programming process of a particular cell |
JPH10133754A (en) * | 1996-10-28 | 1998-05-22 | Fujitsu Ltd | Regulator circuit and semiconductor integrated circuit device |
US5717632A (en) * | 1996-11-27 | 1998-02-10 | Advanced Micro Devices, Inc. | Apparatus and method for multiple-level storage in non-volatile memories |
TW318283B (en) | 1996-12-09 | 1997-10-21 | United Microelectronics Corp | Multi-level read only memory structure and manufacturing method thereof |
KR100232678B1 (en) * | 1996-12-18 | 1999-12-01 | 구본준 | A structure and a method of ridged bump |
TW347581B (en) | 1997-02-05 | 1998-12-11 | United Microelectronics Corp | Process for fabricating read-only memory cells |
US6103572A (en) * | 1997-02-07 | 2000-08-15 | Citizen Watch Co., Ltd. | Method of fabricating a semiconductor nonvolatile storage device |
US5872848A (en) * | 1997-02-18 | 1999-02-16 | Arcanvs | Method and apparatus for witnessed authentication of electronic documents |
US5870335A (en) | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US6028324A (en) | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
US6190966B1 (en) * | 1997-03-25 | 2001-02-20 | Vantis Corporation | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration |
TW381325B (en) | 1997-04-15 | 2000-02-01 | United Microelectronics Corp | Three dimensional high density deep trench ROM and the manufacturing method thereof |
US6297096B1 (en) | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
US6335990B1 (en) * | 1997-07-03 | 2002-01-01 | Cisco Technology, Inc. | System and method for spatial temporal-filtering for improving compressed digital video |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US5963412A (en) | 1997-11-13 | 1999-10-05 | Advanced Micro Devices, Inc. | Process induced charging damage control device |
US5867429A (en) * | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
US5963465A (en) * | 1997-12-12 | 1999-10-05 | Saifun Semiconductors, Ltd. | Symmetric segmented memory array architecture |
US6020241A (en) | 1997-12-22 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Post metal code engineering for a ROM |
US6195196B1 (en) * | 1998-03-13 | 2001-02-27 | Fuji Photo Film Co., Ltd. | Array-type exposing device and flat type display incorporating light modulator and driving method thereof |
US6344959B1 (en) * | 1998-05-01 | 2002-02-05 | Unitrode Corporation | Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage |
US6030871A (en) | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
US6188211B1 (en) * | 1998-05-13 | 2001-02-13 | Texas Instruments Incorporated | Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response |
US6348711B1 (en) * | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6063666A (en) | 1998-06-16 | 2000-05-16 | Advanced Micro Devices, Inc. | RTCVD oxide and N2 O anneal for top oxide of ONO film |
US6034403A (en) | 1998-06-25 | 2000-03-07 | Acer Semiconductor Manufacturing, Inc. | High density flat cell mask ROM |
DE69828966D1 (en) * | 1998-09-15 | 2005-03-17 | St Microelectronics Srl | Method for protecting the content of non-volatile memory cells |
US5991202A (en) | 1998-09-24 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for reducing program disturb during self-boosting in a NAND flash memory |
US6282145B1 (en) * | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6181597B1 (en) * | 1999-02-04 | 2001-01-30 | Tower Semiconductor Ltd. | EEPROM array using 2-bit non-volatile memory cells with serial read operations |
US6346442B1 (en) * | 1999-02-04 | 2002-02-12 | Tower Semiconductor Ltd. | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
WO2000070675A1 (en) * | 1999-05-14 | 2000-11-23 | Hitachi, Ltd. | Semiconductor memory device |
JP2000332241A (en) * | 1999-05-20 | 2000-11-30 | Nec Corp | Manufacture of semiconductor device |
US6337502B1 (en) | 1999-06-18 | 2002-01-08 | Saifun Semicinductors Ltd. | Method and circuit for minimizing the charging effect during manufacture of semiconductor devices |
US6175519B1 (en) * | 1999-07-22 | 2001-01-16 | Macronix International Co., Ltd. | Virtual ground EPROM structure |
US6181605B1 (en) * | 1999-10-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Global erase/program verification apparatus and method |
US6175523B1 (en) * | 1999-10-25 | 2001-01-16 | Advanced Micro Devices, Inc | Precharging mechanism and method for NAND-based flash memory devices |
JP2001143487A (en) * | 1999-11-15 | 2001-05-25 | Nec Corp | Semiconductor memory |
US6185143B1 (en) * | 2000-02-04 | 2001-02-06 | Hewlett-Packard Company | Magnetic random access memory (MRAM) device including differential sense amplifiers |
US6343033B1 (en) * | 2000-02-25 | 2002-01-29 | Advanced Micro Devices, Inc. | Variable pulse width memory programming |
DE10017920A1 (en) * | 2000-04-11 | 2001-10-25 | Infineon Technologies Ag | Charge pump arrangement |
JP4707803B2 (en) * | 2000-07-10 | 2011-06-22 | エルピーダメモリ株式会社 | Error rate determination method and semiconductor integrated circuit device |
US6519182B1 (en) * | 2000-07-10 | 2003-02-11 | Advanced Micro Devices, Inc. | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure |
US6348380B1 (en) * | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
US6348381B1 (en) * | 2001-02-21 | 2002-02-19 | Macronix International Co., Ltd. | Method for forming a nonvolatile memory with optimum bias condition |
DE10110150A1 (en) * | 2001-03-02 | 2002-09-19 | Infineon Technologies Ag | Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array |
US6351415B1 (en) * | 2001-03-28 | 2002-02-26 | Tower Semiconductor Ltd. | Symmetrical non-volatile memory array architecture without neighbor effect |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6493266B1 (en) * | 2001-04-09 | 2002-12-10 | Advanced Micro Devices, Inc. | Soft program and soft program verify of the core cells in flash memory array |
US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
US6512701B1 (en) * | 2001-06-21 | 2003-01-28 | Advanced Micro Devices, Inc. | Erase method for dual bit virtual ground flash |
US6462387B1 (en) * | 2001-06-29 | 2002-10-08 | Chinatech Corporation | High density read only memory |
US6525969B1 (en) * | 2001-08-10 | 2003-02-25 | Advanced Micro Devices, Inc. | Decoder apparatus and methods for pre-charging bit lines |
US6440797B1 (en) * | 2001-09-28 | 2002-08-27 | Advanced Micro Devices, Inc. | Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory |
US6510082B1 (en) * | 2001-10-23 | 2003-01-21 | Advanced Micro Devices, Inc. | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold |
US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US6706595B2 (en) * | 2002-03-14 | 2004-03-16 | Advanced Micro Devices, Inc. | Hard mask process for memory device without bitline shorts |
US6690602B1 (en) * | 2002-04-08 | 2004-02-10 | Advanced Micro Devices, Inc. | Algorithm dynamic reference programming |
CN1292356C (en) * | 2002-04-17 | 2006-12-27 | 松下电器产业株式会社 | Nonvolatile semiconductor memory device and its secret protection method |
US6813189B2 (en) * | 2002-07-16 | 2004-11-02 | Fujitsu Limited | System for using a dynamic reference in a double-bit cell memory |
JP4260434B2 (en) * | 2002-07-16 | 2009-04-30 | 富士通マイクロエレクトロニクス株式会社 | Nonvolatile semiconductor memory and operation method thereof |
US6734063B2 (en) * | 2002-07-22 | 2004-05-11 | Infineon Technologies Ag | Non-volatile memory cell and fabrication method |
JP2004079602A (en) * | 2002-08-12 | 2004-03-11 | Fujitsu Ltd | Nonvolatile memory having trap layer |
US6859028B2 (en) * | 2002-11-26 | 2005-02-22 | Sige Semiconductor Inc. | Design-for-test modes for a phase locked loop |
-
2001
- 2001-11-19 US US09/988,122 patent/US7098107B2/en not_active Expired - Lifetime
-
2002
- 2002-07-08 US US10/189,533 patent/US6828625B2/en not_active Expired - Lifetime
- 2002-11-18 IL IL15291302A patent/IL152913A0/en not_active IP Right Cessation
- 2002-11-19 AU AU2002353459A patent/AU2002353459A1/en not_active Abandoned
- 2002-11-19 EP EP02257954A patent/EP1313138A3/en not_active Withdrawn
- 2002-11-19 JP JP2002334684A patent/JP2003243545A/en active Pending
- 2002-11-19 WO PCT/IL2002/000922 patent/WO2003044856A1/en not_active Application Discontinuation
-
2006
- 2006-07-20 US US11/490,483 patent/US20070032016A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4665426A (en) * | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
US5120672A (en) * | 1989-02-22 | 1992-06-09 | Texas Instruments Incorporated | Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region |
US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
US5334555A (en) * | 1991-11-06 | 1994-08-02 | Sony Corporation | Method of determining conditions for plasma silicon nitride film growth and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
AU2002353459A1 (en) | 2003-06-10 |
IL152913A0 (en) | 2003-06-24 |
US20030096476A1 (en) | 2003-05-22 |
JP2003243545A (en) | 2003-08-29 |
US20070032016A1 (en) | 2007-02-08 |
US20030096475A1 (en) | 2003-05-22 |
EP1313138A2 (en) | 2003-05-21 |
EP1313138A3 (en) | 2007-12-05 |
US6828625B2 (en) | 2004-12-07 |
US7098107B2 (en) | 2006-08-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070032016A1 (en) | Protective layer in memory device and method therefor | |
US8541277B2 (en) | Non-volatile memory device and method for fabricating the same | |
KR101071965B1 (en) | - uv-blocking layer for reducing uv-induced charging of sonos dual-bit flash memory devices in beol processing | |
US5449941A (en) | Semiconductor memory device | |
US4833514A (en) | Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide | |
EP0780902B1 (en) | Nonvolatile semiconductor memory and method for fabricating the same | |
US6380033B1 (en) | Process to improve read disturb for NAND flash memory devices | |
US6815283B2 (en) | Method of manufacturing semiconductor devices | |
US7439575B2 (en) | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories | |
US5933729A (en) | Reduction of ONO fence during self-aligned etch to eliminate poly stringers | |
KR101056151B1 (en) | Apparatus and method for wordline protection in flash memory devices | |
US7713875B2 (en) | Variable salicide block for resistance equalization in an array | |
EP0614223B1 (en) | Non-volatile memory with protection diode | |
KR100643468B1 (en) | Nonvolatile memory devices having insulating spacer and manufacturing method thereof | |
EP1330840A1 (en) | Non-volatile memory with source side boron implantation | |
US6894342B1 (en) | Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control | |
US7553727B2 (en) | Using implanted poly-1 to improve charging protection in dual-poly process | |
US6833581B1 (en) | Structure and method for preventing process-induced UV radiation damage in a memory cell | |
JP3947041B2 (en) | Semiconductor device and manufacturing method thereof | |
US6284602B1 (en) | Process to reduce post cycling program VT dispersion for NAND flash memory devices | |
US20040105321A1 (en) | Non-volatile memory and fabrication thereof | |
US6653189B1 (en) | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | |
KR20010045232A (en) | Method for manufacturing flash memory cell and the same | |
US8198708B2 (en) | System and method for improving CMOS compatible non volatile memory retention reliability | |
US20080057646A1 (en) | Nonvolatile memory device and methods of fabricating and driving the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: JP |