WO2003046979A3 - Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect - Google Patents

Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect Download PDF

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Publication number
WO2003046979A3
WO2003046979A3 PCT/US2002/032605 US0232605W WO03046979A3 WO 2003046979 A3 WO2003046979 A3 WO 2003046979A3 US 0232605 W US0232605 W US 0232605W WO 03046979 A3 WO03046979 A3 WO 03046979A3
Authority
WO
WIPO (PCT)
Prior art keywords
copper alloy
ternary copper
grain size
low resistance
large grain
Prior art date
Application number
PCT/US2002/032605
Other languages
French (fr)
Other versions
WO2003046979A2 (en
Inventor
Sergey Lopatin
Paul R Besser
Pin-Chin Connie Wang
Original Assignee
Advanced Micro Devices Inc
Sergey Lopatin
Paul R Besser
Pin-Chin Connie Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Sergey Lopatin, Paul R Besser, Pin-Chin Connie Wang filed Critical Advanced Micro Devices Inc
Priority to EP02770570A priority Critical patent/EP1449247A2/en
Priority to KR1020047007985A priority patent/KR100966359B1/en
Priority to AU2002335805A priority patent/AU2002335805A1/en
Priority to JP2003548301A priority patent/JP4463555B2/en
Publication of WO2003046979A2 publication Critical patent/WO2003046979A2/en
Publication of WO2003046979A3 publication Critical patent/WO2003046979A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
PCT/US2002/032605 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect WO2003046979A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02770570A EP1449247A2 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
KR1020047007985A KR100966359B1 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
AU2002335805A AU2002335805A1 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
JP2003548301A JP4463555B2 (en) 2001-11-26 2002-10-11 Using ternary copper alloy to obtain low resistance, large grain size wiring

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,395 US7696092B2 (en) 2001-11-26 2001-11-26 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
US09/994,395 2001-11-26

Publications (2)

Publication Number Publication Date
WO2003046979A2 WO2003046979A2 (en) 2003-06-05
WO2003046979A3 true WO2003046979A3 (en) 2003-10-30

Family

ID=25540628

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/032605 WO2003046979A2 (en) 2001-11-26 2002-10-11 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Country Status (7)

Country Link
US (1) US7696092B2 (en)
EP (1) EP1449247A2 (en)
JP (1) JP4463555B2 (en)
KR (1) KR100966359B1 (en)
CN (1) CN1320630C (en)
AU (1) AU2002335805A1 (en)
WO (1) WO2003046979A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696092B2 (en) 2001-11-26 2010-04-13 Globalfoundries Inc. Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
US7989338B2 (en) * 2005-06-15 2011-08-02 Globalfoundries Singapore Pte. Ltd. Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
JP5234306B2 (en) * 2006-10-18 2013-07-10 三菱マテリアル株式会社 Wiring and electrode for flat panel display using TFT transistor with less surface defects and good surface condition, and sputtering target for forming them
US8575019B2 (en) * 2010-09-30 2013-11-05 Institute of Microelectronics, Chinese Academy of Sciences Metal interconnection structure and method for forming metal interlayer via and metal interconnection line
CN104137191A (en) * 2011-12-28 2014-11-05 矢崎总业株式会社 Ultrafine conductor material, ultrafine conductor, method for preparing ultrafine conductor, and ultrafine electrical wire
JP5987443B2 (en) * 2012-04-19 2016-09-07 富士通株式会社 Operation motion detection device, operation motion detection method, and program
KR102211741B1 (en) * 2014-07-21 2021-02-03 삼성전기주식회사 Printed circuit board and method of manufacturing the same
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
KR20220030455A (en) * 2020-09-01 2022-03-11 삼성전자주식회사 Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0567867A2 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Oxidation-resistant compound of Cu3Si and fabrication thereof
US6090710A (en) * 1995-06-27 2000-07-18 International Business Machines Corporation Method of making copper alloys for chip and package interconnections
EP1039531A2 (en) * 1999-03-23 2000-09-27 Kabushiki Kaisha Toshiba Interconnection in semiconductor device and method of manufacturing the same
EP1094515A2 (en) * 1999-10-18 2001-04-25 Lucent Technologies Inc. Microstructure control of copper interconnects
US6242808B1 (en) * 1998-04-09 2001-06-05 Fujitsu Limited Semiconductor device with copper wiring and semiconductor device manufacturing method
US20010035237A1 (en) * 1999-11-24 2001-11-01 Shozo Nagano Conductive integrated circuit metal alloy interconnections, electroplating anodes; metal alloys for use as a conductive interconnection in an integrated circuit; and physical vapor deposition targets

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908275A (en) * 1987-03-04 1990-03-13 Nippon Mining Co., Ltd. Film carrier and method of manufacturing same
JPH0750697B2 (en) 1989-02-20 1995-05-31 株式会社東芝 Method for manufacturing semiconductor device
US5224520A (en) 1990-11-19 1993-07-06 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Weaving bar prevention in a jet loom
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
KR960010056B1 (en) 1992-12-10 1996-07-25 삼성전자 주식회사 Semiconductor device and menufacturing method thereof
US5654245A (en) 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
JP3296709B2 (en) * 1995-07-10 2002-07-02 古河電気工業株式会社 Thin copper alloy for electronic equipment and method for producing the same
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
KR100243286B1 (en) 1997-03-05 2000-03-02 윤종용 Method for manufacturing a semiconductor device
US5770517A (en) 1997-03-21 1998-06-23 Advanced Micro Devices, Inc. Semiconductor fabrication employing copper plug formation within a contact area
US5969422A (en) 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US5821168A (en) 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US5882738A (en) 1997-12-19 1999-03-16 Advanced Micro Devices, Inc. Apparatus and method to improve electromigration performance by use of amorphous barrier layer
US6344413B1 (en) 1997-12-22 2002-02-05 Motorola Inc. Method for forming a semiconductor device
US6482734B1 (en) 1998-01-20 2002-11-19 Lg Semicon Co., Ltd. Diffusion barrier layer for semiconductor device and fabrication method thereof
KR100404649B1 (en) 1998-02-23 2003-11-10 가부시끼가이샤 히다치 세이사꾸쇼 Semiconductor device and fabrication method thereof
US6156638A (en) 1998-04-10 2000-12-05 Micron Technology, Inc. Integrated circuitry and method of restricting diffusion from one material to another
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6015749A (en) 1998-05-04 2000-01-18 Taiwan Semiconductor Manufacturing Company Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure
US6461675B2 (en) 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate
US6380083B1 (en) * 1998-08-28 2002-04-30 Agere Systems Guardian Corp. Process for semiconductor device fabrication having copper interconnects
US6144096A (en) 1998-10-05 2000-11-07 Advanced Micro Devices, Inc. Low resistivity semiconductor barrier layers and manufacturing method therefor
US6117770A (en) 1998-10-08 2000-09-12 Advanced Micro Devices, Inc. Method for implanting semiconductor conductive layers
KR100385042B1 (en) 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 Method for forming electromigration-resistant structures by doping
US6294836B1 (en) 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6096648A (en) 1999-01-26 2000-08-01 Amd Copper/low dielectric interconnect formation with reduced electromigration
KR100309642B1 (en) 1999-01-29 2001-09-26 김영환 A method of forming contacts in semiconductor device
US6521532B1 (en) 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6159845A (en) * 1999-09-11 2000-12-12 United Microelectronics Corp. Method for manufacturing dielectric layer
CN1155057C (en) * 1999-12-02 2004-06-23 国际商业机器公司 Method for forming deelectric transferred structure by doping
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6376370B1 (en) 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US6225221B1 (en) 2000-02-10 2001-05-01 Chartered Semiconductor Manufacturing Ltd. Method to deposit a copper seed layer for dual damascene interconnects
US6627995B2 (en) 2000-03-03 2003-09-30 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6410383B1 (en) 2000-03-16 2002-06-25 Sharp Laboratories Of America, Inc. Method of forming conducting diffusion barriers
US6426289B1 (en) 2000-03-24 2002-07-30 Micron Technology, Inc. Method of fabricating a barrier layer associated with a conductor layer in damascene structures
US6423633B1 (en) 2000-04-10 2002-07-23 Vanguard International Semiconductor Corp. Method for manufacturing diffusion barrier layer
TW508658B (en) * 2000-05-15 2002-11-01 Asm Microchemistry Oy Process for producing integrated circuits
US6749699B2 (en) * 2000-08-09 2004-06-15 Olin Corporation Silver containing copper alloy
JP2002075994A (en) 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US6294463B1 (en) 2000-09-13 2001-09-25 Vanguard International Semiconductor Corp. Method for manufacturing diffusion barrier layer
US6977224B2 (en) 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
US6465867B1 (en) 2001-02-21 2002-10-15 Advanced Micro Devices, Inc. Amorphous and gradated barrier layer for integrated circuit interconnects
US6500749B1 (en) 2001-03-19 2002-12-31 Taiwan Semiconductor Manufacturing Company Method to improve copper via electromigration (EM) resistance
US6534865B1 (en) 2001-06-12 2003-03-18 Advanced Micro Devices, Inc. Method of enhanced fill of vias and trenches
US7696092B2 (en) 2001-11-26 2010-04-13 Globalfoundries Inc. Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0567867A2 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Oxidation-resistant compound of Cu3Si and fabrication thereof
US6090710A (en) * 1995-06-27 2000-07-18 International Business Machines Corporation Method of making copper alloys for chip and package interconnections
US6242808B1 (en) * 1998-04-09 2001-06-05 Fujitsu Limited Semiconductor device with copper wiring and semiconductor device manufacturing method
EP1039531A2 (en) * 1999-03-23 2000-09-27 Kabushiki Kaisha Toshiba Interconnection in semiconductor device and method of manufacturing the same
EP1094515A2 (en) * 1999-10-18 2001-04-25 Lucent Technologies Inc. Microstructure control of copper interconnects
US20010035237A1 (en) * 1999-11-24 2001-11-01 Shozo Nagano Conductive integrated circuit metal alloy interconnections, electroplating anodes; metal alloys for use as a conductive interconnection in an integrated circuit; and physical vapor deposition targets

Also Published As

Publication number Publication date
JP2005510875A (en) 2005-04-21
AU2002335805A8 (en) 2003-06-10
JP4463555B2 (en) 2010-05-19
US7696092B2 (en) 2010-04-13
AU2002335805A1 (en) 2003-06-10
KR20040064287A (en) 2004-07-16
CN1592963A (en) 2005-03-09
KR100966359B1 (en) 2010-06-28
CN1320630C (en) 2007-06-06
WO2003046979A2 (en) 2003-06-05
US20040005773A1 (en) 2004-01-08
EP1449247A2 (en) 2004-08-25

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