WO2003049184A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2003049184A1
WO2003049184A1 PCT/JP2001/010722 JP0110722W WO03049184A1 WO 2003049184 A1 WO2003049184 A1 WO 2003049184A1 JP 0110722 W JP0110722 W JP 0110722W WO 03049184 A1 WO03049184 A1 WO 03049184A1
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WO
WIPO (PCT)
Prior art keywords
terminal
semiconductor device
semiconductor chip
semiconductor
insulating film
Prior art date
Application number
PCT/JP2001/010722
Other languages
English (en)
French (fr)
Inventor
Hirohisa Matsuki
Yoshitaka Aiba
Mitsutaka Sato
Tadahiro Okamoto
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP01274912A priority Critical patent/EP1455392A4/en
Priority to CNB018238653A priority patent/CN100350607C/zh
Priority to PCT/JP2001/010722 priority patent/WO2003049184A1/ja
Priority to KR1020047008710A priority patent/KR100636259B1/ko
Priority to JP2003550280A priority patent/JP4182189B2/ja
Publication of WO2003049184A1 publication Critical patent/WO2003049184A1/ja
Priority to US10/860,657 priority patent/US7084513B2/en
Priority to US11/477,550 priority patent/US7759246B2/en

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a plurality of semiconductor chips and a method for manufacturing the same.
  • CSPs chip-size packages
  • the wafer level C SP has, for example, a structure as shown in FIG.
  • a wiring 102 is formed on a first semiconductor device chip 101, and a second semiconductor device chip 10 is formed on the wiring 102 via a solder pole 103. 4 is installed.
  • the second semiconductor device chip 104 is smaller than the first semiconductor device chip 101.
  • a pin-like terminal (via) 105 is connected to a peripheral region of the second semiconductor device chip 104 among the wirings 102 on the first semiconductor device chip 104. Have been. Further, on the upper surface of the first semiconductor device chip 101, a sealing resin 106 for sealing the second semiconductor device chip 104 is formed in such a degree that the upper end of the terminal 105 is exposed. It is formed to a thickness. A solder pole 107 is connected to the upper end of the terminal 105. However, since the terminal 105 shown in FIG. 1 is formed on the wiring 102 by the plating method, it takes time to form the terminal 105, and the throughput of CSP formation deteriorates.
  • An object of the present invention is to provide a semiconductor device in which a region where external terminals are formed in a stacked structure of a plurality of semiconductor chips is widened and external terminals can be easily formed.
  • the above-mentioned problem is solved by a first semiconductor chip having a first terminal on one surface, and a second semiconductor chip which is larger than the first semiconductor chip, is overlaid with the first semiconductor chip, and has a second terminal on one surface.
  • An insulating film formed on the second semiconductor chip to cover the first semiconductor chip; a plurality of holes formed in the insulating film; and a film formed on an inner peripheral surface and a bottom surface of the hole, and A conductive via electrically connected to at least one of the first terminal and the second terminal; a first wiring pattern formed on an upper surface of the insulating film; and a first wiring pattern formed on the first wiring pattern.
  • the problem is solved by a semiconductor device having external terminals.
  • an insulating film covering the first semiconductor chip is formed on the second semiconductor chip, and holes are formed in the insulating film.
  • the film-shaped via is formed in the hole, and the wiring pattern is formed on the insulating film.
  • the via could be formed in a short time, and the wiring pattern and the via could be formed of the same conductive film, thus forming the film.
  • the number of steps can be reduced.
  • Covering the via with an insulating film in the hole prevents corrosion of the via. Also, By covering the first wiring pattern on the edge film with another insulating film except for a portion connected to the external terminal, migration shot and corrosion of the first wiring pattern are prevented.
  • first wiring pattern is provided above the first and second semiconductor chips, external terminals can be formed at arbitrary positions, and a multi-pin structure can be accommodated.
  • FIG. 1 is a cross-sectional view showing a semiconductor device having a conventional structure
  • FIGS. 3A to 3C show the steps of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIGS. 4A and 4B show a manufacturing process (part 3) of the semiconductor device according to the first embodiment of the present invention
  • FIGS. 5A and 5B show a manufacturing process (part 4) of the semiconductor device according to the first embodiment of the present invention
  • FIG. 6A is a sectional view showing a semiconductor wafer constituting the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6B is a cross-sectional view showing a semiconductor device chip constituting the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a sectional view showing a semiconductor device according to the first embodiment of the present invention
  • FIG. 8 is a sectional view of a semiconductor device having a multilayer wiring structure according to the first embodiment of the present invention Fig.
  • 9 (a) and 9 (b) are cross-sectional views (1) showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention
  • FIGS. 11A to 11C show manufacturing steps of the semiconductor device according to the third embodiment of the present invention.
  • 12 (a) and 12 (b) are cross-sectional views (part 2) illustrating a process for manufacturing a semiconductor device according to the third embodiment of the present invention
  • 13 (a) and 13 (b) are cross-sectional views (part 3) illustrating a process for manufacturing a semiconductor device according to the third embodiment of the present invention
  • FIG. 14 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention
  • FIG. 15 is a cross-sectional view illustrating a first semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 16 is a sectional view showing a second semiconductor device according to the fourth embodiment of the present invention.
  • FIGS. 2 to 5 are cross-sectional views illustrating a process of forming a multichip package (MCP) according to the first embodiment of the present invention.
  • MCP multichip package
  • a semiconductor layer 1 in which a first semiconductor circuit (not shown) is formed in each of a plurality of device regions A is prepared.
  • the semiconductor wafer 1 has a protective insulating film 2 on its upper surface, and the protective insulating film 2 is electrically connected to the internal wiring (not shown) of the semiconductor device.
  • An opening 2a exposing the first terminal (conductive pad) 3 to be connected is formed.
  • the first terminal 3 is formed of aluminum, copper, or the like.
  • the semiconductor wafer 1 is, for example, a silicon wafer, and is cut for each first semiconductor circuit in a later step and divided into device regions A.
  • titanium is formed on the protective insulating film 2 and the first terminal 3.
  • a metal film having a two-layer structure of nickel is formed to a thickness of about 0.5, and the metal film is patterned by a photolithography method to form a first rewiring pattern 4.
  • the first rewiring pattern 4 is a conductive pattern drawn out from above the first terminal 3 onto the protective insulating film 2.
  • a first semiconductor device chip 5 on which a second semiconductor circuit (not shown) is formed is prepared.
  • the first semiconductor device chip 5 is, for example, a silicon chip smaller than the device area A of the semiconductor wafer 1, and has a protective insulating film 6 on its upper surface.
  • the protective insulating film 6 has an opening 6 a exposing a second terminal 7 connected to a wiring (not shown) inside the first semiconductor device chip 5.
  • a second rewiring pattern 8 extending from the second terminal 7 is formed.
  • the lower surface of the first semiconductor device chip 5 is bonded to the center of the semiconductor device region A of the semiconductor wafer 1 via a die bonding agent (adhesive) 9.
  • the resin insulating layer 10 such as epoxy or polyimide is set to be higher than the first semiconductor chip 5 by about 10 to 20 xm on the upper surface of the semiconductor wafer 1. Form. Thereby, the first semiconductor chip 5 is covered with the resin insulating film 10.
  • the resin insulating layer 10 is formed on the semiconductor wafer 1 by spin coating, printing, laminating, or the like. For example, when the lamination method is employed, it is necessary to sufficiently adjust the thickness of the resin insulating layer and the like so as to prevent air bubbles from entering on and around the first semiconductor device chip 5.
  • the back ground technology is used after forming the resin insulating layer 10 on the semiconductor wafer 1. It is desirable to flatten the upper surface of the resin insulating layer 10 by mechanical polishing, chemical mechanical polishing (CMP), polishing, or the like.
  • CMP chemical mechanical polishing
  • the upper surface of the resin insulating layer 10 is mechanically polished or chemically treated. Flatten by mechanical polishing.
  • via holes having a diameter of 80 to 100 m are formed on the first rewiring pattern 4 and the second rewiring pattern 8 of the resin insulating layer 10 respectively. (Through hole) 10a is formed.
  • a photosensitive resin material is selected as the resin film insulating layer 10
  • an exposure mask for forming a via hole is used. Te exposing the resin insulating layer 1 0, via holes 1 0 a is easily made form by developing further by using an inorganic alkaline solution such as sodium carbonate (NaC0 3).
  • the via hole 10a When the via hole 10a is formed by such exposure and development, the via hole 10a has a tapered shape in which the upper portion is widened, so that various processes in the via hole 10a to be described later become easy. In this case, since the first terminal 3 under the via hole 10a is covered with the first rewiring pattern 4, corrosion of the first terminal 3 by the inorganic alkali solution is prevented.
  • the via hole 10 a is irradiated by irradiating a predetermined position of the resin insulating layer 10 with high energy such as a laser. It is appropriate to form.
  • the via hole 10a is formed by a laser, the first terminal 3 and the protective insulating film 2 are covered with the first rewiring pattern 4 made of hard metal under the via hole 10a.
  • the first terminal 3 made of a relatively soft conductive material such as copper or the like and the protective insulating film 2 around the first terminal 3 can be removed or deteriorated by laser irradiation.
  • the via hole 10a may be formed by drilling.
  • the surface of the resin insulating layer 10 is activated with a diluting solvent, and then the upper surface of the resin insulating layer 10 and the inner peripheral surface and the bottom surface of the via hole 10a are activated.
  • a metal film 11, for example, a copper film is formed to a thickness of 0.5 to 1.5 mm by electroless plating.
  • the metal film 11 having such a thickness is formed in an extremely short time as compared with the case where the external terminals 105 shown in FIG. 1 are formed by plating. In this case, the metal film 11 is connected on the first rewiring pattern 4 within the via hole 10a.
  • the metal film may have a multilayer structure.
  • the metal film 11 it is also possible to adopt a method of forming a thin film by the electroplating method after forming the film once by the thinning method.
  • the resin insulating layer 10 is made of epoxy resin or polyimide, it is easy to grow the metal film 11 by an electroless plating method on the upper surface of the resin insulating layer 10 and the inner surface of the via hole 10a. It is.
  • the metal film 11 is patterned by photolithography to leave the metal film 11 in the via hole 10a as a via 11a.
  • the pattern of the metal film 11 on the upper surface of the resin insulating layer 10 is applied as a third rewiring pattern 11b.
  • the plurality of third rewiring patterns 11b on the resin insulating layer 10 are connected to the terminals 7 of the first semiconductor device chip 5 via the vias 11a and the second rewiring patterns 8, respectively. It is electrically connected to the terminal 3 of the semiconductor wafer 1 via the via 11 a and the first rewiring pattern 4.
  • the terminal 6 of the first semiconductor device chip 5 is electrically connected to the terminal 3 of the semiconductor wafer 1 via the via 11a and the third rewiring pattern 11b.
  • the via 11a is connected to the third rewiring 11b, but there may be a portion that is not connected.
  • a non-photosensitive epoxy resin is embedded in the opening 10a of the resin insulating layer 10 by using a squeegee or by a printing method, so that the embedded insulating layer is formed.
  • Form 1 2 Thereby, the via 11 a is covered with the buried insulating layer 12 in the opening 10 a.
  • an insulating resin cover film 13 made of a photosensitive epoxy resin or a photosensitive nopolak resin is applied to the resin insulating layer 10 and the third rewiring pattern 1. 1 b and the buried insulating layer 12.
  • the resin cover film 13 is applied on the resin insulating layer 10 by using a squeegee or by a printing method in a non-photosensitive atmosphere.
  • the resin cover film 13 prevents corrosion of the third rewiring pattern 11b, and prevents migration short-circuit of the third rewiring pattern 11b.
  • the resin cover film 13 is exposed and developed to perform patterning, thereby forming an opening 13a for exposing the contact portion of the third rewiring pattern 11b.
  • the external terminals 14 such as solder bumps are connected to the third rewiring pattern 11b through the openings 13a of the resin cover film 13. This place
  • the opening 13a has a tapered shape in which the upper portion expands, so that the positioning and connection of the pole-shaped external terminal 14 on the third rewiring pattern 11b are easy. is there.
  • the semiconductor wafer is divided into a plurality of second semiconductor device chips 1a by dicing the boundary between the semiconductor circuit regions A of the semiconductor wafer 1 shown in FIG. A plurality of such MCP type semiconductor devices are formed.
  • the side surface of the second semiconductor device chip 1a is exposed without being covered with the resin insulating layer 10.
  • the lower surface thereof Before dividing the semiconductor wafer 1, the lower surface thereof may be ground by a mechanical polishing method or a chemical mechanical polishing method.
  • the via hole 10a is formed around the first semiconductor chip 5, and
  • the conductive film formed on the inner peripheral surface and the bottom surface of the via hole 10a is used as the via 11a, and the conductive film is used as the rewiring pattern 11b on the upper surface of the resin insulating layer 10. I have.
  • the via 11a to be formed in the via hole 10a is formed in a shorter time than the conventional structure in which the via hole is completely buried because the via 11a is formed by the process of forming the metal film 11. can do.
  • the external terminals 14 are also formed above the first semiconductor device chip 5, so that the number of the external terminals 14 can be increased as compared with the conventional case, and the pitch of the external terminals 14 is reduced. You.
  • both the via 11a and the rewiring pattern 11b are formed from the same metal film 11, the throughput is improved as compared with the case where each is formed separately.
  • the first semiconductor device chip 5 is bonded onto the semiconductor wafer 1, and thereafter, the resin insulating layer 10, the via 11 a, and the third rewiring pattern 11 1 b,
  • the semiconductor wafer 1 is divided after forming the protective cover film 13 and the external terminals 14.
  • the second semiconductor chip 5 is bonded on the second semiconductor chip 1a, and then the resin insulating layer 10 Via 11a, third rewiring pattern 11b, protective cover film 13 and external terminal 14 may be formed, which also forms a semiconductor device having the same structure as shown in FIG. .
  • the side surface of the second semiconductor device chip 1a is covered with the resin film 10.
  • the wiring structure layer having the resin insulating layer 10, the via 11a, and the rewiring pattern 11b may have a multilayer structure of two or more layers.
  • a protective cover film 13 and external terminals 14 are formed on the insulating layer 10.
  • the upper and lower rewiring patterns 11b are arranged so as to intersect with each other in correspondence with high-speed signal processing.
  • Such a multilayer wiring structure may be adopted in the embodiments described below.
  • the buried insulating layer 12 is formed in the via hole 10a, and then the resin layer 10 is formed on the resin insulating layer 10.
  • the bar film 13 is formed.
  • the buried insulating layer 12 and the resin cover film 13 may be formed simultaneously.
  • a photosensitive resin film 15 for example, an epoxy resin is simultaneously applied to the inside of the via hole 10 a and the resin insulating layer 10, and then the resin film 15 is exposed to light.
  • An opening 15a for exposing the contact portion of the third rewiring pattern 1b is formed by development.
  • the epoxy resin in the via hole 10a is used as a buried insulating layer
  • the epoxy resin on the resin insulating layer 10 is used as a resin cover film
  • the buried insulating film layer and the resin cover film are used. Can be formed at the same time, and the number of insulating film forming steps is reduced as compared with the first embodiment.
  • nickel phosphorus (NiP), nickel, gold, or the like is selectively placed on the terminal 3 in the opening 2a of the protective insulating film 2 on the semiconductor wafer 1.
  • the covered conductive layer 16 is formed to a thickness of 3 to 5 / m by an electroless plating method.
  • the first semiconductor device chip 5 is mounted on the semiconductor wafer 1 by the same method as in the first embodiment.
  • the first semiconductor device chip 5 has a structure in which a NiP-coated conductive film 17 is formed on the second terminal 7 of the protective insulating film 6 on the upper surface thereof, instead of a rewiring pattern.
  • a resin insulating layer 10 is formed on the semiconductor wafer 1 so as to cover the first semiconductor device chip 5.
  • the same method as in the first embodiment is employed.
  • a via hole 10a is formed thereon.
  • the via hole 10a employs the same method as that shown in the first embodiment. That is, when the resin insulating layer 10 is made of a photosensitive material, it is formed by exposure and development, or when the resin insulating layer 10 is made of a non-photosensitive material, it is formed by laser irradiation. In this case, the terminals 3 and 7 made of copper or aluminum below the via hole 10a are protected by the coated conductive layers 16 and 17, respectively, and can be directly exposed to the developing solution or the laser. Therefore, deterioration due to development and laser is prevented.
  • the via hole 10a may be formed by drilling.
  • FIG. 13A Thereafter, as shown in FIG. 13A, through the same steps as in the first embodiment, vias 11a are formed in the via holes 10a, and the rewiring patterns 11 are formed on the resin insulating layer 10. b is formed respectively. Further, as shown in FIG. 13 (b), a buried insulating film 12, a cover insulating film 13, and an external terminal 14 are formed. Note that the buried insulating film 1 2 and the cover insulating film 1 3 May be simultaneously formed from the same resin film 15 as shown in the second embodiment.
  • the semiconductor wafer 1 is divided into a plurality of second semiconductor device chips la for each device region A, a semiconductor device as shown in FIG. 14 is formed.
  • the side surface of the second semiconductor device chip 1a is exposed without being covered with the resin insulating layer 10.
  • the supply of the inorganic alkali used for forming the via hole 10a to the resin insulating layer 10 to the terminals 3 and 7 can be prevented by the covering conductive layers 16 and 17.
  • irradiation of the terminals 3 and 7 of the laser used for forming the via hole 10a can be prevented by the coating conductive layers 16 and 17, and the deterioration of the terminals 3 and 7 is prevented.
  • a rewiring pattern may be formed on one of the first semiconductor chip 5 and the semiconductor wafer 1, but the terminals 3 and 7 that are not covered by the rewiring pattern are covered with conductive wires 16 and 17. Need to cover with 1 7
  • the first semiconductor device chip 5 shown in FIG. 6 (b) is connected to the terminal 3 of the semiconductor wafer 1 via a wire or a solder pole without passing through the rewiring pattern 11b on the upper surface of the resin insulating layer 10. The connection may be made.
  • a nickel-phosphorous-coated conductive layer 17 is formed on the terminal 7 of the first semiconductor device chip 5 without forming a rewiring pattern, and the coated conductive layer 17 is A structure in which the rewiring pattern 4 on the semiconductor wafer (the second semiconductor device chip 1 a) is connected by gold (conductive) wires 21 by wire bonding may be adopted. In this case, no via hole 10 a is formed in the resin insulating layer 10 on the first semiconductor device chip 5.
  • solder bumps (external terminals) 22 are connected to the terminals 7 of the first semiconductor device chip 5, and the solder bumps 22 are connected to the semiconductor wafer 1 (the second semiconductor device chip 5). It may be connected on the rewiring pattern 4 above 1 a ). Also in this case, no via hole 10 a is formed in the resin insulating layer 10 on the first semiconductor device chip 5. Although no via hole 10a is formed above the first semiconductor device chip 5 in the resin insulating layer 10 shown in FIGS. 15 and 16, a rewiring pattern 1 is formed on the resin insulating layer 10. 1b is formed, and the external terminal 14 is bonded thereon.
  • the area for forming the external terminals 14 on the resin insulating layer 10 is wider than before, so that the number of the external terminals 14 can be increased as compared with the conventional case, and the pitch of the external terminals 14 can be reduced. Be relaxed.
  • an insulating film covering the first semiconductor chip is formed on the second semiconductor chip. Since a hole was formed in the insulating film, a film-like via was formed in the hole, and a wiring pattern was formed on the insulating film, the via could be formed in a short time, and the wiring pattern and the via were the same. It can be formed of a conductive film, so that the number of steps for forming the film can be reduced.
  • the wiring pattern on the insulating film is drawn out onto the first semiconductor chip and external terminals are formed thereon, it is possible to suppress the narrowing of a plurality of external terminals on the insulating film, and to reduce the number of external terminals. Can be increased.
  • the vias in the holes by covering the vias in the holes with an insulating film, corrosion of the vias can be prevented.
  • the first wiring pattern on the insulating film should be covered with another insulating film except for the part connected to the external terminals. Thereby, migration short-circuit and corrosion of the first wiring pattern can be prevented.

Description

明 細 書 半導体装置及びその製造方法 技術分野
本発明は、 半導体装置及びその製造方法に関し、 より詳しくは、 複数の半導 体チップを有する半導体装置及びその製造方法に関する。 背景技術
次世代の携帯電話ゃモパイル P Cを含む携帯情報端末機については、 小型 ·軽 量 ·薄型化の向上がキーポイントとなっている。 従って、 今後高い成長が予想さ れる携帯情報端末機の技術競争力を高めるためには、 さらなる小型 ·軽量 ·薄型 化を実現できる高密度実装技術の開発が重要である。
高密度実装技術としてはフリップ ·チップ実装、 マルチ ·チップ ·モジュール や積層基板など種々の技術が存在する。 さらに、 パッケージに複数の機能を盛り 込みたいというニーズから半導体チップを積層化した構造のチップ ·サイズ ·パ ッケージ （C S P ) の技術開発が進み、 さらに、 インターポーザ基板を用いない ウェハレベル C S Pが開発されている。
ウェハレベル C S Pは例えば図 1に示すような構造を有している。
図 1において、 第 1の半導体デバイスチップ 1 0 1の上には配線 1 0 2が形成 され、 その配線 1 0 2の上には半田ポール 1 0 3を介して第 2の半導体デバイス チップ 1 0 4が取り付けられている。 その第 2の半導体デバイスチップ 1 0 4は 、 第 1の半導体デバイスチップ 1 0 1よりも小さい。
また、 第 1の半導体デバイスチップ 1 0 4上の配線 1 0 2のうち、 第 2の半導 体デバイスチップ 1 0 4の周辺領域には、 ピン状の端子 （ビア） 1 0 5が接続さ れている。 さらに、 第 1の半導体デバイスチップ 1 0 1の上面では、 第 2の半導 体デバイスチップを 1 0 4封止するための封止樹脂 1 0 6が端子 1 0 5の上端が 露出する程度の厚さに形成されている。 その端子 1 0 5の上端には半田ポール 1 0 7が接続されている。 しかし、 図 1に示した端子 1 0 5は配線 1 0 2の上にメツキ法によって形成さ れるので、 端子 1 0 5の形成に時間がかかり、 C S P形成のスループットが悪く なる。
また、 端子 1 0 5の形成領域は第 2の半導体デバイスチップ 1 0 4の周辺に限 定されるので、 端子 1 0 5の数の増加は望めない。 発明の開示
本発明の目的は、 複数の半導体チップの積層構造において外部端子の形成領域 を広げるとともに、 外部端子を容易に形成できる半導体装置を提供することにあ る。
上記した課題は、 一面に第 1端子を有する第 1半導体チップと、 前記第 1半導 体チップより大きく、 前記第 1半導体チップが重ねられ且つ一面に第 2端子を有 する第 2半導体チップと、 前記第 2半導体チップ上に形成されて前記第 1半導体 チップを覆う絶縁膜と、 前記絶縁膜に形成される複数のホールと、 前記ホールの 内周面及び底面に膜状に形成され且つ前記第 1端子と前記第 2端子の少なくとも 一方に電気的に接続される導電性のビアと、 前記絶縁膜の上面上に形成された第 1配線パターンと、 前記第 1配線パターンの上に形成された外部端子とを有する 半導体装置によつて解決される。
本発明によれば、 大きさの異なる第 1及び第 2半導体チップを積層した構造の 半導体装置において、 第 2半導体チップの上に第 1半導体チップを覆う絶縁膜を 形成し、 絶縁膜にホールを形成し、 ホールの中に膜状のビアを形成し、 絶縁膜上 に配線パターンを形成している。
従って、 ホールを完全に充填せずに膜状のビアを形成したので、 ビアを短時間 で形成することができ、 しかも配線パターンとビアを同じ導電膜によって構成す ることができて膜の形成工程を減らすことができる。
また、 絶縁膜上の配線パターンを第 1半導体チップの上方に引き出してその上 に外部端子を形成すると、 絶縁膜上での複数の外部端子の狭ピッチ化を抑制でき 、 しかも外部端子の数を増やすことができる。
ホール内でビアを絶縁膜で覆うことによりビアの腐食が防止される。 また、 絶 縁膜上の第 1配線パターンのうち外部端子と接続する部分を除いて別の絶縁膜で 覆うことにより、 第 1配線パターンのマイグレーションショ一卜や腐食は防止さ れる。
ところで、 第 1半導体チップの第 1端子が形成される回路面を、 第 2半導体チ ップの第 2端子が形成される回路面に対してフェースアップ、 フェースダウンで 配置するにかかわらず、 同じ技術で積層ウェハレベルパッケージを作成でき、 し かも、 フエ一スアップ、 フェースダウンの使い分けができて、 種々の機能を持つ た半導体デバイスの重ね合わせが可能であるために有用である。
また、 第 1及び第 2半導体チップの上方に第 1配線パターンがあるために、 外 部端子を自由な位置に形成でき、 多ピン構造に対応できる。
さらに、 上記したような配線パターンとビアを有する絶縁膜を多層化すること や、 上記した構造を重ねることにより半導体チップの複数搭載が可能になる。 図面の簡単な説明
図 1は、 従来構造の半導体装置を示す断面図であり ；
図 2 (a) 〜（c) .は、 本発明の第 1実施形態に係る半導体装置の製造工程 （その
1 ) であり ；
図 3 (a) 〜（c) は、 本発明の第 1実施形態に係る半導体装置の製造工程 （その
2 ) であり ；
図 4 (a) , (b) は、 本発明の第 1実施形態に係る半導体装置の製造工程 （その 3 ) であり ；
図 5 (a)，（b) は、 本発明の第 1実施形態に係る半導体装置の製造工程 （その 4 ) であり ；
図 6 (a) は、 本発明の第 1実施形態に係る半導体装置を構成する半導体ウェハ を示す断面図であり ；
図 6 (b) は、 本発明の第 1実施形態に係る半導体装置を構成する半導体デバイ スチップを示す断面図であり ；
図 7は、 本発明の第 1実施形態に係る半導体装置を示す断面図であり ； 図 8は、 本発明の第 1実施形態に係る多層配線構造を有する半導体装置の断面 図であり ；
図 9 (a), (b) は、 本発明の第 2実施形態に係る半導体装置の製造工程を示す断 面図 （その 1) であり ；
図 10は、 本発明の第 2実施形態に係る半導体装置を示す断面図であり ； 図 1 1 (a) 〜（c) は、 本発明の第 3実施形態に係る半導体装置の製造工程を示 す断面図 （その 1) であり ；
図 12 (a), (b) は、 本発明の第 3実施形態に係る半導体装置の製造工程を示す 断面図 （その 2) であり ；
図 13 (a)，（b) は、 本発明の第 3実施形態に係る半導体装置の製造工程を示す 断面図 （その 3) であり ；
図 14は、 本発明の第 3実施形態に係る半導体装置を示す断面図であり ； 図 1 5は、 本発明の第 4実施形態に係る第 1半導体装置を示す断面図であり ； そして
図 16は、 本発明の第 4実施形態に係る第 2半導体装置を示す断面図である。 発明の実施をするための最良の形態
以下に本発明の実施形態を図面に基づいて説明する。
(第 1の実施の形態）
図 2〜図 5は、 本発明の第 1実施形態に係るマルチップパッケージ （MCP (m ulti chip package)) の形成工程を示す断面図である。
まず、 図 2 (a) に示すように複数のデバイス領域 Aにそれぞれ第 1の半導体回 路 （不図示） が形成された半導体ゥェ八 1を用意する。 半導体ウェハ 1は、 図 6 (a) の部分拡大図に示すように、 その上面に保護絶縁膜 2を有し、 その保護絶縁 膜 2には半導体デバイスの内部配線 （不図示） に電気的に接続される第 1の端子 (導電性パッド） 3を露出する開口 2 aが形成されている。 第 1の端子 3は、 ァ ルミ二ゥム、 銅などで形成されている。
なお、 半導体ウェハ 1は、 例えばシリコンウェハであって、 後の工程で第 1の 半導体回路毎に切断されてデバイス領域 A単位に分割される。
続いて、 図 2 (b) に示すように、 保護絶縁膜 2と第 1の端子 3の上にチタンと ニッケルの二層構造の金属膜を 0 . 5 程度の厚さに形成し、 さらに、 その金 属膜をフォトリソグラフィ一法によりパターニングして第 1の再配線パターン 4 を形成する。 この第 1の再配線パターン 4は、 第 1の端子 3の上から保護絶縁膜 2上に引き出される導電パターンである。
その後に、 図 6 (b) に示すように、 第 2の半導体回路 （不図示） が形成された 第 1の半導体デバイスチップ 5を用意する。 第 1の半導体デバイスチップ 5は、 半導体ウェハ 1のデバイス領域 Aよりも小さい例えばシリコンチップであり、 そ の上面に保護絶縁膜 6を有している。 保護絶縁膜 6には、 第 1の半導体デバイス チップ 5内部の配線 （不図示） に接続される第 2の端子 7を露出する開口 6 aが 形成されている。 また、 その保護絶縁膜 6上には第 2の端子 7上から引き出され る第 2の再配線パターン 8が形成されている。
そして、 図 2 (c) に示すように、 第 1の半導体デバイスチップ 5の下面をダイ ボンディング剤 （接着剤） 9を介して半導体ウェハ 1の半導体デバイス領域 Aの 中央にボンディングする。
次に、 図 3 (a) に示すように、 エポキシ、 ポリイミドのような樹脂絶縁層 1 0 を半導体ウェハ 1上面上で第 1の半導体チップ 5よりも 1 0〜2 0 x m程度高く なるように形成する。 これにより、 第 1の半導体チップ 5は樹脂絶縁膜 1 0によ り覆われる。
樹脂絶縁層 1 0は、 半導体ウェハ 1の上にスピン塗布、 印刷、 ラミネート法な どにより形成される。 例えば、 ラミネート法を採用する場合には樹脂絶縁層の膜 厚などを十分調整し、 第 1の半導体デバイスチップ 5上とその周囲に気泡が入ら ないように工夫する必要がある。
また、 樹脂絶縁層 1 0の材料の特性により樹脂絶縁層 1 0表面の平坦化が困難 な場合には、 樹脂絶縁層 1 0を半導体ウェハ 1上に形成した後に、 バックグライ ンド技術を用いた機械的な研磨、 化学機械研磨 （C M P ) 又はポリッシングなど によって樹脂絶縁層 1 0の上面を平坦化することが望ましい。 例えばエポキシレ ジンやポリイミドからなる樹脂絶縁層 1 0を半導体ウェハ 1上に例えば 1 2 0〜 1 5 0 mの厚さに形成した後に、 樹脂絶縁層 1 0の上面を機械的研磨法又は化 学機械研磨法により平坦化する。 次に、 図 3 (b) に示すように、 樹脂絶縁層 1 0のうち、 第 1の再配線パターン 4と第 2の再配線パターン 8の上にそれぞれ直径 8 0〜 1 0 0 mのビアホール (貫通孔） 1 0 aを形成する。
樹脂膜絶縁層 1 0として感光性樹脂材料を選択する場合には、 半導体ウェハ 1 上の樹脂絶縁層 1 0の形成を非感光光の環境下で行った後に、 ビアホール形成用 の露光マスクを用いて樹脂絶縁層 1 0を露光し、 さらに炭酸ナトリウム（NaC03) などの無機アルカリ液を用いて現像することによりビアホール 1 0 aが容易に形 成される。
このような露光、 現像によってビアホール 1 0 aを形成すると、 ビアホール 1 0 aは上部が広くなるようなテーパ形状になるので、 後述するビアホール 1 0 a 内での各種の処理が容易になる。 この場合、 ビアホール 1 0 aの下の第 1の端子 3が第 1の再配線パターン 4に覆われているので、 第 1の端子 3の無機アルカリ 液による腐食が防止される。
一方、 樹脂絶縁層 1 0の構成材料として非感光性材料を選択する場合には、 レ —ザ等の高エネルギーを樹脂絶縁層 1 0の所定位置に照射することによりビアホ —ル 1 0 aを形成することが適当である。 ビアホール 1 0 aをレーザにより形成 する場合には、 ビアホール 1 0 aの下では第 1の端子 3や保護絶縁膜 2が硬質金 属の第 1の再配線パターン 4に覆われているので、 アルミニウム、 銅などの比較 的軟質の導電材ょりなる第 1の端子 3やその周辺の保護絶縁膜 2がレーザ照射に よって除去されたり劣化するおそれはなくなる。
なお、 ビアホール 1 0 aはドリリングで形成されることもある。
次に、 図 3 (c) に示すように、 樹脂絶縁層 1 0の表面を希釈溶剤により活性化 し、 その後に樹脂絶縁層 1 0の上面とビアホール 1 0 aの内周面及び底面の上に 金属膜 1 1、 例えば銅膜を無電解メツキによって 0 . 5〜 1 . Ο ΓΙΙの厚さに形 成する。 その程度の厚さの金属膜 1 1は、 図 1に示した外部端子 1 0 5をメツキ により形成する場合に比べて極めて短い時間で形成される。 この場合、 金属膜 1 1は、 ビアホ一ル 1 0 a内で第 1の再配線パターン 4の上に接続される。 なお、 金属膜は、 多層構造であってもよい。
なお、 金属膜 1 1を 3〜 5 程度の厚さに形成したい場合には、 無電解メッ キ法によって一旦薄く形成した後に、 電解メツキ法によって厚く形成する方法を 採用してもよい。 また、 樹脂絶縁層 1 0がエポキシレジンやポリイミドから構成 される場合には、 樹脂絶縁層 1 0の上面とビアホール 1 0 a内面の上での無電解 メツキ法による金属膜 1 1の成長は容易である。
この後に、 図 4 (a) に示すように、 金属膜 1 1をフォトリソグラフィ一法によ りパタ一ニングすることにより、 ビアホール 1 0 a内の金属膜 1 1をビア 1 1 a として残すとともに、 樹脂絶縁層 1 0の上面の金属膜 1 1のパターンを第 3の再 配線パターン 1 1 bとして適用する。 これにより、 樹脂絶縁層 1 0上の複数の第 3の再配線パターン 1 1 bは、 それぞれビア 1 1 a及び第 2の再配線パターン 8 を介して第 1の半導体デバイスチップ 5の端子 7に電気的に接続され、 且つ、 ビ ァ 1 1 a及び第 1の再配線パターン 4を介して半導体ウェハ 1の端子 3に電気的 に接続される。 また、 第 1の半導体デバイスチップ 5の端子 6は、 ビア 1 1 aと 第 3の再配線パターン 1 1 bを介して半導体ウェハ 1の端子 3に電気的に接続さ れている。 なお、 ビア 1 1 aは第 3の再配線 1 1 bに繋がっているが、 繋がって いない部分もあってもよい。
次に、 図 4 (b) に示すように、 非感光性のエポキシ樹脂を樹脂絶縁層 1 0の開 口部 1 0 a内にスキージを用いたり或いは印刷法により埋め込むことにより、 埋 込絶縁層 1 2を形成する。 これにより、 開口部 1 0 a内でビア 1 1 aは埋込絶縁 層 1 2により覆われる。
続いて、 図 5 (a) に示すように、 感光性エポキシ樹脂又は感光性ノポラック樹 脂などからなる絶縁性の樹脂カバー膜 1 3を、 樹脂絶縁層 1 0、 第 3の再配線パ ターン 1 1 b及び埋込絶縁層 1 2の上に形成する。 樹脂カバー膜 1 3は、 スキー ジを用いたり或いは印刷法により非感光光の雰囲気中で樹脂絶縁層 1 0上に塗布 される。 樹脂カバー膜 1 3は、 第 3の再配線パターン 1 1 bの腐食を防止し、 第 3の再配線パターン 1 1 bのマイグレーションショートを防止する。
さらに、 樹脂カバ一膜 1 3を露光、 現像することによりバタ一ニングして、 第 3の再配線パターン 1 1 bのコンタクト部を露出する開口 1 3 aを形成する。 その後に、 図 5 (b) に示すように、 半田バンプなどの外部端子 1 4を樹脂カバ 一膜 1 3の開口 1 3 aを通して第 3の再配線パターン 1 1 bに接続する。 この場 合、 外部端子 1 4は、 樹脂カバー膜 1 3の開口 1 3 aの中に形成されるので、 位 置ズレが防止され、 或いは位置決めが容易となる。 この場合、 露光、 現像によれ ば、 開口 1 3 aは、 上が広がるテーパー形状になるので、 第 3の再配線パターン 1 1 b上のポール状の外部端子 1 4の位置決めと接続は容易である。
この後に、 図 5 (b) に示した半導体ウェハ 1の半導体回路領域 A同士の境界を ダイシングすることにより半導体ウェハを複数の第 2の半導体デバイスチップ 1 aに分割することにより、 図 7に示すような M C P型の半導体装置が複数形成さ れる。 この場合、 第 2の半導体デバイスチップ 1 aの側面は樹脂絶縁層 1 0に覆 われずに露出する。
なお、 半導体ウェハ 1を分割する前に、 その下面を機械研磨法又は化学機械研 磨法により研削してもよい。
以上のような半導体装置によれば、 第 2の半導体デバイスチップ 1 aの上面に 形成された樹脂絶縁層 1 0のうち、 第 1の半導体チップ 5の周囲にビアホール 1 0 aを形成するととも、 そのビアホール 1 0 aの内周面及び底面に形成された導 電膜をビア 1 1 aとして用いるとともに、 樹脂絶縁層 1 0の上面にその導電膜を 再配線パターン 1 1 bとして用いるようにしている。
従って、 ビアホール 1 0 a内に形成しょうとするビア 1 1 aの形成が、 金属膜 1 1の形成という工程によっているので、 ビアホールを完全に埋め込むような従 来の構造に比べて短時間で形成することができる。
また、 ビア 1 1 aを構成する金属膜 1 1のうち樹脂絶縁層 1 0の上面上に形成 された部分は、 パターニングされて再配線パターン 1 l bとして使用されている 。 このため、 第 1の半導体デバイスチップ 5の上方にも外部端子 1 4が形成され 、 外部端子 1 4の数を従来よりも増やすことができ、 しかも、 外部端子 1 4の狭 ピッチ化が緩和される。
さらに、 ビア 1 1 aと再配線パターン 1 1 bを双方とも同じ金属膜 1 1から形 成しているので、 それぞれを別々に形成する場合に比べてスループットが改善さ れる。
なお、 上記した例では、 半導体ウェハ 1の上に第 1の半導体デバイスチップ 5 を接着し、 その後に、 樹脂絶縁層 1 0、 ビア 1 1 a、 第 3の再配線パターン 1 1 b、 保護カバー膜 1 3、 外部端子 1 4を形成した後に半導体ウェハ 1を分割して いる。 しかし、 半導体ウェハ 1を複数の第 2の半導体デバイスチップ 1 aに分割 した後に、 第 2の半導体チップ 1 aの上に第 2の半導体チップ 5を接着し、 その 後に、 樹脂絶縁層 1 0、 ビア 1 1 a、 第 3の再配線パターン 1 1 b、 保護カバ一 膜 1 3、 外部端子 1 4を形成してもよく、 こによっても図 7に示すと同じ構造の 半導体装置が形成される。 この場合には、 第 2の半導体デバイスチップ 1 aの側 面は樹脂膜 1 0で覆われる。
また、 図 8に示すように、 樹脂絶縁層 1 0とビア 1 1 aと再配線パターン 1 1 bを有する配線構造層を 2層以上の多層構造としてもよく、 この場合には、 最上 の樹脂絶縁層 1 0の上に保護カバー膜 1 3と外部端子 1 4が形成される。 この場 合、 上下の再配線パターン 1 1 b同士は、 高速信号処理に対応させて互いに交差 するように配置される。 このような多層配線構造は、 以下に示す実施形態におい て採用してもよい。
(第 2の実施の形態）
第 1実施形態では、 ビア 1 1 aと再配線パターン 1 1 bを形成した後に、 ビア ホール 1 0 a内に埋込絶縁層 1 2を形成し、 その後に樹脂絶縁層 1 0上に樹脂力 バー膜 1 3を形成している。 しかし、 埋込絶縁層 1 2と樹脂カバ一膜 1 3を同時 に形成してもよい。
例えば、 図 9 (a) に示すように、 感光性の樹脂膜 1 5、 例えばエポキシ樹脂を ビアホール 1 0 a内と樹脂絶縁層 1 0上に同時に塗布した後に、 樹脂膜 1 5を露 光、 現像して第 3の再配線パターン 1 bのコンタクト部を露出する開口 1 5 a を形成する。
その後に、 図 9 (b) に示すように、 外部端子 1 4を樹脂膜 1 5の開口 1 5 aを 通して再配線パターン 1 1 bに接合する。
これによれば、 ビアホール 1 0 a内のエポキシ樹脂は埋込絶縁層として使用さ れ、 樹脂絶縁層 1 0上のエポキシ樹脂は樹脂カバー膜として使用され、 埋込絶縁 膜層と樹脂カバ一膜を同時に形成でき、 第 1実施形態に比べて絶縁膜形成工程が 減ることになる。
その後に、 半導体回路領域 A同士の境界を切断することにより、 図 1 0に示す ような半導体装置が形成される。 この場合、 第 2の半導体デバイスチップ 1 aの 側面は樹脂絶縁層 1 0に覆われずに露出する。
(第 3の実施の形態）
第 1実施形態に示した半導体ウェハ 1の上に第 1の再配線パターン 3を形成し ない場合には、 以下のような工程を採用する。
まず、 図 l l (a)，（b) に示すように、 半導体ウェハ 1の上の保護絶縁膜 2の開 口 2 a内の端子 3上に選択的にニッケルリン（NiP) 、 ニッケル、 金等よりなる被 覆導電層 1 6を無電解メツキ法により 3〜5 / mの厚さに形成する。
その後に、 図 1 1 (c) に示すように、 第 1実施形態と同様な方法により半導体 ウェハ 1上に第 1の半導体デバイスチップ 5を取り付ける。 第 1の半導体デバイ スチップ 5として、 その上面の保護絶縁膜 6の第 2の端子 7上に、 再配線パター ンではなく、 NiP の被覆導電膜 1 7が形成された構造のものが使用される。 続いて、 図 1 2 (a) に示すように、 第 1の半導体デバイスチップ 5を覆うよう に樹脂絶縁層 1 0を半導体ウェハ 1の上に形成する。 樹脂絶縁層 1 0の形成とそ の平坦化については、 第 1実施形態と同様な方法を採用する。
さらに、 図 1 2 (b) に示すように、 樹脂絶縁層 1 0のうち第 1の半導体デバイ スチップ 5上と半導体ウェハ 1のそれぞれの端子 3 , 7上の被覆導電層 1 6 , 1 7の上にビアホール 1 0 aを形成する。
ビアホール 1 0 aは、 第 1実施形態に示したと同様な方法を採用する。 即ち、 樹脂絶縁層 1 0を感光性材料で構成する場合には感光及び現像により形成し、 ま たは、 非感光性材料で構成する場合にはレーザ照射により形成する。 この場合、 ビアホール 1 0 aの下方で銅やアルミニウムから形成された端子 3， 7はそれぞ れ被覆導電層 1 6， 1 7により保護されて、，現像液やレーザに直接曝されること がなく、 現像やレーザによる劣化が防止される。 なお、 ビアホール 1 0 aはドリ リングにより形成されてもよい。
この後に、 図 1 3 (a) に示すように、 第 1実施形態と同様な工程を経て、 ビア ホール 1 0 a内にビア 1 1 aを、 樹脂絶縁層 1 0上に再配線パターン 1 1 bをそ れぞれ形成する。 さらに、 図 1 3 (b) に示すように、 埋込絶縁膜 1 2、 カバー絶 縁膜 1 3、 外部端子 1 4を形成する。 なお、 埋込絶縁膜 1 2、 カバ 絶縁膜 1 3 については、 第 2実施形態に示したように同じ樹脂膜 1 5から同時に形成しても よい。
その後に、 デバイス領域 A毎に半導体ウェハ 1を複数の第 2の半導体デバイス チップ l aに分割すると、 図 1 4に示すような半導体装置が形成される。 この場 合、 第 2の半導体デバイスチップ 1 aの側面は樹脂絶縁層 1 0に覆われずに露出 する。
以上な工程によれば、 樹脂絶縁層 1 0にビアホール 1 0 aを形成するために使 用される無機アルカリの端子 3， 7への供給を被覆導電層 1 6， 1 7によって防 止でき、 又は、 ビアホール 1 0 a形成されるために使用されるレーザの端子 3， 7への照射を被覆導電層 1 6， 1 7によって防止することができ、 端子 3， 7の 劣化が防止される。
なお、 第 1の半導体チップ 5と半導体ウェハ 1のいずれか一方の上に再配線パ ターンを形成してもよいが、 再配線パターンで覆われない端子 3 , 7には被覆導 電 1 6， 1 7で覆う必要がある。
(第 4の実施の形態）
図 6 (b) に示した第 1の半導体デバイスチップ 5は、 樹脂絶縁層 1 0の上面の 再配線パターン 1 1 bを介さずに、 ワイヤーや半田ポールを介して半導体ウェハ 1の端子 3に接続されるようにしてもよい。
例えば、 図 1 5に示すように、 第 1の半導体デバイスチップ 5の端子 7上に再 配線パターンを形成せずにニッケルリンの被覆導電層 1 7を形成し、 その被覆導 電層 1 7と半導体ウェハ （第 2の半導体デバイスチップ 1 a ) 上の再配線パター ン 4とをワイヤボンディングにより金 （導電性） ワイヤ 2 1によって接続する構 造を採用してもよい。 この場合には、 第 1の半導体デバイスチップ 5の上で樹脂 絶縁層 1 0にはビアホール 1 0 aが形成されない。
また、 図 1 6に示すように、 第 1の半導体デバイスチップ 5の端子 7上に半田 バンプ （外部端子） 2 2を接続し、 その半田バンプ 2 2を半導体ウェハ 1 (第 2 の半導体デバイスチップ 1 a ) の上の再配線パターン 4上に接続するようにして もよい。 この場合にも、 第 1の半導体デバイスチップ 5の上では樹脂絶縁層 1 0 内にビアホール 1 0 aが形成されない。 図 1 5、 図 1 6に示した樹脂絶縁層 1 0のうち第 1の半導体デバイスチップ 5 の上方にはビアホール 1 0 aは形成されないが、 樹脂絶縁層 1 0上には再配線パ ターン 1 1 bが形成されてその上に外部端子 1 4が接合される。
従って、 樹脂絶縁層 1 0上の外部端子 1 4の形成領域は従来よりも広くなり、 外部端子 1 4の数を従来よりも増やすことができ、 しかも、 外部端子 1 4の狭ピ ツチ化が緩和される。
以上述べたように本発明によれば、 大きさの異なる第 1及び第 2半導体チップ を積層した構造の半導体装置において、 第 2半導体チップの上に第 1半導体チッ プを覆う絶縁膜を形成し、 絶縁膜にホールを形成し、 ホールの中に膜状のビアを 形成し、 絶縁膜上に配線パターンを形成したので、 ビアを短時間で形成すること ができ、 しかも配線パターンとビアを同じ導電膜によって構成することができて 膜の形成工程を減らすことができる。
また、 絶縁膜上の配線パターンを第 1半導体チップの上に引き出してその上に 外部端子を形成したので、 絶縁膜上での複数の外部端子の狭ピッチ化を抑制でき 、 しかも外部端子の数を増やすことができる。
さらに、 ホール内のビアを絶縁膜で覆うことによりビアの腐食を防止でき、 ま た、 絶縁膜上の第 1配線パターンのうち外部端子と接続する部分を除いて別の絶 縁膜で覆うことにより、 第 1配線パターンのマイグレーションショート、 腐食を 防止することができる。

Claims

請 求 の 範 囲
1 . 一面に第 1端子を有する第 1半導体チップと、
前記第 1半導体チップより大きく、 前記第 1半導体チップが重ねられ且つ一面 に第 2端子を有する第 2半導体チップと、
前記第 2半導体チップ上に形成されて前記第 1半導体チップを覆う絶縁膜と、 前記絶縁膜に形成される複数のホールと、
前記ホールの内周面及び底面に膜状に形成され且つ前記第 1端子と前記第 2端 子の少なくとも一方に電気的に接続される導電性のビアと、
前記絶縁膜の上面上に形成された第 1配線パターンと、
前記第 1配線パターンの上に形成された外部端子と
を有することを特徴とする半導体装置。
2 . 前記第 1端子と前記第 2端子を同じ向きにして前記第 1半導体チップが前 記第 2半導体チップ上に載置されることを特徴とする請求項 1に記載の半導体装 置。
3 . 前記第 1半導体チップの前記第 1端子は前記第 2半導体チップの前記第 2 端子と導電性ワイヤを介して接続されていることを '特徴とする請求項 2に記載の 半導体装置。
4 . 前記第 1半導体チップの前記第 1端子は、 前記第 1配線パターン、 前記ビ ァを介して前記第 2半導体チップの前記第 2端子に電気的に接続されていること を特徴とする請求項 2又は請求項 3に記載の半導体装置。
5 . 前記第 1半導体チップは接着剤を介して前記第 2半導体チップに搭載され ていることを特徴とする請求項 2〜請求項 4のいずれかに記載の半導体装置。
6 . 前記第 1半導体チップと前記第 2半導体チップは、 前記第 1端子を有する 面と前記第 2端子を有する面を互いに対向させて重なっていることを特徴とする 請求項 1に記載の半導体装置。
7 . 前記第 2半導体チップ上では前記第 2端子に電気的に接続される第 3配線 パターンが形成され、 さらに該第 3配線パターンには前記第 1半導体チップの前 記第 1端子が導電材を介して接続されることを特徴とする請求項 6に記載の半導 体装置。
8 . 前記第 1端子と前記第 2端子の少なくとも一方の上には第 2配線パターン が形成され、 前記ビァは該第 2配線パターンの上に形成されることを特徴とする 請求項 1に記載の半導体装置。
9 . 前記第 1端子、 前記第 2端子の少なくとも一方は被覆導電層を介して前記 ビアに接続されることを特徴とする請求項 1〜請求項 8のいずれかに記載の半導
1 0 . 前記ビアと前記第 1配線パターンは接続されていることを特徴とする請求 項 1〜請求項 9のいずれかに記載の半導体装置。
1 1 . 前記ホール内において前記ビアは絶縁膜によって埋め込まれることを特徴 とする請求項 1〜請求項 1 0のいずれかに記載の半導体装置。
1 2 . 前記第 1配線パターンは、 前記外部端子との接続部分を除いて前記絶縁膜 上でカバー絶縁膜により覆われていることを特徴とする請求項 1〜請求項 1 1の いずれかに記載の半導体装置。
1 3 . 前記ホール内において前記ビアの上と、 前記第 1配線のうちの前記外部端 子との接続部分を除いた領域の上に同じ絶縁膜で覆われることを特徴とする請求 項 1〜請求項 1 2のいずれかに記載の半導体装置。
1 4 . 前記第 2半導体チップの側面は露出していることを特徴とする請求項 1〜 請求項 1 3のいずれかに記載の半導体装置。
1 5 . 第 1端子を有する第 1半導体チップをこれより大きく且つ第 2端子を持つ 半導体基板上に取り付ける工程と、
前記第 1半導体チップを覆う絶縁膜を前記半導体基板上に形成する工程と、 前記絶縁膜にホールを形成する工程と、
前記ホール内と前記絶縁膜上に導電膜を形成する工程と、
前記導電膜をパターニングして前記ホール内にはビアとして残し、 前記絶縁膜 上では配線を形成する工程と、
前記第 1配線の上に外部端子を接続する工程と
を有することを特徴とする半導体装置の製造方法。
1 6 . 前記第 1端子と前記第 2端子の少なくとも一方の上に金属パターンを形成 し、 該金属パターンの上に前記ホールを形成することを特徴とする請求項 1 5に 記載の半導体装置の製造方法。
1 7 . 前記金属パターンは、 配線パターンであることを特徵とする請求項 1 6に 記載の半導体装置の製造方法。
1 8 . 前記ホールの形成は、 レーザ照射法、 フォトリソグラフィ一法、 ドリリン グ法のいずれかで形成されることを特徴とする請求項 1 5〜請求項 1 7のいずれ に記載の半導体装置の製造方法。
1 9 . 前記導電膜は、 メツキ法により形成された金属膜であることを特徴とする 請求項 1 5〜請求項 1 8のいずれかに記載の半導体装置の製造方法。
2 0 . 前記絶縁膜はエポキシ樹脂又はポリイミド樹脂であることを特徴とする請 求項 1 5〜請求項 1 9のいずれかに記載の半導体装置の製造方法。
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US7759246B2 (en) 2010-07-20
JP4182189B2 (ja) 2008-11-19
US20050001329A1 (en) 2005-01-06
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