WO2003058634A1 - Pcram rewrite prevention - Google Patents

Pcram rewrite prevention Download PDF

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Publication number
WO2003058634A1
WO2003058634A1 PCT/US2003/000239 US0300239W WO03058634A1 WO 2003058634 A1 WO2003058634 A1 WO 2003058634A1 US 0300239 W US0300239 W US 0300239W WO 03058634 A1 WO03058634 A1 WO 03058634A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
sense amplifier
une
activated
sense
Prior art date
Application number
PCT/US2003/000239
Other languages
French (fr)
Inventor
John Moore
Jake Baker
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to CN038052393A priority Critical patent/CN1679116B/en
Priority to AU2003235728A priority patent/AU2003235728A1/en
Priority to AT03729340T priority patent/ATE548734T1/en
Priority to JP2003558859A priority patent/JP4277102B2/en
Priority to EP03729340A priority patent/EP1468422B1/en
Priority to KR1020047010536A priority patent/KR100616208B1/en
Publication of WO2003058634A1 publication Critical patent/WO2003058634A1/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0011RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/003Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0033Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0061Timing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • G11C2013/0054Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/76Array using an access device for each cell which being not a transistor and not a diode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/79Array wherein the access device being a transistor

Definitions

  • the present invention relates to integrated memory circuits. More specifically,
  • PCRAM PCRAM
  • DRAM Dynamic random access memory
  • Fig. 1 is a schematic diagram of a DRAM memory cell 100 comprising an
  • the capacitor 102 which is coupled to a Vcc/2
  • a charge of one polarity e.g., a charge corresponding to a potential difference
  • a charge of the opposite polarity e.g., a charge corresponding to a potential
  • transistor 101 is coupled to a word line 103, thereby permitting the word line 103 to
  • each word line 103 is at ground potential, which causes the
  • transistor 101 to be switched off, thereby electrically isolating capacitor 102.
  • the capacitor 102 may naturally decay over time, even if the capacitor 102 remains
  • DRAM cells 100 require periodic refreshing. Additionally, as
  • refreshing is also required after a memory cell 100 has been accessed, for
  • FIG. 2 illustrates a memory device 200 comprising a plurality of memory arrays
  • sense amplifiers 300a and 300b in Fig. 2 have identical
  • N and P may denote different circuitry associated with negative or positive typed
  • Each memory array 150a, 150b includes a plurality of memory cells lOOa-lOOd,
  • Each memory array has its own set of bit lines.
  • memory array 150a includes bit lines 104a, 104b, while memory array 150b
  • bit lines 104a', 104b' The bit lines from each adjacent pair of memory arrays
  • bit lines 104a, 104a' are coupled to sense amplifier 300a, while bit lines 104b, 104b' are coupled to
  • sense amplifier 300b As explained below, the sense amplifiers 300a, 300b are used to generate the sense amplifiers 300a, 300b. As explained below, the sense amplifiers 300a, 300b are used to generate the sense amplifiers 300a, 300b. As explained below, the sense amplifiers 300a, 300b are used to generate the sense amplifiers 300a, 300b.
  • Reading a DRAM memory cell comprises the operations of accessing
  • the purpose of the access operation is to transfer charge stored on the
  • Each bit line 104a, 104b is then electrically disconnected.
  • the bit lines 104a, 104b is then electrically disconnected.
  • the word line (e.g.,
  • bit lines 104 due to inherent parasitic capacitance between bit lines 104
  • bit line 104 to increase slightly. However, in typical DRAM systems, the magnitude of this
  • bit lines 104a, 104b are associated bit lines 104a, 104b.
  • the bit lines 104a', 104b' in the other array 150b remain
  • the charge sharing causes the bit line 104a, 104b potential to
  • the sense/refresh operation serves two purposes. First, the sense/refresh
  • bit line will be driven to ground during sensing.
  • bit Une has a
  • the second purpose of the sense/refresh operation is to restore the state
  • This step is required since the access operation diluted the charge stored on the
  • Fig. 3 is a detailed lustration of a sense ampUfier 300, which comprises a N-
  • sense amp 31 OP include nodes NLAT* and ACT, respectively. These nodes are coupled to
  • Node NLAT* is initiaUy biased to the pre-
  • the sense/refresh operation is a two phased operation in which the
  • N- sense amp 310N is triggered before the P- sense amp 310P.
  • the N- sense amp 310N is triggered by bringing the potential at node NLAT*
  • the higher voltage bit line begins to conduct. This causes the lower voltage bit line to
  • NMOS transistor never conducts since its gate is coupled to the low voltage digit line being
  • the P- sense amp 310P is triggered (after the N- sense amp 310N has been
  • the PMOS transistor with its gate coupled to the lower potential bit line will begin to conduct. This causes the initiaUy higher potential bit line to
  • memory cell 100a being read is driven from the pre-charge potential of Vcc/2 to ground if
  • the memory cell 100a stored a charge corresponding to a binary 0, or to Vcc if the memory
  • ceU 100a stored a charge corresponding to a binary 1, thereby permitting a comparator (or
  • differential ampUfier 350a coupled to bit lines 104a, 104a' to output a binary 0 or 1
  • Such material could be programmed (set) to a high resistive state to store, for example, a
  • the stored data bit could then be retrieved by detecting the magnitude of a readout
  • doped chalcogenide have been investigated as data storage memory cells for use in memory
  • programmable conductor cells are called programmable conductor cells (alternatively, they are also known as
  • ceUs programmable metaUization ceUs
  • soUd metal electrolyte such as a metal doped chalcogenide and a cathode and
  • the cathode and anode causes growth of a metal dendrite which changes the resistance
  • a memory element comprised of a chalcogenide material
  • programmable conductor also known as a dendrite
  • a memory element of chalcogenide material is nearly nonvolatile, in that it need
  • PCRAM programmable conductor random access memory
  • the present invention is directed to a method and apparatus for reading a
  • programmable conductor is electrically decoupled from the bit line.
  • time is chosen to be a point in time before the N- and P- sense amplifiers have been
  • the N- and P- sense amplifier can change the potential on the bit
  • transistors may be added on each bit Une between the PCRAM cell and the sense amplifier
  • FIG. 1 is a schematic diagram of a conventional DRAM ceU
  • FIG. 2 is a schematic diagram of a conventional DRAM array
  • FIG. 3 is schematic diagram a conventional sense ampUfier
  • FIG. 4 is a schematic diagram of a PCRAM ceU
  • FIG. 5 is a schematic diagram a PCRAM array
  • FIGS. 6A and 6B are timing diagrams iUustrating the voltages on the word.
  • FIG. 7 is a flow chart illustrating the method of the invention.
  • FIG. 8 is a block diagram of a processor based system including a PCRAM in
  • FIG. 9 is a schematic diagram of a PCRAM array according to a second
  • FIG. 10 is a schematic diagram of an alternative embodiment of a PCRAM ceU
  • FIG. 4 a PCRAM ceU 400 and in Fig. 5 a memory device 500 a
  • a PCRAM cell 400 comprises an access transistor 401, a programmable conductor
  • the access transistor 401 has its gate coupled
  • bit lines 406a, 406b are
  • pre-charge circuits 501a, 105b which can switchably supply a pre-
  • access transistor 401 is coupled to one end of the programmable conductor memory
  • the cell plate 403 may span and be coupled to several other PCRAM cells.
  • the ceU plating 403 is also coupled to a potential source. In the exemplary
  • the potential source is at 1.25 volts (Vdd/2).
  • the access transistor 401 as well as the other access transistors, are depicted as
  • the programmable conductor memory element 402 is preferably
  • the programmable conductor memory element 402 stores a binary 0 when
  • the programmable conductor is ideally programmed to store a low
  • conductor can be nondestructively read by a reading voltage having a magnitude of less
  • the reading voltage is 0.2 volt. However, it is not limited to 0.25 volt.
  • Fig. 5 Ulustrates a memory device 500 comprising a plurality of memory arrays
  • Each memory array 550a, 550b includes a plurality of memory cells 400a-
  • memory ceUs 400 along any given bit line 406a, 406a', 406b, 406b' do not share a common word line 405a-405d. Conversely, the memory cells 400 along any word line
  • word Une may also be switchably coupled to ground via transistors 520a- 520d.
  • transistors 510a-5l0d, 520a-520d are coupled to signal lines 511a-511d used to
  • Each memory array 550a, 550b has its own set of bit Unes. For example,
  • memory array 550a includes bit lines 406a, 406b, while memory array 550b includes bit
  • bit lines 406a, 406a' are
  • bit Unes 406b, 406b' are coupled to sense ampUfier 600a, while bit Unes 406b, 406b' are coupled to sense ampUfier
  • Fig. 5 iUustrates a memory device having only two arrays 550a, 550b,
  • the device may include several million ceUs 400.
  • the memory device 500 also includes a plurality of pre-charge circuits 501a-
  • One pre-charge circuit (e.g., 501a) is provided for each pair of bit lines coupled to a
  • Each pre-charge circuit (e.g., 501a) includes two pre-charge circuits
  • transistors e.g., 501a, 501b. One terminal of each transistor is coupled to a potential
  • the potential source is at 2.5 volts (Vdd).
  • each transistor e.g., 502a, 502b
  • bit Une e.g.,
  • the gate of the each transistor (e.g., 502a, 502b) is coupled to a pre-charge control signal.
  • the transistors e.g., 502a, 502b are P-MOS
  • the transistors e.g., 502a, 502b
  • bit lines e.g., 406a, 406a'.
  • bit lines will remain at approximately the bit lines
  • pre-charge voltage level of 2.5 volts for a predetermined period of time is a pre-charge voltage level of 2.5 volts for a predetermined period of time.
  • the purpose of the access operation is to create a sma potential difference
  • bit lines e.g., 406a, 406a'
  • sense ampUfier e.g., 300a
  • comparator coupled to the bit lines to output a value corresponding to the contents of the
  • the bit Unes may be pre-charged by temporarily
  • transistors 502a-502d to conduct the pre-
  • Vdd charge voltage
  • bit lines 406a, 406a', 406b, 406b' are pre-
  • a low resistive state wiU cause the bit line to discharge faster than a high resistive
  • the word lines 405a-405d are normally at ground
  • the predetermined level is designed to create a reading voltage at the programmable
  • contact 402a which as previously explained, must have a magnitude less than the
  • the word line 401a is
  • the threshold voltage of the transistor 401a is 0.8 volt
  • bit lines 406a', 406b' remain at ground potential.
  • bit Une 406a is used in combination with the two
  • a sense amplifier e.g., 300a
  • the memory is designed and operated so that if the programmable contact
  • bit Une 406a discharges slowly, thereby causing it to
  • bit line 406a discharges at a faster rate, so that bit line 406 transitions to
  • Word line deactivation may be achieved by, for example, grounding terminal
  • electrical characteristics of the memory device 500, T2 may occur, for example, between
  • the predetermined time t must be sufficiently long to permit the logical state of the
  • conductor 402a can be distinguished and amplified by the sense ampUfier 300a.
  • bit Une e.g., 406a'
  • T3 is approximately 30 nanosecond after
  • T4 is approximately 35 nanosecond after Tl (end of step S5). However, it is not limited
  • wiU have one of its bit Unes (e.g., 406a) at Vcc potential and the other bit Une (e.g., 406a')
  • a comparator (or differential ampUfier) 350 can be used to output a value corresponding to the contents of the ceU 400a
  • Fig. 9 is an uTustration of a memory device 900 according to an alternate
  • PCRAM ceUs which do not include an access transistor 401.
  • Fig. 10 For example, Fig. 10
  • programmable conductor memory element 402 which is coupled to a bit line 104.
  • programmable conductor memory element 402 is also coupled to the word line via a diode
  • the diode circuit comprises two diodes 1001a, 1001b arranged as shown.
  • the memory device 900 is otherwise very similar to the memory device 500 of
  • memory device 900 includes new isolation transistors
  • the invention operates in memory device 900 in a manner very
  • the isolation transistor 901a which is normaUy conducting, is turned off,
  • bit line 406a The portion of the bit line between the transistor
  • FIG. 8 is a block diagram of a processor based system 800, such as a computer
  • the memory 802 may be constituted as one or more memory chips or
  • memory integrated circuits mounted on a memory module for example, a plug-in memory
  • the processor based on a SIMM, DIMM, or other plug-in memory module.
  • SIMM SIMM, DIMM, or other plug-in memory module.
  • DIMM DIMM
  • plug-in memory module such as a SIMM, DIMM, or other plug-in memory module.
  • system 800 includes a processor 801, a memory 802, a mass storage 803, and an I/O
  • processor 801 could be any type of processor and may include
  • Memory 802 is Ulustrated in Fig.
  • memory 802 may only include a
  • 800 may include a pluraUty of mass storage devices, possibly of varying types such as, but
  • disks not limited to, floppy disks, CDROMs, CD-R, CD-RW, DVD, hard disks, and disk arrays.
  • I/O device 804 may likewise comprise a pluraUty of I/O devices of varying types,
  • keyboard including, but not limited to keyboard, mouse, graphic cards, monitors, and network
  • Bus 805 while illustrated as a single bus may comprise a plurality of buses
  • Some of the devices 801-804 may be coupled to only a single bus 805, others may be
  • the present invention provides a PCRAM ceU 400 and a method for reading
  • the PCRAM ceU 400 includes an access
  • transistor 401 has a gate coupled to a word Une.
  • word Une is deactivated the predetermined amount of time after it has been activated
  • the PCRAM cell 400 does not include an
  • the PCRAM cell instead utilize diodes.
  • the PCRAM cell instead utilize diodes.
  • isolation transistor may be inserted between the programmable
  • the isolation transistors which are normally conducting, may be

Abstract

A programmable conductor memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the programmable contact memory cell has an access transistor, the access transistor is switched off to decouple the cell from the bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For programmable contact memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell. The isolation transistor, normally conducting, is switched off after the predetermined time past the time the bit line begins to discharge through the programmable contact memory cell, thereby isolating the programmable contact memory cell from the sense amplifier before a sensing operation begins.

Description

PCRAM REWRITE PREVENTION
FIELD OF INVENTION
[0001] The present invention relates to integrated memory circuits. More specifically,
it relates to a method for reading a programmable conductor random access memory
(PCRAM) cell.
BACKGROUND OF THE INVENTION
[0002] Dynamic random access memory (DRAM) integrated circuit arrays have
existed for more than thirty years and their dramatic increase in storage capacity has been
achieved through advances in semiconductor fabrication technology and circuit design
technology. The tremendous advances in these two technologies have also achieved higher
levels of integration that permit dramatic reductions in memory array size and cost, as well
as increased process yield.
[0003] Fig. 1 is a schematic diagram of a DRAM memory cell 100 comprising an
access transistor 101 and a capacitor 102. The capacitor 102, which is coupled to a Vcc/2
potential source and the transistor 101, stores one bit of data in the form of a charge.
Typically, a charge of one polarity (e.g., a charge corresponding to a potential difference
across the capacitor 102 of +Vcc/2) is stored in the capacitor 102 to represent a binary "1"
while a charge of the opposite polarity (e.g., a charge corresponding to a potential
difference across the capacitor 102 of -Vcc/2) represents a binary "0." The gate of the
transistor 101 is coupled to a word line 103, thereby permitting the word line 103 to
control whether the capacitor 102 is conductively coupled via the transistor 101 to a bit line 104. The default state of each word line 103 is at ground potential, which causes the
transistor 101 to be switched off, thereby electrically isolating capacitor 102.
[0004] One of the drawbacks associated with DRAM cells 100 is that the charge on
the capacitor 102 may naturally decay over time, even if the capacitor 102 remains
electrically isolated. Thus, DRAM cells 100 require periodic refreshing. Additionally, as
discussed below, refreshing is also required after a memory cell 100 has been accessed, for
example, as part of a read operation.
[0005] Fig. 2 illustrates a memory device 200 comprising a plurality of memory arrays
150a, 150b. (Generally, in the drawings, elements having the same numerical value are of
the same type. For example, sense amplifiers 300a and 300b in Fig. 2 have identical
circuitry to sense amplifier 300 of Fig. 3. A lower case alphabetic suffix is generally used to
discriminate between different units of the same type. However, upper case prefixes, such
as "N" and "P" may denote different circuitry associated with negative or positive typed
variants.) Each memory array 150a, 150b includes a plurality of memory cells lOOa-lOOd,
lOOe-lOOh arranged by tiling a plurality of memory cells 100 together so that the memory
cells 100 along any given bit line 104a, 104a', 104b, 104b' do not share a common word
Une 103a-103d. Conversely, the memory cells 100 along any word line 103 do not share a
common bit line 104a, 104a', 104b, 104b'. Each memory array has its own set of bit lines.
For example, memory array 150a includes bit lines 104a, 104b, while memory array 150b
includes bit lines 104a', 104b'. The bit lines from each adjacent pair of memory arrays
150a, 150b are coupled to a common sense amplifier 300a, 300b. For example, bit lines 104a, 104a' are coupled to sense amplifier 300a, while bit lines 104b, 104b' are coupled to
sense amplifier 300b. As explained below, the sense amplifiers 300a, 300b are used to
conduct the sense/refresh portion when a memory cell lOOa-lOOh is read.
[0006] Reading a DRAM memory cell comprises the operations of accessing and
sensing/refreshing.
[0007] The purpose of the access operation is to transfer charge stored on the
capacitor 102 to the bit line 104 associated with the memory cell 100. The access
operation begins by precharging each bit line 104a, 104a', 104b, 104b' to a predetermined
potential (e.g., Vcc/2) by coupling each bit line 104a, 104b to a potential source (not
illustrated). Each bit line 104a, 104b is then electrically disconnected. The bit lines 104a,
104a', 104b, 104b' will float at the predetermined potential due to the inherent
capacitance of the bit lines 104a, 104a', 104b, 104b'. Subsequently, the word line (e.g.,
103a) associated with a memory cell being read (e.g., 100a) is activated by raising its
potential to a level which causes each transistor 101a, lOle coupled to the word line 103a
to gate. It should be noted that due to inherent parasitic capacitance between bit lines 104
and word lines 103, activation of a word line 103 will cause the potential at each associated
bit line 104 to increase slightly. However, in typical DRAM systems, the magnitude of this
potential change is insignificant in comparison to the magnitude of the potential change on
the bit lines due to charge sharing. Therefore, with respect to DRAM systems only, further
discussion regarding the effect of parasitic capacitance is omitted. [0008] Activation of the word line 103a causes each capacitor 102a, 102e of each
memory cell 100a, lOOe coupled to that word line 103a to share its charge with its
associated bit line 104a, 104b. The bit lines 104a', 104b' in the other array 150b remain
at the pre-charge potential. The charge sharing causes the bit line 104a, 104b potential to
either increase or decrease, depending upon the charge stored in the capacitors 102a, 102e.
Since only the bit lines 104a, 104b of one memory array has its potential altered, at each
sense amplifier 300a, 300b, a differential potential develops between the bit lines 104a,
104b associated with the activated word line 103a and the other bit lines 104a', 104b'
associated with the same sense amplifier 300a, 300b. Thus, the access operation causes the
bit lines 104a, 104b associated with the cell 100a being read to have a potential which is
either greater than or less than the pre-charged voltage. However, the change in potential
is small and requires amplification before it can be used.
[0009] The sense/refresh operation serves two purposes. First, the sense/refresh
operation amplifies the small change in potential to the bit line coupled to the cell which
was accessed. If the bit Une has a potential which is lower than the pre-charge potential,
the bit line will be driven to ground during sensing. Alternatively, if the bit Une has a
potential which is higher than the pre-charge potential, the bit line will be driven to Vcc
during sensing. The second purpose of the sense/refresh operation is to restore the state
of the charge in the capacitor of the accessed cell to the state it had prior to the access
operation. This step is required since the access operation diluted the charge stored on the
capacitor by sharing it with the bit Une. [0010] Fig. 3 is a detailed lustration of a sense ampUfier 300, which comprises a N-
sense amp 3 ION and a P- sense amp portion 31 OP. The N- sense amp 3 ION and the P-
sense amp 31 OP include nodes NLAT* and ACT, respectively. These nodes are coupled to
controllable potential sources (not illustrated). Node NLAT* is initiaUy biased to the pre-
charge potential of the bit lines 104 (e.g., Vcc/2) while node ACT is initiaUy biased to
ground. In this initial state, the transistors 301-304 of the N- and P- sense amps 310N,
31 OP are switched off. The sense/refresh operation is a two phased operation in which the
N- sense amp 310N is triggered before the P- sense amp 310P.
[0011] The N- sense amp 310N is triggered by bringing the potential at node NLAT*
from the pre-charge potential (e.g., Vcc/2) towards ground potential. As the potential
difference between node NLAT* and the bit lines 104a, 104a', 104b, 104b' approach the
threshold potential of NMOS transistors 301, 302, the transistor with the gate coupled to
the higher voltage bit line begins to conduct. This causes the lower voltage bit line to
discharge towards the voltage of the NLAT* node. Thus, when node NLAT* reaches
ground potential, the lower voltage bit line will also reach ground potential. The other
NMOS transistor never conducts since its gate is coupled to the low voltage digit line being
discharged towards ground.
[0012] The P- sense amp 310P is triggered (after the N- sense amp 310N has been
triggered) by bringing the potential at node ACT from ground towards Vcc. As the
potential of the lower voltage bit Une approaches ground (caused by the earUer triggering
of the N- sense amp 3 ION), the PMOS transistor with its gate coupled to the lower potential bit line will begin to conduct. This causes the initiaUy higher potential bit line to
be charged to a potential of Vcc. After both the N- and P- sense amps 310N, 310P have
been triggered, the higher voltage bit Une has its potential elevated to Vcc while the lower
potential bit line has it potential reduced to ground. Thus, the process of triggering both
sense amps 3 ION, 31 OP ampUfies the potential difference created by the access operation to
a level suitable for use in digital circuits. In particular, the bit line 104a associated with the
memory cell 100a being read is driven from the pre-charge potential of Vcc/2 to ground if
the memory cell 100a stored a charge corresponding to a binary 0, or to Vcc if the memory
ceU 100a stored a charge corresponding to a binary 1, thereby permitting a comparator (or
differential ampUfier) 350a coupled to bit lines 104a, 104a' to output a binary 0 or 1
consistent with the data stored in the cell 100a on signal Une 351. Additionally, the charge
initiaUy stored on the capacitor 102a of the accessed ceU is restored to its pre-access state.
[0013] Efforts continue to identify other forms of memory elements for use in
memory cells. Recent studies have focused on resistive materials that can be programmed
to exhibit either high or low stable ohmic states. A programmable resistance element of
such material could be programmed (set) to a high resistive state to store, for example, a
binary "1" data bit or programmed to a low resistive state to store a binary "0" data bit.
The stored data bit could then be retrieved by detecting the magnitude of a readout
current switched through the resistive memory element by an access device, thus indicating
the stable resistance state it had previously been programmed to. [0014] Recently chalcogenide glasses fabricated with soUd electrolyte such as a metal
doped chalcogenide have been investigated as data storage memory cells for use in memory
devices, such as DRAM memory devices. U.S. Patents 5,761,115, 5,896,312, 5,914,893,
and 6,084,796 all describe this technology and are incorporated herein by reference. The
storage ceUs are called programmable conductor cells (alternatively, they are also known as
programmable metaUization ceUs). One characteristic of such a ceU is that it typicaUy
includes soUd metal electrolyte such as a metal doped chalcogenide and a cathode and
anode spaced apart on a surface of the fast ion conductor. AppUcation of a voltage across
the cathode and anode causes growth of a metal dendrite which changes the resistance and
capacitance of the ceU which can then be used to store data.
[0015] One particularly promising programmable, bi-stable resistive material is an
aUoy system including Ge:Se:Ag. A memory element comprised of a chalcogenide material
has a natural stable high resistive state but can be programmed to a low resistance state by
passing a current pulse from a voltage of suitable polarity through the cell. This causes a
programmable conductor, also known as a dendrite, to grow between the anode and
cathode which lowers the cell resistance. A chalcogenide memory element is simply written
over by the appropriate current pulse and voltage polarity (reverse of that which writes the
ceU to a low resistance state) to reprogram it, and thus does not need to be erased.
Moreover, a memory element of chalcogenide material is nearly nonvolatile, in that it need
only be rarely (e.g., once per week) connected to a power supply or refreshed, in order to
retain its programmed low resistance state. Such memory ceUs, unUke DRAM ceUs, can be
accessed without requiring a refresh. [0016] While conventional sense amp circuitry, such as those associated with DRAM
cells, are capable of sensing programmable conductor random access memory (PCRAM)
cells, the natural refresh operation associated with these sense amplifiers are not required in
a PCRAM context. Indeed, frequent rewriting of PCRAM ceUs is not desirable because it
can cause the PCRAM cell to become resistant to rewriting. Accordingly, there is a need
and desire for a circuit and method for reading PCRAM ceUs without refreshing them.
SUMMARY OF THE INVENTION
[0017] The present invention is directed to a method and apparatus for reading a
PCRAM memory cell without refreshing the ceU. At a predetermined time after the
programmable conductor of the PCRAM ceU has been coupled to its bit line, the
programmable conductor is electrically decoupled from the bit line. The predetermined
time is chosen to be a point in time before the N- and P- sense amplifiers have been
activated. In this manner, the N- and P- sense amplifier can change the potential on the bit
line without causing the altered potential to rewrite the PCRAM cell. In PCRAM arrays
which use access transistors having gates coupled to word lines, the present invention may
be practiced by deactivating the word line at the predetermined time after the word Une has
been activated. In PCRAM arrays which do not include access transistors, isolation
transistors may be added on each bit Une between the PCRAM cell and the sense amplifier
to decouple the PCRAM cells from their associated bit lines. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The foregoing and other advantages and features of the invention wiU become
more apparent from the detailed description of exemplary embodiments of the invention
given below with reference to the accompanying drawings in which:
[0019] FIG. 1 is a schematic diagram of a conventional DRAM ceU;
[0020] FIG. 2 is a schematic diagram of a conventional DRAM array;
[0021] FIG. 3 is schematic diagram a conventional sense ampUfier;
[0022] FIG. 4 is a schematic diagram of a PCRAM ceU;
[0023] FIG. 5 is a schematic diagram a PCRAM array;
[0024] FIGS. 6A and 6B are timing diagrams iUustrating the voltages on the word and
bit lines when a PCRAM cell is read in high resistance and low resistance states,
respectively.
[0025] FIG. 7 is a flow chart illustrating the method of the invention;
[0026] FIG. 8 is a block diagram of a processor based system including a PCRAM in
accordance with the principles of the present invention; [0027] FIG. 9 is a schematic diagram of a PCRAM array according to a second
embodiment of the present invention; and
[0028] FIG. 10 is a schematic diagram of an alternative embodiment of a PCRAM ceU
for use with the PCRAM array of FIG. 9.
DETAILED DESCRIPTION OF THE INVENTION
[0029] Now referring to the drawings, where like reference numerals designate like
elements, there is shown in Fig. 4 a PCRAM ceU 400 and in Fig. 5 a memory device 500 a
memory device comprised of a plurahty of PCRAM ceUs 400a-400h. As illustrated in Fig.
4, a PCRAM cell 400 comprises an access transistor 401, a programmable conductor
memory element 402, and a cell plate 403. The access transistor 401 has its gate coupled
to a word line 405 and one terminal coupled to a bit line 406. A small portion of an array
of such ceUs is shown in Fig. 5 as including bit lines 406a, 406a', 406b, 406b', and word
lines 405a, 405b, 405c, and 405d. As shown in Fig. 5, the bit lines 406a, 406b are
coupled to a respective pre-charge circuits 501a, 105b, which can switchably supply a pre-
charge potential to the bit lines 406a, 406a', 406b, 406b'. The other terminal of the
access transistor 401 is coupled to one end of the programmable conductor memory
element 402, while the other end of the programmable conductor memory element 402 is
coupled to a cell plate 403. The cell plate 403 may span and be coupled to several other PCRAM cells. The ceU plating 403 is also coupled to a potential source. In the exemplary
embodiment the potential source is at 1.25 volts (Vdd/2).
[0030] The access transistor 401, as well as the other access transistors, are depicted as
N-type CMOS transistors, however, it should be understood that P-type CMOS transistors
may be used as long as the corresponding polarities of the other components and voltages
are modified accordingly. The programmable conductor memory element 402 is preferably
made of chalcogenide, however, it should be understood that any other bi-stable resistive
material known to those with ordinary skiU in the art may also be used. In the exemplary
embodiment, the programmable conductor memory element 402 stores a binary 0 when
has a resistance of approximately 10 K ohm, and a binary 1 when it has a resistance greater
than 10 M ohm. The programmable conductor is ideally programmed to store a low
resistance, e.g., binary 0, by a voltage of +0.25 volt and can be restored to a high resistance
value, e.g., a binary 1, by a programming voltage of -0.25 volt. The programmable
conductor can be nondestructively read by a reading voltage having a magnitude of less
than 0.25 volt. In the exemplary embodiment, the reading voltage is 0.2 volt. However, it
should be readily apparent that alternate parameters may be selected for the PCRAM cell
without departing from the spirit and scope of the invention.
[0031] Fig. 5 Ulustrates a memory device 500 comprising a plurality of memory arrays
550a, 550b. Each memory array 550a, 550b includes a plurality of memory cells 400a-
400d, 400e-400h arranged by tiling a plurality of memory cells 400 together so that the
memory ceUs 400 along any given bit line 406a, 406a', 406b, 406b' do not share a common word line 405a-405d. Conversely, the memory cells 400 along any word line
405a-405d do not share a common bit Une 406a, 406a', 406b, 406b'. Each word Une is
switchably to a word Une driver 512a- 512d via a transistor 510a-510d. AdditionaUy, each
word Une may also be switchably coupled to ground via transistors 520a- 520d. The gates
of the transistors 510a-5l0d, 520a-520d are coupled to signal lines 511a-511d used to
selectively couple/decouple the word lines 405a-405d to/from the word line drivers 512a-
512b /ground. Each memory array 550a, 550b has its own set of bit Unes. For example,
memory array 550a includes bit lines 406a, 406b, while memory array 550b includes bit
lines 406a', 406b'. The bit Unes from each adjacent pair of memory arrays 550a, 550b are
coupled to a common sense ampUfier 600a, 600b. For example, bit lines 406a, 406a' are
coupled to sense ampUfier 600a, while bit Unes 406b, 406b' are coupled to sense ampUfier
600b. For simpUcity, Fig. 5 iUustrates a memory device having only two arrays 550a, 550b,
and eight ceUs 400a-400h. However, it should be understood that real world memory
devices would have significantly more ceUs and arrays. For example, a real world memory
device may include several million ceUs 400.
[0032] The memory device 500 also includes a plurality of pre-charge circuits 501a-
501b. One pre-charge circuit (e.g., 501a) is provided for each pair of bit lines coupled to a
sense ampUfier (e.g., 406a, 406a'). Each pre-charge circuit (e.g., 501a) includes two
transistors (e.g., 501a, 501b). One terminal of each transistor is coupled to a potential
source . In the exemplary embodiment, the potential source is at 2.5 volts (Vdd). Another
terminal of each transistor (e.g., 502a, 502b) is coupled to its corresponding bit Une (e.g.,
406a, 406a', respectively). The gate of the each transistor (e.g., 502a, 502b) is coupled to a pre-charge control signal. As illustrated, the transistors (e.g., 502a, 502b) are P-MOS
type transistor. Thus, when the pre-charge signal is low, the transistors (e.g., 502a, 502b)
conducts, thereby pre-charging the bit lines (e.g., 406a, 406a'). When the pre-charge
signal is high, the transistors (e.g., 502a, 502b) are switched off. Due to capacitance
inherent in the bit Unes (e.g., 406a, 406a'), the bit lines will remain at approximately the
pre-charge voltage level of 2.5 volts for a predetermined period of time.
[0033] Reading a PCRAM cell, for example, ceU 400a, in the PCRAM device 500
comprises the operations of accessing and sensing.
[0034] The purpose of the access operation is to create a sma potential difference
between the bit lines (e.g., 406a, 406a') coupled to the same sense ampUfier (e.g., 300a) of
the memory cell 400a being read. This small potential difference can be subsequently
ampUfied by a sense amplifier 300 to the threshold required to subsequently drive a
comparator coupled to the bit lines to output a value corresponding to the contents of the
memory cell 400a. Now also referring to Fig. 7, the access operation begins with the pre¬
charging of the bit Unes 406a, 406a', 406b, 406b' of the memory device 500 via pre-
charge circuits 501a-501b (step SI). The bit Unes may be pre-charged by temporarily
bringing the pre-charge signal low, causing transistors 502a-502d to conduct the pre-
charge voltage (Vdd) to the bit lines 406a, 406a', 406b, 406b'. Once the pre-charge signal
returns to a high state, the transistors 502a-502d stop conducting, but the bit Unes 406a,
406a', 406b, 406b' wiU remain at the pre-charge potential for a predetermined period due
to the capacitance inherent in the bit lines. [0035] In the exemplary embodiment, bit lines 406a, 406a', 406b, 406b' are pre-
charged to 2.5 volts and the ceU plate 403a, 403b is tied to 1.25 volts. The 1.25 volt
potential difference between the bit line and the ceU plate wiU cause the bit Une to
discharge to the ceU plate through the access transistor 401 (when it is in a conductive
state) and the programmable conductor memory element 402. The discharge rate is
dependent upon the resistive state of the programmable conductor memory element 402.
That is, a low resistive state wiU cause the bit line to discharge faster than a high resistive
state. As the bit Une discharges, its voltage will fall from the pre-charge voltage toward the
cell plate voltage.
[0036] In the memory device 500, the word lines 405a-405d are normally at ground
potential. Thus the access transistors 401a-401e are normaUy switched off. Now also
referring to Figs. 6A and 6B, at time Tl, the word Une 405a associated with the ceU 400a
to be read is activated by bringing its potential from ground to a predetermined level (step
S2). The predetermined level is designed to create a reading voltage at the programmable
contact 402a, which as previously explained, must have a magnitude less than the
magnitude of a writing voltage. In the exemplary embodiment, the word line 401a is
brought to 2.25 volt. Since the threshold voltage of the transistor 401a is 0.8 volt, the
potential at the interface between the transistor 401a and the programmable contact 402a
is 1.45 volt. This results in a reading voltage of 0.2 volt since the voltage at the interface
between the programmable contact 402a and the ceU plate 403a is maintained at 1.25 volt. [0037] Due to the inherent parasitic capacitance between the word Une 401a and its
associated bit lines 406a the potential in the associated bit line 406a increase as the word
line 401a is activated. In the exemplary embodiment, the potential in bit Une 406a
increases by 0.1 volt to 2.6 volt. It should be noted that the word Unes 405c, 405d
coupled to complementary bit lines 406a', 406b' remain at ground potential. Thus, bit
Unes 406a', 406b' remain at the pre-charge potential, which is 2.5 volt in the exemplary
embodiment.
[0038] The increased potential of bit Une 406a is used in combination with the two
bi-stable resistive states of the programmable contact 402a to cause one of the bit Unes
(e.g., 406a) coupled to a sense amplifier (e.g., 300a) to have either a greater or lesser
voltage than the other bit line (e.g., 406a') coupled to the same sense ampUfier 300a.
EssentiaUy, the parasitic capacitance between word lines and associated bit lines is used to
achieve an initial state where the bit Une (e.g., 406a) associated with the ceU 400a being
read is at a higher potential than the other bit line 406a' coupled to the same sense
amplifier 300a. The memory is designed and operated so that if the programmable contact
402a has a high resistive state, bit Une 406a discharges slowly, thereby causing it to
maintain its relatively higher potential. However, if the programmable contact 402a has a
low resistive state, bit line 406a discharges at a faster rate, so that bit line 406 transitions to
a lower potential state than bit Une 406a'. These two effects can be seen by comparing Fig.
6A (iUustrating the effects of a programmable contact at a high resistive state) and Fig. 6B
(iUustrating the effects of a programmable contact at a low resistive state.) [0039] At time T2, a predetermined time t after time Tl (step S3), the word line 405a
associated with the ceU 400a being read is deactivated by returning its potential to ground
(step S4). Word line deactivation may be achieved by, for example, grounding terminal
511a, which will cause the transistor 510a serially coupling the word Une driver 512a to the
word Une 405a to stop conducting. This shuts off access transistors 401a, 401 thereby
preventing further discharge of the bit Une through the programmable contact 402a, 402e.
This also prevents the ampUfied potential difference developed during the subsequent
sensing operation from refreshing (writing) the programmable contact 402a, 402e. In the
rare instance when it would be desirable to refresh the contents of the programmable
contact 402a, 402e, the word line can be held high for a longer period of time. This mode
of operation is shown via the dashed trace in Figs. 6A and 6B. In the exemplary
embodiment, the predetermined time t is approximately 15 nanosecond (i.e., T2 = Tl + 15
ns).
[0040] It should be noted that the values of t and T2 may be varied without departing
from spirit of the invention. In particular, the objectives of the present invention will be
reaUzed by electrically decoupling the programmable contact from the bit Une at any time
before the bit line voltages are ampUfied by the sense amplifiers 3 ION, 31 OP to a level
which result in the potential difference across the programmable contact reaching threshold
required to write the programmable contact. Thus, while Figs. 6A and 6B illustrate T2
occurring prior to either sense ampUfiers 3 ION, 31 OP being activated, depending upon the
electrical characteristics of the memory device 500, T2 may occur, for example, between
the activation of the N- sense amp 310N and the P- sense amp 310P. Regardless, the predetermined time t must be sufficiently long to permit the logical state of the
programmable conductor 402a to be reflected on the bit line 406a; i.e., the bit Une 406a
voltage to be sufficiently altered from the pre-charge voltage by the discharge through the
programmable conductor 402a so that the two resistive states of the programmable
conductor 402a can be distinguished and amplified by the sense ampUfier 300a.
[0041] At time period T3, the N- sense amplifier 310N is activated (start of step S5).
As previously noted with respect to DRAM systems, activating the N-sense ampUfier causes
the bit Une (e.g., 406a') having the lower potential to be puUed with the NLAT signal
toward ground. In the exemplary embodiment, T3 is approximately 30 nanosecond after
Tl . However, it should be noted that the value T3 may be varied without departing from
spirit of the invention.
[0042] At time period T4, the P- sense amplifier 310P is activated. As previously
noted with respect to DRAM systems, activating the P-sense ampUfier causes the bit line
(e.g., 406a) having the higher potential to be puUed towards Vcc. In the exemplary
embodiment, T4 is approximately 35 nanosecond after Tl (end of step S5). However, it
should be noted that the value of T4 may be varied without departing from spirit of the
invention.
[0043] At time T5, the sense ampUfier 300a associated with the ceU 400a being read
wiU have one of its bit Unes (e.g., 406a) at Vcc potential and the other bit Une (e.g., 406a')
at ground potential. Since one bit line coupled to sense amplifier 300a is now at ground
potential while the other bit Une is now at Vcc potential, a comparator (or differential ampUfier) 350 can be used to output a value corresponding to the contents of the ceU 400a
on signal Une 351a.
[0044] Fig. 9 is an uTustration of a memory device 900 according to an alternate
embodiment of the present invention. This alternate embodiment is designed for use with
PCRAM ceUs which do not include an access transistor 401. For example, Fig. 10
illustrates one example of a PCRAM ceU 400' which utiUzes a pair of diodes 1001a, 1001b
in Ueu of an access transistor. As iUustrated, the PCRAM ceU 400' features a
programmable conductor memory element 402 which is coupled to a bit line 104. The
programmable conductor memory element 402 is also coupled to the word line via a diode
circuit 1002. The diode circuit comprises two diodes 1001a, 1001b arranged as shown.
[0045] The memory device 900 is otherwise very similar to the memory device 500 of
the first embodiment. However, memory device 900 includes new isolation transistors
901a-901d which seria y connect the sense amplifiers 300a, 300d to the bit lines 406a,
406a', 406b, 406b'. The invention operates in memory device 900 in a manner very
similar to memory device 500 except that instead of deactivating word lines 405a to
electrically decouple memory cell 400a from amplified voltages on the bit line 406a' prior
to sensing, the isolation transistor 901a, which is normaUy conducting, is turned off,
thereby bifurcating the bit line 406a. The portion of the bit line between the transistor
901a and the sense ampUfier 301a wiU then be sensed whUe the portion of the bit Une
between the transistor 901a and the pre-charge circuit 501a will be isolated from the sense
ampUfier. [0046] Fig. 8 is a block diagram of a processor based system 800, such as a computer
system, containing a PCRAM semiconductor memory 802 as described in connection with
the other figures. The memory 802 may be constituted as one or more memory chips or
memory integrated circuits mounted on a memory module, for example, a plug-in memory
module such as a SIMM, DIMM, or other plug-in memory module. The processor based
system 800 includes a processor 801, a memory 802, a mass storage 803, and an I/O
device 804, each coupled to a bus 805. WhUe a single processor 801 is illustrated, it
should be understood that processor 801 could be any type of processor and may include
multiple processor and/or processors and co -processors. Memory 802 is Ulustrated in Fig.
9 as having a plurahty of PCRAM chips 500. However, memory 802 may only include a
single PCRAM device 500, or a larger plurality of PCRAM devices 500 than Ulustrated,
and/or may include additional forms of memories, such as non-volatile memory or cache
memories. While one mass storage 803 device is illustrated, the processor based system
800 may include a pluraUty of mass storage devices, possibly of varying types such as, but
not limited to, floppy disks, CDROMs, CD-R, CD-RW, DVD, hard disks, and disk arrays.
I/O device 804 may likewise comprise a pluraUty of I/O devices of varying types,
including, but not limited to keyboard, mouse, graphic cards, monitors, and network
interfaces. Bus 805, while illustrated as a single bus may comprise a plurality of buses
and/or bridges, which may be coupled to each other or bridged by other components.
Some of the devices 801-804 may be coupled to only a single bus 805, others may be
coupled to a plurality of buses 805. [0047] The present invention provides a PCRAM ceU 400 and a method for reading
the contents of the cell 400 using sense ampUfiers but without rewriting the contents of the
ceU. Rewrite prevention is achieved by isolating the programmable conductor 402 of the
cell 400 from the bit line 406 a predetermined amount of time after the programmable
conductor 402 has been electrically coupled to the bit line 406. The predetermined
amount of time corresponds a time prior to the activation time of both the N- and P- sense
amps 310N, 310P. In the exemplary embodiment, the PCRAM ceU 400 includes an access
transistor 401 for electrica y coupUng and decoupling the ceU to the bit line. The access
transistor 401 has a gate coupled to a word Une. Thus, in the exemplary embodiment, the
word Une is deactivated the predetermined amount of time after it has been activated,
thereby ensuring that the activation of the N- and P- sense amplifiers 3 ION, 31 OP do not
rewrite the ceU 400. In another embodiment, the PCRAM cell 400 does not include an
access transistor. For example, the PCRAM cell instead utilize diodes. In any embodiment
without an access transistor, isolation transistor may be inserted between the programmable
contact memory element and the bit line associated with the programmable contact
memory element. The isolation transistors, which are normally conducting, may be
switched off at the same predetermined time as in the exemplary embodiment, after the
word Une has been activated, thereby achieving the same result of isolating the
programmable contact memory element from the elevated voltages generated during
sensing.
[0048] WhUe the invention has been described in detaU in connection with the
exemplary embodiment, it should be understood that the invention is not limited to the above disclosed embodiment. Rather, the invention can be modified to incorporate any
number of variations, alternations, substitutions, or equivalent arrangements not heretofore
described, but which are commensurate with the spirit and scope of the invention.
Accordingly, the invention is not Umited by the foregoing description or drawings, but is
only Umited by the scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A memory device comprising,
an apparatus for reading data from a programmable conductor random access
memory cell, said apparatus comprising:
an access circuit for coupling said memory ceU between an addressed and activated
word line and an addressed and activated bit line during a read operation;
a sense amplifier coupled to said addressed and activated bit Une for sensing a logical
state of said memory cell; and
preventing circuitry for preventing said memory cell from being refreshed in
response to said read operation.
2. The memory device of claim 1, wherein said access circuit is a transistor
circuit and said preventing circuitry causes said activated word line to be deactivated after a
logical state of said memory ceU is transferred to said activated bit line and before said sense
amplifier senses a logical state of said memory ceU.
3. The memory device of claim 2, wherein said preventing circuitry comprises a
transistor which causes said activated word line to be deactivated.
4. The memory device of claim 3, wherein said transistor is serially connected
between said word Une and a driver for said word line and is turned on during said read
operation and turned off to deactivate said row Une.
5. The memory device of claim 3, wherein said transistor is connected between
said word line and ground and is turned off during said read operation and is turned on to
deactivate said word line.
6. The memory device of claim 1, wherein said preventing circuitry comprises a
transistor serially connected between an activated bit line and a sense amplifier associated
with the activate bit line, said seriaUy connected transistor being turned on during a read
operation and turned off before said memory cell can be refreshed.
7. The memory device of claim 1, wherein said preventing circuitry causes said
activated word line to be deactivated a predetermined amount of time after said memory
ceU begins to transfer a logical state to said activated bit Une.
8. The memory device of claim 7, wherein said sense amplifier further comprises
a first sense amplifier portion and a second sense ampUfier portion.
9. The memory device of claim 8, wherein said predetermined amount of time
is after said first sense amplifier portion is activated and before said second sense amplifier
portion is activated.
10. The memory device of claim 8, wherein said first sense ampUfier portion is a
N-sense amplifier, and said second sense amplifier portion is a P-sense ampUfier.
11. The memory device of claim 1 further comprising:
a pre-charge circuit for pre-charging the addressed and activated bit line and an
another bit line, wherein said addressed and accessed bit Une and said other bit line are
coupled to the sense amplifier.
12. The memory device of claim 11, wherein said pre-charge circuit pre-charges
the addressed and activated bit line and the another bit Une prior to the sense ampUfier
sensing said addressed and activated bit line.
13. An system comprising,
a processor; and
a memory, said memory further comprising,
an apparatus for reading data from a programmable conductor random access
memory cell, said apparatus comprising:
an access circuit for coupling said memory cell between an addressed and
activated word line and an addressed and activated bit Une during a read
operation;
a sense amplifier coupled to said addressed and activated bit line for sensing a
logical state of said memory cell; and
preventing circuitry for preventing said memory ceU from being refreshed in
response to said read operation.
14. The system of claim 13, wherein said access circuit is a transistor circuit and
said preventing circuitry causes said activated word Une to be deactivated after a logical state
of said memory ceU is transferred to said activated bit line and before said sense ampUfier
senses a logical state of said memory ceU.
15. The system of claim 14, wherein said preventing circuitry comprises a
transistor which causes said activated word line to be deactivated.
16. The system of claim 15, wherein said transistor is seriaUy connected between
said word Une and a driver for said word line and is turned on during said read operation
and turned off to deactivate said row Une.
17. The system of claim 15, wherein said transistor is connected between said
word line and ground and is turned off during said read operation and is turned on to
deactivate said word Une.
18. The system of claim 13, wherein said preventing circuitry comprises a
transistor serially connected between an activated bit line and a sense amplifier associated
with the activate bit line, said serially connected transistor being turned on during a read
operation and turned off before said memory cell can be refreshed.
19. The system of claim 13, wherein said preventing circuitry causes said
activated word Une to be deactivated a predetermined amount of time after said memory
cell begins to transfer a logical state to said activated bit line.
20. The system of claim 19, wherein said sense ampUfier further comprises a first
sense ampUfier portion and a second sense ampUfier portion.
21. The system of claim 20, wherein said predetermined amount of time is after
said first sense amplifier portion is activated and before said second sense amplifier portion
is activated.
22. The system of claim 20, wherein said first sense ampUfier portion is a N-sense
ampUfier and said second sense amplifier portion is a P-sense amplifier.
23. The system of claim 13 further comprising:
a pre-charge circuit for pre-charging the addressed and activated bit line and an
another bit line, wherein said addressed and accessed bit Une and said other bit Une are
coupled to the sense ampUfier.
24. The system of claim 23, wherein said pre-charge circuit pre-charges the
addressed and activated bit Une and the another bit line prior to the sense amplifier sensing
said addressed and activated bit Une.
25. A method for reading data from a programmable conductor random access
memory cell, said method comprising: activating an addressed word Une containing said programmable conductor random
access memory cell and transferring a logical value in said ceU to an associated addressed bit
Une;
deactivating said addressed word Une; and
sensing a logical value transferred to said bit line after said word line is deactivated.
26. The method of claim 25, wherein said deactivating takes place a
predetermined amount of time after said activating.
27. The method of claim 25, wherein said sensing further comprises,
activating a first sense amplifier unit; and
activating a second sense ampUfier unit a second predetermined time after said
activating of said first sense ampUfier unit.
28. The method of claim 25, wherein said deactivating takes place a first
predetermined amount of time after said activating of an addressed word line.
29. The method of claim 28, wherein said first predetermined amount of time is
after said activating of said first sense amplifier unit and before said activating of said second
sense ampUfier unit.
30. The method of claim 28, wherein said first predetermined amount of time is
before said activating of said first sense amplifier unit and before said activating of said
second sense amplifier unit.
31. A method for reading data from a programmable conductor random access
memory ceU, said method comprising:
activating an addressed word line containing said programmable conductor random
access memory ceU and transferring a logical value in said ceU to an associated addressed bit
line;
switching off an isolation transistor located on the associated addressed bit line and
serially connecting a sense amplifier and said ceU;
sensing a logical value transferred to said bit Une after said word Une is deactivated.
32. The method of claim 31, wherein said switching off takes place a
predetermined amount of time after said activating.
33. The method of claim 31, wherein said sensing further comprises,
activating a first sense amplifier unit; and
activating a second sense ampUfier unit a second predetermined time after said
activating of said first sense ampUfier unit.
34. The method of claim 32, wherein said switching off takes place a first
predetermined amount of time after said activating of an addressed word line.
35. The method of claim 34, wherein said first predetermined amount of time is
after said activating of said first sense amplifier unit and before said activating of said second
sense ampUfier unit.
36. The method of claim 34, wherein said first predetermined amount of time is
before said activating of said first sense amplifier unit and before said activating of said
second sense ampUfier unit.
37. A method for reading data from a programmable conductor random access
memory cell, said method comprising:
pre-charging a first bit line coupled to the programmable conductor random access
memory ceU, said memory cell including a programmable conductor memory element;
pre-charging a second bit Une;
increasing voltage on said first bit line;
switching on an access transistor of said cell to couple the programmable conductor
memory element to said first bit line;
switching off the access transistor of said ceU to decoupling the programmable
conductor memory element from said first bit line;
sensing voltage on said first bit Une and said second bit line to determine a logical
state of said programmable conductor memory element;
wherein said switching off is performed before said sensing.
38. A method for reading data from a programmable conductor random access
memory cell, said method comprising:
36. The method of claim 34, wherein said first predetermined amount of time is
before said activating of said first sense ampUfier unit and before said activating of said
second sense ampUfier unit.
37. A method for reading data from a programmable conductor random access
memory ceU, said method comprising:
pre-charging a first bit line coupled to the programmable conductor random access
memory cell, said memory cell including a programmable conductor memory element;
pre-charging a second bit line;
increasing voltage on said first bit line;
switching on an access transistor of said cell to couple the programmable conductor
memory element to said first bit line;
switching off the access transistor of said cell to decoupling the programmable
conductor memory element from said first bit line;
sensing voltage on said first bit line and said second bit line to determine a logical
state of said programmable conductor memory element;
wherein said switching off is performed before said sensing.
38. A method for reading data from a programmable conductor random access
memory cell, said method comprising:
29 switching on an isolation transistor to couple a first bit line to a sense amplifier, said first bit line also coupled to a programmable conductor memory element of the programmable conductor random access memory ceU;
pre-charging said first bit line;
pre-charging a second bit line;
increasing voltage on said first bit line;
switching off said isolation transistor to decouple said programmable conductor memory element from said sense amplifier;
sensing voltage on said first bit line and said second bit line to determine a logical state of said programmable conductor memory element;
wherein said switching off is performed before said sensing.
30
PCT/US2003/000239 2002-01-04 2003-01-06 Pcram rewrite prevention WO2003058634A1 (en)

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AT03729340T ATE548734T1 (en) 2002-01-04 2003-01-06 PCRAM REWRITE PREVENTION
JP2003558859A JP4277102B2 (en) 2002-01-04 2003-01-06 Prevention of rewriting of PCRAM
EP03729340A EP1468422B1 (en) 2002-01-04 2003-01-06 Pcram rewrite prevention
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