WO2003058690A2 - Deposition of tungsten for the formation of conformal tungsten silicide - Google Patents

Deposition of tungsten for the formation of conformal tungsten silicide Download PDF

Info

Publication number
WO2003058690A2
WO2003058690A2 PCT/US2002/040944 US0240944W WO03058690A2 WO 2003058690 A2 WO2003058690 A2 WO 2003058690A2 US 0240944 W US0240944 W US 0240944W WO 03058690 A2 WO03058690 A2 WO 03058690A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
tungsten
capacitor
polysilicon layer
over
Prior art date
Application number
PCT/US2002/040944
Other languages
French (fr)
Other versions
WO2003058690A3 (en
Inventor
Hyungsuk Yoon
Hui Zhang
Michael Yang
Ken Kaung Lai
Robert Jackson
Alfred Mak
Ming Xu
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2003058690A2 publication Critical patent/WO2003058690A2/en
Publication of WO2003058690A3 publication Critical patent/WO2003058690A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

Definitions

  • Embodiments of the present invention generally relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques. More particularly, embodiments of the present invention relate to methods and apparatuses for depositing a tungsten film by cyclical deposition technique in the formation of tungsten suicide for use in capacitor structures.
  • DRAM Dynamic random-access memory
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • each capacitor may be individually charged or discharged in order to store one bit of information.
  • 64 Mbit, 256 Mbit, 1 Gbit, and larger DRAMs smaller memory cells with smaller capacitor structures are needed.
  • One limitation to reducing the size of memory ceils is that the capacitors must have enough capacitance for reliable storage ability.
  • FIG. 1 is a schematic cross sectional view of a prior art three-dimensional trench capacitor 2.
  • the trench capacitor 2 is formed in a trench 4 etched vertically into the surface of a silicon substrate 6.
  • An insulating layer 7 comprising a dielectric material is formed over the trench 2, and a polysilicon layer 8 is formed over the insulating layer 7.
  • the silicon substrate 6 acts as a first electrode and the polysilicon layer 8 acts as the second electrode in the trench capacitor 2.
  • the trench capacitor 2 occupies a smaller area on the surface of the substrate 6 in comparison to a planar capacitor. Therefore, it is desirable to form trench capacitors in trench structures having openings with reduced widths to increase the amount of charge stored per surface area of semiconductor substrate.
  • the capacitance of the trench capacitor 2 increases as the depth of the trench 4 increases due to the increased surface area of the electrodes. Therefore, it is also desirable to form trench capacitors in trench structures with higher aspect ratios to increase the capacitance of the trench capacitors. With other types of three-dimensional capacitors, it is also desirable to form capacitors over structures with aggressive geometries, such as over openings having reduced widths and having high aspect ratios.
  • Embodiments of the present invention generally relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques. More particularly, embodiments of the present invention relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques in the formation of tungsten suicide for use in capacitor structures.
  • One embodiment of forming an electrode for a capacitor structure comprises depositing a polysilicon layer over a structure and depositing a tungsten layer over the polysilicon layer by cyclical deposition techniques. The tungsten layer is annealed to form a tungsten suicide layer from the polysilicon layer and the tungsten layer. The tungsten suicide layer acts as one electrode in the capacitor structure.
  • the tungsten suicide layer may be used to form three-dimensional capacitor structures, such as trench capacitors, crown capacitors, and other types of capacitors.
  • the tungsten suicide layer may be used to form capacitor structures which comprise a hemi-spherical silicon grain layer or a rough polysilicon layer.
  • Figure 1 is a schematic cross sectional view of a prior art three- dimensional trench capacitor.
  • Figure 2 is a schematic cross sectional view of one exemplary embodiment of a processing system adapted to perform cyclical deposition.
  • Figures 3A-3D are cross-sectional views of a substrate illustrating one embodiment of the sequential fabrication steps in the formation of a capacitor.
  • Figures 4A-D are simplified drawings illustrating one embodiment of the alternating adsorption of monolayers of a tungsten containing compound and of monolayers of a reducing gas on a structure.
  • Figures 5A-C are cross-sectional views of a substrate illustrating another embodiment of the sequential fabrication steps in the formation of a capacitor.
  • Figure 6 is a schematic top view of one example of a multi-chamber processing system.
  • Figures 7A-B are cross sectional views of a substrate illustrating still another embodiment of the sequential fabrication steps in the formation of a capacitor.
  • FIG. 2 is a schematic cross-sectional view of one exemplary embodiment of a processing system 10 that may be used to deposit tungsten by cyclical deposition techniques in accordance with aspects of the present invention.
  • cyclical deposition refers to the sequential introduction of reactants to deposit a thin layer over a structure and includes processing techniques such as atomic layer deposition and rapid sequential chemical vapor deposition.
  • the sequential introduction of reactants may be repeated to deposit a plurality of thin layers to form a conformal layer to a desired thickness. More than one of the reactants may be present in the chamber at the same time during the sequential introduction of reactants. Alternatively, only one of the reactants may be present in the chamber at one time during the sequential introduction of reactants.
  • the present invention also includes depositing tungsten by cyclical deposition techniques utilizing other processing systems.
  • the processing system 10 of Figure 2 includes a housing 14 defining a processing chamber 16 with a slit valve opening 44 and a vacuum lid assembly 20.
  • Slit valve opening 44 allows transfer of a wafer (not shown) between processing chamber 16 and the exterior of system 10. Any conventional wafer transfer device may achieve the aforementioned transfer.
  • the vacuum lid assembly 20 includes a lid 21 and a process fluid injection assembly 30 to deliver reactive (i.e. precursor, reductant, oxidant), carrier, purge, cleaning and/or other fluids into the processing chamber 16.
  • the fluid injection assembly 30 includes a gas manifold 34 mounting a plurality of control valves 32 (one is shown in Figure 2), and a baffle plate 36.
  • Valves 32 provide rapid gas flows with valve open and close cycles of less than about one second, and in one embodiment, of less than about 0.1 second.
  • the valves 32 are surface mounted, electronically controlled valves, such as electronically controlled valves available from Fujikin of Japan as part number FR-21-6.35 UGF — APD. Other valves that operate at substantially the same speed may also be used.
  • the lid assembly 20 may further include one or more gas reservoirs (not shown) which are fluidically connected between one or more process gas sources (such as vaporized precursor sources) and the gas manifold 34.
  • the gas reservoirs may provide bulk gas delivery proximate to each of the valves 32.
  • the reservoirs are sized to insure that an adequate gas volume is available proximate to the valves 32 during each cycle of the valves 32 during processing to minimize time required for fluid delivery thereby shortening sequential deposition cycles.
  • the reservoirs may be about 5 times the volume required in each gas delivery cycle.
  • the vacuum lid assembly 20 may include one or more valves, such as three valves 32. Two of the valves 32 are fluidly coupled to two separate process gas sources. One of the valves 32 is fluidly coupled to a purge gas source. Each valve 32 is fluidly coupled to a separate trio of gas channels 71a, 71 b, 73 (one trio is shown in Figure 2) of the gas manifold 34. Gas channel 71a provides passage of gases through the gas manifold 34 to the valves 32. Gas channel 71b delivers gases from the valves 32 through the gas manifold 34 and into a gas channel 73. Channel 73 is fluidly coupled to a respective inlet passage 86 disposed through the lid 21.
  • Gases flowing through the inlet passages 86 flow into a plenum or region 88 defined between the lid 21 and the baffle plate 36 before entering the chamber 16.
  • the baffle plate 36 is utilized to prevent gases injected into the chamber 16 from blowing off gases adsorbed onto the surface of the substrate.
  • the baffle plate 36 may include a mixing lip 84 to re-direct gases toward the center of the plenum 88 and into the process chamber 16.
  • a heater/lift assembly 46 Disposed within processing chamber 16 is a heater/lift assembly 46 that includes a wafer support pedestal 48.
  • the heater/lift assembly 46 may be moved vertically within the chamber 16 so that a distance between support pedestal 48 and vacuum lid assembly 20 may be controlled.
  • the support pedestal may include an embedded heater element, such as a resistive heater element or heat transfer fluid, utilized to control the temperature thereof.
  • a substrate disposed on the , support pedestal 48 may be heated using radiant heat.
  • the support pedestal 48 may also be configured to hold a substrate thereon, such as by a vacuum chuck, by an electrostatic chuck, or by a clamp ring.
  • a pumping channel 62 Disposed along the side walls 14b of the chamber 16 proximate the lid assembly 20 is a pumping channel 62.
  • the pumping channel 62 is coupled by a conduit 66 to a pump system 18 which controls the amount of flow from the processing chamber 16.
  • a plurality of supplies 68a, 68b and 68c of process and/or other fluids, are in fluid communication with one of valves 32 through a sequence of conduits (not shown) formed through the housing 14, lid assembly 20, and gas manifold 34.
  • the processing system 10 may include a controller 70 which regulates the operations of the various components of system 10.
  • the present invention relates to methods for depositing a tungsten film by cyclical deposition techniques in the formation of tungsten suicide for use in capacitor structures. It is believed that the mode of deposition of an ALD tungsten film provides conformal coverage over structures. Therefore, a tungsten suicide film can be formed from an ALD tungsten film over structures having aggressive geometries, such as structures with openings having reduced widths and having higher aspect ratios.
  • the present invention may be used to advantage in forming a tungsten suicide electrode in three-dimensional capacitors, such as trench capacitors, crown capacitors, or other capacitors.
  • Figures 3A-3D are cross-sectional views of a substrate illustrative of one possible capacitor structure.
  • FIG. 3A shows a structure 302 at one stage in the formation of a trench capacitor.
  • the structure 302 comprises a substrate 312 having a trench 314 formed therein by patterning and etching, such as a silicon substrate, germanium substrate, or a gallium arsenide substrate.
  • the structure comprises a conductive layer, such as a polysilicon layer, deposited over a trench formed in a dielectric layer.
  • the bottom and the lower sidewalls of the trench 314 are doped with arsenic, antimony, phosphorus, boron, or other dopants to formed doped areas 316.
  • the doped areas 316 act as a buried first electrode in the trench capacitor.
  • the structure 302 may include a collar 322, such as a silicon oxide collar, to server as an insulating layer in the final device structure.
  • a hemispherical silicon grain layer (HSG) 318 or a rough polysilicon layer may be optionally formed over the doped areas 316 to increase the surface area of the first electrode.
  • One example of forming a hemi-spherical silicon grain layer or a rough polysilicon layer comprises depositing an amorphous silicon layer. The amorphous silicon layer is annealed to transform the amorphous silicon layer to a polysilicon layer having a rough surface.
  • the hemi-spherical silicon grain layer 318 may also be doped.
  • the structure 302 further includes an insulating layer 332 comprising a dielectric material, such as tantalum pentoxide (Ta2O5), silicon oxide/silicon nitride/oxynitride ("ONO"), and other dielectric materials including high dielectric constant materials.
  • the insulating layer 332 preferably comprises Ta2O5 or other high dielectric constant materials because a high dielectric constant material allows the insulating layer 332 to be thinner and thus allows for larger capacitance densities.
  • Examples of other high dielectric constant materials include, but are not limited to, barium strontium titanate, barium titanate, lead zirconate titanate, lead lanthanium titanate, strontium titanate, and strontium bismuth titanate.
  • Figure 3B shows a polysilicon layer 342 deposited over the structure 302 of Figure 3A.
  • Any suitable method and apparatus may be used to deposit the polysilicon layer 342.
  • the polysilicon layer 342 may be deposited by chemical vapor deposition utilizing a Polygen CenturaTM chamber, commercially available from Applied Materials, Inc., located in Santa Clara, California.
  • One exemplary process regime for depositing the polysilicon layer comprises flowing silane (SiH4) into the chamber to thermally decompose to polysilicon over the structure 302.
  • the substrate 312 is heated to a substrate temperature between about 550°C and about 700°C at a chamber pressure between about 80 torr and about 160 torr.
  • the polysilicon layer 342 may be doped or undoped.
  • Figure 3C shows a tungsten layer 352 deposited by cyclical deposition over the polysilicon layer 342.
  • Cyclical deposition of the tungsten layer 352 may be performed by the chamber described above in Figure 2 and other suitable chambers.
  • cyclical deposition of a tungsten layer 352 comprises sequentially and alternatively providing a tungsten containing compound and a reducing gas in a process chamber. While other attractive and/or boding forces may be at work and/or may contribute to the process, sequentially providing a tungsten containing compound and a reducing gas is believed to result in the alternating adsorption of monolayers of a tungsten containing compound and of monolayers of a reducing compound over a structure.
  • ALD atomic- layer deposition
  • a monolayer of a tungsten containing compound 405 is adsorbed on the structure 400 by introducing a pulse of the tungsten containing compound 405 into a process chamber, such as into system 10 as described in Figure 2. It is believed that the adsorption processes used to adsorb the monolayer of the tungsten containing compound 405 are self-limiting in that only one monolayer may be adsorbed onto the surface of the substrate 400 during a given pulse because the surface of the substrate has a finite number of sites for adsorbing the tungsten containing compound. Once the finite number of sites are occupied by the tungsten containing compound 405, further adsorption of any tungsten containing compound will be blocked.
  • the tungsten containing compound 405 may adsorb onto the surface of the substrate. Any of the tungsten containing compound 405 not adsorbed will flow out of the chamber as a result of the vacuum system, carrier gas flow, and/or purge gas flow.
  • the tungsten containing compound 405 typically comprises tungsten atoms (W) 410 with one or more reactive species (a) 415.
  • the tungsten containing compound 405 may be tungsten hexafluoride (WF6), tungsten carbonyl (W(CO)6), or other suitable tungsten containing compounds.
  • the tungsten containing compound 405 may be provided as a gas or may be provided with the aid of a carrier gas.
  • the tungsten containing compound 405, such as WF6, may be a gas and may be introduced with or without a carrier gas.
  • the tungsten containing compound 405 may be a liquid and may be introduced by bubbling a carrier gas therethrough.
  • carrier gases examples include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), and combinations thereof.
  • the carrier gas may be provided as pulses to provide pulses of the tungsten containing compound 405.
  • the carrier gas may be provided as a continuous flow into the chamber in which pulses of the tungsten containing compound 405 is provided by dosing the carrier gas with the tungsten containing compound.
  • a purge gas is introduced.
  • purge gases which may be used include, but are not limited to, hydrogen (H2), helium (He), argon (Ar), nitrogen (N2), other gases, and combinations thereof.
  • the purge gas may be provided as pulses or may be provided as a continuous flow into the chamber.
  • the purge gas and the carrier gas may comprise or different gas flows or may comprise the same gas flow. If the purge gas and the carrier gas comprise different gas flows, the purge gas and the carrier gas preferably comprise the same composition.
  • a pulse of a reducing gas 425 is introduced into the process chamber in which the purge gas separates the pulse of the tungsten containing compound 405 and the pulse of the reducing gas 425.
  • Suitable reducing gases may include for example, silane (SiH4), borane (BH3), diborane (B2H6), triborane (B3H9), tetraborane (B4H12), pentaborane (B5H15), hexaborane (B6H18), heptaborane (B7H21), octaborane (B8H24), nanoborane (B9H27), and decaborane (B10H30), among others.
  • the reducing gas may be introduced alone or may be introduced with a carrier.
  • the reducing gas, such as diborane may be a gas and may be introduced with or without a carrier gas.
  • the reducing gas may be introduced by bubbling a carrier gas therethrough.
  • carrier gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), and combinations thereof.
  • the carrier gas may be provided as pulses to provide pulses of the reducing gas.
  • the carrier gas may be provided as a continuous flow into the chamber in which pulses of the reducing gas is provided by dosing the carrier gas with the reducing gas.
  • a monolayer of the reducing gas 425 may be adsorbed on the monolayer of the tungsten containing compound 405.
  • the adsorbed monolayer of the reducing gas 425 reacts with the monolayer of the tungsten containing compound 405 to form a tungsten layer 409.
  • the reactive species (a) 415 form by-products (ab) 440, that are transported from the substrate surface by the vacuum system, carrier gas flow, and/or purge gas flow. It is believed that the reaction of the reducing gas 425 with the tungsten containing compound 405 is self-limited since only one monolayer of the tungsten containing compound 405 was adsorbed onto the substrate surface.
  • the reducing gas 425 may adsorb onto the surface of the substrate. Any of the reducing gas 425 not adsorbed will flow out of the chamber as a result of the vacuum system, carrier gas, and/or purge gas.
  • the tungsten containing compound 405 may be in an intermediate state when on a surface of the substrate 400.
  • the deposited tungsten layer 409 may also contain more than simply elements of tungsten.
  • a purge gas may be introduced.
  • the tungsten layer deposition sequence of alternating introduction of pulses of the tungsten containing compound 405 and of the reducing gas 425 separated by a purge gas may be repeated, if necessary, until a desired thickness of the tungsten layer 409 is achieved.
  • pulses of the tungsten containing compound 405 and the reducing gas 425 may be present at the same time in the chamber.
  • each pulse of the tungsten containing compound 405 and the reducing gas 425 and the purge gas flow therebetween may flow across the surface of the substrate as waves or zones present in the chamber at the same time but flowing across different portions of the substrate.
  • the tungsten layer formation is depicted as starting with the adsorption of a monolayer of a tungsten containing compound on the substrate followed by a monolayer of a reducing gas.
  • the tungsten layer formation may start with the adsorption of a monolayer of a reducing gas on the substrate followed by a monolayer of the tungsten containing compound.
  • a pump evacuation alone between pulses of reactant gases may be used to prevent simultaneous introduction of the reactant gases and to provide for alternating exposure of the substrate to a plurality of reactants.
  • the time duration for the pulses of the tungsten containing compound, the reducing gas, and the purge gas are variable and depends on the volume capacity of a deposition chamber employed as well as a vacuum system coupled thereto. For example, (1) a lower chamber pressure of a gas may require a longer pulse time; (2) a lower gas flow rate may require a longer time for chamber pressure to rise and stabilize requiring a longer pulse time; and (3) a large-volume chamber may take longer to fill and longer for chamber pressure to stabilize thus requiring a longer pulse time.
  • the time duration of a pulse of the tungsten containing compound or the reducing gas should be long enough for adsorption of a monolayer thereof.
  • the time duration of a pulse of the purge gas should be long enough to facilitate removal of the reaction by-products and/or any residual materials in the process chamber.
  • the tungsten layer may be formed over a structure at a substrate temperature between about 20°C and 800°C, and a chamber pressure less than about 100 torr.
  • a pulse time of less than about 5 seconds for a tungsten containing compound and a pulse time of less than about 2 seconds for the reducing gas are typically sufficient to form the tungsten layer on the structure.
  • a pulse time of about 2 seconds for a purge gas is typically sufficient to clean a surface of a substrate from reaction by-products as well as any residual materials for a following pulse of reactant to adsorb thereon.
  • One exemplary process of depositing a tungsten layer by cyclical deposition in a process chamber comprises sequentially providing pulses of tungsten hexafluoride (WF6) and pulses of diborane (B2H6).
  • the tungsten hexafluoride may be provided at an undiluted flow rate of between about 10 seem about 400 seem, preferably between about 20 seem and 100 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less.
  • a carrier gas such as an argon carrier gas, may be provided with the tungsten hexafluoride.
  • the diborane may be provided at an undiluted flow rate between about 5 seem and 150 seem, preferably between about 5 seem and about 25 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less.
  • a carrier gas such as an argon carrier gas
  • a purge gas such as an Argon purge gas
  • the cycle time of introducing the tungsten hexafluoride and diborane separated by a purge gas is about 2 seconds or less.
  • the substrate temperature may be maintained at a temperature between about 250°C and about 350°C at a chamber pressure of between about 1 torr and about 10 torr.
  • Another exemplary process of depositing a tungsten layer by cyclical deposition in a process chamber comprises sequentially providing pulses of tungsten hexafluoride (WF6) and pulses of silane (SiH4).
  • the tungsten hexafluoride may be provided at an undiluted flow rate of between about 20 seem and 100 seem in pulses of about 1.0 second or less, preferably about 0.2 seconds or less.
  • a carrier gas such as an argon carrier gas, may be provided with the tungsten hexafluoride.
  • the silane may be provided at an undiluted flow rate between about 10 seem and 500 seem, preferably between 50 seem and 200 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less.
  • a carrier gas such as an argon carrier gas
  • a purge gas such as an Argon purge gas
  • the cycle time of introducing the tungsten hexafluoride and silane separated by a purge gas is about 2 seconds or less.
  • the substrate temperature may be maintained at a temperature between about 300°C and about 400°C at a chamber pressure of between about 1 torr and about 10 torr.
  • the tungsten layer 352 may be annealed to form a tungsten suicide layer 362 from the tungsten layer 352 and from the polysilicon layer 342 ( Figure 3C) to serve as the second electrode in the trench capacitor.
  • the tungsten layer 352 is annealed so that the polysilicon layer 342 is only partially consumed to leave a thin polysilicon layer 343.
  • the tungsten layer 352 is annealed so that the polysilicon layer is entirely consumed.
  • one or more tungsten layers may be deposited in which each layer is annealed.
  • Annealing of the tungsten layer may be performed in any suitable anneal chamber, such as a Radiance CenturaTM rapid thermal anneal chamber available from Applied Materials, Inc., located in Santa Clara, California.
  • One exemplary process of annealing the tungsten layer 352 comprises annealing the tungsten layer 352 at a substrate temperature of between about 750°C and about 1 ,000°C for a time period of between about 45 seconds and about 120 seconds in a nitrogen gas (N2) atmosphere, although other inert gas environments may be used, such as a noble gas environment.
  • N2 nitrogen gas
  • FIGS. 7A-B are cross sectional views of a substrate illustrating another embodiment of the sequential fabrication steps in the formation of a capacitor.
  • FIG. 7A shows a tungsten layer 352a deposited by cyclical deposition over the polysilicon layer 342a to fill the trench 314a.
  • Figure 7B shows a tungsten suicide layer 362a formed from the tungsten layer 352a and the polysilicon layer 342a after annealing.
  • the tungsten layer 352a is annealed so that the polysilicon layer 342a is only partially consumed to leave a thin polysilicon layer 343a.
  • the tungsten layer 352a is annealed so that the polysilicon layer is entirely consumed.
  • the structure 302a may be further processed, such as to complete formation of the capacitor structure and to form other devices over the capacitor structure.
  • Figures 5A-C are cross-sectional views of a substrate illustrating still another embodiment of the sequential fabrication steps in the formation of a capacitor.
  • Figure 5A shows a structure 502 at one stage in the formation of a crown capacitor.
  • the structure 502 comprises a substrate 512, such as a silicon substrate, germanium substrate, or a gallium arsenide substrate, having a dielectric layer 514, such as a silicon oxide film, formed thereover.
  • the dielectric layer 514 may include access devices formed therein.
  • the dielectric layer 514 is patterned and etched to form an aperture 516.
  • a polysilicon layer 518 is formed over the dielectric layer 514 and the aperture 516.
  • the polysilicon layer 518 is doped with dopants, such as arsenic, antimony, phosphorus, boron, or other dopants.
  • a polysilicon layer 520 having a hemi-spherical silicon grain surface or a rough surface 522 is formed over the polysilicon layer 518 by depositing an amorphous film over the polysilicon layer, etching the amorphous film and the polysilicon layer 518, and subjecting the amorphous film to a heat treatment.
  • the polysilicon layer 520 may also be doped.
  • the polysilicon layer 520 having a rough surface 522 and the polysilicon layer 518 form a crown structure which acts as a first electrode.
  • the structure 502 further includes an insulating layer 532 comprising a dielectric material, such as Ta205, silicon oxide/silicon nitride/oxynitride ("ONO"), other dielectric materials, and other high dielectric constant materials.
  • the insulating layer 532 preferably comprises Ta205 or other high dielectric constant materials because a high dielectric constant material allows the insulating layer 532 to be thinner and thus allows larger capacitance densities.
  • Examples of other high dielectric constant materials include, but are not limited to, barium strontium titanate, barium titanate, lead zirconate titanate, lead lanthanium titanate, strontium titanate, and strontium bismuth titanate.
  • Figure 5B is a schematic cross-section view of forming a second electrode over the crown structure of Figure 5A.
  • a polysilicon layer 542 is deposited over the insulating layer 532 and a tungsten layer 552 is deposited by cyclical deposition over the polysilicon layer 542 by methods as described elsewhere herein.
  • the tungsten layer 552 ( Figure 5B) may be annealed to form a tungsten suicide layer 562 from the tungsten layer 552 and from the polysilicon layer 542 ( Figure 5B) to serve as the second electrode in the capacitor.
  • the tungsten layer 552 is annealed so that the polysilicon layer 542 is only partially consumed to leave a thin polysilicon layer 542A.
  • the tungsten layer 552 is annealed so that the polysilicon layer 542 is entirely consumed.
  • the structure 502 may be further processed, such as to complete formation of the capacitor structure and to form other devices over the capacitor structure.
  • Figures 3A-D, 5A-C, and 7A-B illustrate the formation of specific embodiments of capacitors.
  • the present invention includes forming a tungsten suicide electrode in other embodiments of trench capacitors, crown capacitors, and other capacitor structures including three-dimensional capacitors.
  • Forming a tungsten suicide electrode by depositing tungsten by cyclical deposition may be used to advantage in depositing a conformal tungsten layer over difficult to cover topographies, such as over narrow openings, rough surfaces, and/or steep surfaces.
  • a conformal ALD tungsten layer may be used to advantage in forming trench capacitors over structures having a high aspect ratio, in forming crown capacitors to cover the varied topography of the crown structure, or in covering the rough topographies of hemi-spherical silicon grain layers or of materials deposited over hemi-spherical silicon grain layers.
  • a conformal ALD tungsten layer may be used to advantage in forming three-dimensional capacitors over structures having small openings, such as openings of about 0.15 ⁇ m or less, and/or over structures having high aspect ratios, such as an aspect ratio of about 15:1 or more, about 20:1 or more, or even about 40:1 or more.
  • a polysilicon layer is deposited over the aperture to a sidewall and bottom coverage of between about 10 ⁇ A and about 200A and an ALD tungsten layer is deposited over the polysilicon layer to a sidewall and bottom coverage between about 50A and about 200A.
  • FIG. 6 is a schematic top view of one example of a multi-chamber processing system 600 which may be adapted to perform processes as disclosed herein.
  • the apparatus is a CenturaTM system and is commercially available from Applied Materials, Inc., located in Santa Clara, California.
  • the particular embodiment of the system 600 is provided to illustrate the invention and should not be used to limit the scope of the invention.
  • the system 600 generally includes load lock chambers 606 for the transfer of substrates into and out from the system 600.
  • the load lock chambers 606 may "pump down" the substrates introduced into the system 200.
  • a robot 602 may transfer the substrates between the load lock chambers 606 and processing chambers 604A, 604B, 604C, 604D.
  • the robot 602 may be a dual blade robot having two blades 634 for transferring two substrates. Any of the processing chambers 604A, 604B, 604C, 604D may be removed from the system 600 if not necessary for the particular process to be performed by the system 600.
  • the system 600 is configured to form a tungsten suicide electrode, such as tungsten suicide electrode 362, 362A, or 562 as described in relation to Figures 3A-3D, Figures 7A-B, or Figures 5A-5C.
  • a tungsten suicide electrode such as tungsten suicide electrode 362, 362A, or 562 as described in relation to Figures 3A-3D, Figures 7A-B, or Figures 5A-5C.
  • one embodiment of system 600 comprises a process chamber 604A adapted to deposit a polysilicon layer, such as polysilicon layer 352 of Figure 3B, polysilicon layer 352A of Figure 7A, or polysilicon layer 552 of Figure 5B;
  • process chamber 604B may be adapted to deposit a tungsten layer by cyclical deposition, such as tungsten layer 362 of Figure 3C, tungsten layer 362a of Figure 7A, or tungsten layer 562 of Figure 5B;
  • process chamber 604C may be adapted to anneal the tungsten layer to form a tungsten suicide layer, such as tungsten suicide layer 362 of Figure 3D, tungsten suicide layer 362A of Figure 7B, or tungsten suicide layer 562 of Figure 5C.
  • This embodiment of the system 600 may optionally further include process chamber 604D adapted to deposit a polysilicon layer, such as polysilicon layer 372 of Figure 3D or may further include chamber 604A adapted to deposit both a polysilicon layer 352 of Figure 3B and a polysilicon layer 372 of Figure 3D.
  • process chamber 604D adapted to deposit a polysilicon layer, such as polysilicon layer 372 of Figure 3D or may further include chamber 604A adapted to deposit both a polysilicon layer 352 of Figure 3B and a polysilicon layer 372 of Figure 3D.
  • Other configurations of system 600 are possible. For example, the position of a particular processing chamber on the system 600 may be altered. Other embodiments of the system are within the scope of the present invention. For example, an Endura SLTM multi-chamber processing system, commercially available from Applied Materials, Inc., located in Santa Clara, California, may be used. [0052] While foregoing is directed to the preferred embodiment of the present invention, other and further embodiment

Abstract

A method and apparatus of depositing a tungsten film by cyclical deposition in the formation of tungsten silicide for use in capacitor structures is provided. One embodiment of forming an electrode for a capacitor structure comprises depositing a polysilicon layer over a structure and depositing a tungsten layer over the polysilicon layer by cyclical deposition. The tungsten layer is annealed to form a tungsten silicide layer from the polysilicon layer and the tungsten layer. The tungsten silicide layer acts as one electrode in the capacitor structure. In one aspect, the tungsten silicide layer may be used to form three-dimensional capacitor structures, such as trench capacitors, crown capacitors, and other types of capacitors. In another aspect, the tungsten silicide layer may be used to form capacitor structures which comprise a hemi-spherical silicon grain layer or a rough polysilicon layer.

Description

DEPOSITION OF TUNGSTEN FOR THE FORMATION OF CONFORMAL
TUNGSTEN SILICIDE
INVENTORS:
Hyungsuk Yoon
Hui Zhang
Michael Yang
Ken Kaung Lai
Robert Jackson
Alfred Mak
Ming Xi
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] Embodiments of the present invention generally relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques. More particularly, embodiments of the present invention relate to methods and apparatuses for depositing a tungsten film by cyclical deposition technique in the formation of tungsten suicide for use in capacitor structures.
Description of the Related Art
[0002] Dynamic random-access memory (DRAM) integrated circuits are commonly used for storing data in a digital computer. Currently available DRAMs may contain over 16 million memory cells fabricated on a single silicon chip, and each memory cell generally comprises a single transistor connected to a micron or sub-micron sized capacitor. In operation, each capacitor may be individually charged or discharged in order to store one bit of information. To facilitate construction of 64 Mbit, 256 Mbit, 1 Gbit, and larger DRAMs, smaller memory cells with smaller capacitor structures are needed. One limitation to reducing the size of memory ceils is that the capacitors must have enough capacitance for reliable storage ability.
[0003] Three-dimensional capacitors, such as trench capacitors and crown capacitors, are types of capacitor structures being explored to increase the amount of charge which can be stored per surface area of a semiconductor substrate. In general, three-dimensional capacitors comprise non-planar electrodes which have increased surface area and thus increased capacitance in comparison to planar electrodes. Figure 1 is a schematic cross sectional view of a prior art three-dimensional trench capacitor 2. The trench capacitor 2 is formed in a trench 4 etched vertically into the surface of a silicon substrate 6. An insulating layer 7 comprising a dielectric material is formed over the trench 2, and a polysilicon layer 8 is formed over the insulating layer 7. The silicon substrate 6 acts as a first electrode and the polysilicon layer 8 acts as the second electrode in the trench capacitor 2. In one aspect, the trench capacitor 2 occupies a smaller area on the surface of the substrate 6 in comparison to a planar capacitor. Therefore, it is desirable to form trench capacitors in trench structures having openings with reduced widths to increase the amount of charge stored per surface area of semiconductor substrate. In another aspect, the capacitance of the trench capacitor 2 increases as the depth of the trench 4 increases due to the increased surface area of the electrodes. Therefore, it is also desirable to form trench capacitors in trench structures with higher aspect ratios to increase the capacitance of the trench capacitors. With other types of three-dimensional capacitors, it is also desirable to form capacitors over structures with aggressive geometries, such as over openings having reduced widths and having high aspect ratios.
[0004] However, conventional chemical vapor deposition techniques are inadequate in depositing material conformally in the formation of three- dimensional capacitors over structures having aggressive geometries, such as over structures having openings of about 0.15 μm or less and having an aspect ratio of about 15:1 or more, especially at the bottom of these structures. Conventional chemical vapor deposition techniques may cause material to build up on the top edge of the openings of these structures resulting in the closing off of the opening and the formation of a void.
[0005] Therefore, there exists a need for an improved method and apparatus of forming capacitor structures.
SUMMARY OF THE INVENTION
[0006] Embodiments of the present invention generally relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques. More particularly, embodiments of the present invention relate to methods and apparatuses for depositing a tungsten film by cyclical deposition techniques in the formation of tungsten suicide for use in capacitor structures. [0007] One embodiment of forming an electrode for a capacitor structure comprises depositing a polysilicon layer over a structure and depositing a tungsten layer over the polysilicon layer by cyclical deposition techniques. The tungsten layer is annealed to form a tungsten suicide layer from the polysilicon layer and the tungsten layer. The tungsten suicide layer acts as one electrode in the capacitor structure. In one aspect, the tungsten suicide layer may be used to form three-dimensional capacitor structures, such as trench capacitors, crown capacitors, and other types of capacitors. In another aspect, the tungsten suicide layer may be used to form capacitor structures which comprise a hemi-spherical silicon grain layer or a rough polysilicon layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
[0009] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0010] Figure 1 is a schematic cross sectional view of a prior art three- dimensional trench capacitor.
[0011] Figure 2 is a schematic cross sectional view of one exemplary embodiment of a processing system adapted to perform cyclical deposition. [0012] Figures 3A-3D are cross-sectional views of a substrate illustrating one embodiment of the sequential fabrication steps in the formation of a capacitor. [0013] Figures 4A-D are simplified drawings illustrating one embodiment of the alternating adsorption of monolayers of a tungsten containing compound and of monolayers of a reducing gas on a structure.
[0014] Figures 5A-C are cross-sectional views of a substrate illustrating another embodiment of the sequential fabrication steps in the formation of a capacitor. [0015] Figure 6 is a schematic top view of one example of a multi-chamber processing system.
[0016] Figures 7A-B are cross sectional views of a substrate illustrating still another embodiment of the sequential fabrication steps in the formation of a capacitor.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Process Chamber Adapted for Cyclical Deposition of Tungsten
[0017] Figure 2 is a schematic cross-sectional view of one exemplary embodiment of a processing system 10 that may be used to deposit tungsten by cyclical deposition techniques in accordance with aspects of the present invention. The term "cyclical deposition" as used herein refers to the sequential introduction of reactants to deposit a thin layer over a structure and includes processing techniques such as atomic layer deposition and rapid sequential chemical vapor deposition. The sequential introduction of reactants may be repeated to deposit a plurality of thin layers to form a conformal layer to a desired thickness. More than one of the reactants may be present in the chamber at the same time during the sequential introduction of reactants. Alternatively, only one of the reactants may be present in the chamber at one time during the sequential introduction of reactants. The present invention also includes depositing tungsten by cyclical deposition techniques utilizing other processing systems.
[0018] The processing system 10 of Figure 2 includes a housing 14 defining a processing chamber 16 with a slit valve opening 44 and a vacuum lid assembly 20. Slit valve opening 44 allows transfer of a wafer (not shown) between processing chamber 16 and the exterior of system 10. Any conventional wafer transfer device may achieve the aforementioned transfer. [0019] The vacuum lid assembly 20 includes a lid 21 and a process fluid injection assembly 30 to deliver reactive (i.e. precursor, reductant, oxidant), carrier, purge, cleaning and/or other fluids into the processing chamber 16. The fluid injection assembly 30 includes a gas manifold 34 mounting a plurality of control valves 32 (one is shown in Figure 2), and a baffle plate 36. Programmable logic controllers may be coupled to the control valves 32 to provide sequencing control of the valves. Valves 32 provide rapid gas flows with valve open and close cycles of less than about one second, and in one embodiment, of less than about 0.1 second. In one embodiment, the valves 32 are surface mounted, electronically controlled valves, such as electronically controlled valves available from Fujikin of Japan as part number FR-21-6.35 UGF — APD. Other valves that operate at substantially the same speed may also be used.
[0020] The lid assembly 20 may further include one or more gas reservoirs (not shown) which are fluidically connected between one or more process gas sources (such as vaporized precursor sources) and the gas manifold 34. The gas reservoirs may provide bulk gas delivery proximate to each of the valves 32. The reservoirs are sized to insure that an adequate gas volume is available proximate to the valves 32 during each cycle of the valves 32 during processing to minimize time required for fluid delivery thereby shortening sequential deposition cycles. For example, the reservoirs may be about 5 times the volume required in each gas delivery cycle.
[0021] The vacuum lid assembly 20 may include one or more valves, such as three valves 32. Two of the valves 32 are fluidly coupled to two separate process gas sources. One of the valves 32 is fluidly coupled to a purge gas source. Each valve 32 is fluidly coupled to a separate trio of gas channels 71a, 71 b, 73 (one trio is shown in Figure 2) of the gas manifold 34. Gas channel 71a provides passage of gases through the gas manifold 34 to the valves 32. Gas channel 71b delivers gases from the valves 32 through the gas manifold 34 and into a gas channel 73. Channel 73 is fluidly coupled to a respective inlet passage 86 disposed through the lid 21. Gases flowing through the inlet passages 86 flow into a plenum or region 88 defined between the lid 21 and the baffle plate 36 before entering the chamber 16. The baffle plate 36 is utilized to prevent gases injected into the chamber 16 from blowing off gases adsorbed onto the surface of the substrate. The baffle plate 36 may include a mixing lip 84 to re-direct gases toward the center of the plenum 88 and into the process chamber 16.
[0022] Disposed within processing chamber 16 is a heater/lift assembly 46 that includes a wafer support pedestal 48. The heater/lift assembly 46 may be moved vertically within the chamber 16 so that a distance between support pedestal 48 and vacuum lid assembly 20 may be controlled. The support pedestal may include an embedded heater element, such as a resistive heater element or heat transfer fluid, utilized to control the temperature thereof. Optionally, a substrate disposed on the , support pedestal 48 may be heated using radiant heat. The support pedestal 48 may also be configured to hold a substrate thereon, such as by a vacuum chuck, by an electrostatic chuck, or by a clamp ring.
[0023] Disposed along the side walls 14b of the chamber 16 proximate the lid assembly 20 is a pumping channel 62. The pumping channel 62 is coupled by a conduit 66 to a pump system 18 which controls the amount of flow from the processing chamber 16. A plurality of supplies 68a, 68b and 68c of process and/or other fluids, are in fluid communication with one of valves 32 through a sequence of conduits (not shown) formed through the housing 14, lid assembly 20, and gas manifold 34. The processing system 10 may include a controller 70 which regulates the operations of the various components of system 10.
Capacitor Fabrication
[0024] The present invention relates to methods for depositing a tungsten film by cyclical deposition techniques in the formation of tungsten suicide for use in capacitor structures. It is believed that the mode of deposition of an ALD tungsten film provides conformal coverage over structures. Therefore, a tungsten suicide film can be formed from an ALD tungsten film over structures having aggressive geometries, such as structures with openings having reduced widths and having higher aspect ratios. The present invention may be used to advantage in forming a tungsten suicide electrode in three-dimensional capacitors, such as trench capacitors, crown capacitors, or other capacitors. [0025] Not wishing to be bound by theory, Figures 3A-3D are cross-sectional views of a substrate illustrative of one possible capacitor structure. The present invention also includes embodiments directed to other capacitor structures. Figure 3A shows a structure 302 at one stage in the formation of a trench capacitor. In this embodiment, the structure 302 comprises a substrate 312 having a trench 314 formed therein by patterning and etching, such as a silicon substrate, germanium substrate, or a gallium arsenide substrate. In another embodiment, the structure comprises a conductive layer, such as a polysilicon layer, deposited over a trench formed in a dielectric layer. [0026] The bottom and the lower sidewalls of the trench 314 are doped with arsenic, antimony, phosphorus, boron, or other dopants to formed doped areas 316. The doped areas 316 act as a buried first electrode in the trench capacitor. The structure 302 may include a collar 322, such as a silicon oxide collar, to server as an insulating layer in the final device structure. A hemispherical silicon grain layer (HSG) 318 or a rough polysilicon layer may be optionally formed over the doped areas 316 to increase the surface area of the first electrode. One example of forming a hemi-spherical silicon grain layer or a rough polysilicon layer comprises depositing an amorphous silicon layer. The amorphous silicon layer is annealed to transform the amorphous silicon layer to a polysilicon layer having a rough surface. The hemi-spherical silicon grain layer 318 may also be doped.
[0027] The structure 302 further includes an insulating layer 332 comprising a dielectric material, such as tantalum pentoxide (Ta2O5), silicon oxide/silicon nitride/oxynitride ("ONO"), and other dielectric materials including high dielectric constant materials. In one aspect, the insulating layer 332 preferably comprises Ta2O5 or other high dielectric constant materials because a high dielectric constant material allows the insulating layer 332 to be thinner and thus allows for larger capacitance densities. Examples of other high dielectric constant materials include, but are not limited to, barium strontium titanate, barium titanate, lead zirconate titanate, lead lanthanium titanate, strontium titanate, and strontium bismuth titanate.
[0028] Figure 3B shows a polysilicon layer 342 deposited over the structure 302 of Figure 3A. Any suitable method and apparatus may be used to deposit the polysilicon layer 342. For example, the polysilicon layer 342 may be deposited by chemical vapor deposition utilizing a Polygen CenturaTM chamber, commercially available from Applied Materials, Inc., located in Santa Clara, California. One exemplary process regime for depositing the polysilicon layer comprises flowing silane (SiH4) into the chamber to thermally decompose to polysilicon over the structure 302. The substrate 312 is heated to a substrate temperature between about 550°C and about 700°C at a chamber pressure between about 80 torr and about 160 torr. The polysilicon layer 342 may be doped or undoped.
[0029] Figure 3C shows a tungsten layer 352 deposited by cyclical deposition over the polysilicon layer 342. Cyclical deposition of the tungsten layer 352 may be performed by the chamber described above in Figure 2 and other suitable chambers. In one aspect, cyclical deposition of a tungsten layer 352 comprises sequentially and alternatively providing a tungsten containing compound and a reducing gas in a process chamber. While other attractive and/or boding forces may be at work and/or may contribute to the process, sequentially providing a tungsten containing compound and a reducing gas is believed to result in the alternating adsorption of monolayers of a tungsten containing compound and of monolayers of a reducing compound over a structure. The term "adsorption" as used herein is meant to include chemisorption, physisorption, or otherwise bonding, reaction, or adherence with so as to occupy a portion of an exposed surface of a substrate structure. [0030] The composition and structure of precursors on a surface during atomic- layer deposition (ALD) is not precisely known. Not wishing to be bound by theory, Figures 4A-D are simplified drawings illustrating one embodiment of the alternating adsorption of monolayers of a tungsten containing compound and of monolayers of a reducing gas on an exemplary portion of a structure 400 in a stage of integrated circuit fabrication. In Figure 4A, a monolayer of a tungsten containing compound 405 is adsorbed on the structure 400 by introducing a pulse of the tungsten containing compound 405 into a process chamber, such as into system 10 as described in Figure 2. It is believed that the adsorption processes used to adsorb the monolayer of the tungsten containing compound 405 are self-limiting in that only one monolayer may be adsorbed onto the surface of the substrate 400 during a given pulse because the surface of the substrate has a finite number of sites for adsorbing the tungsten containing compound. Once the finite number of sites are occupied by the tungsten containing compound 405, further adsorption of any tungsten containing compound will be blocked. As a consequence, as a pulse of a tungsten containing compound 405 flows across the surface of a substrate, the tungsten containing compound 405 may adsorb onto the surface of the substrate. Any of the tungsten containing compound 405 not adsorbed will flow out of the chamber as a result of the vacuum system, carrier gas flow, and/or purge gas flow.
[0031] The tungsten containing compound 405 typically comprises tungsten atoms (W) 410 with one or more reactive species (a) 415. The tungsten containing compound 405 may be tungsten hexafluoride (WF6), tungsten carbonyl (W(CO)6), or other suitable tungsten containing compounds. The tungsten containing compound 405 may be provided as a gas or may be provided with the aid of a carrier gas. For example, the tungsten containing compound 405, such as WF6, may be a gas and may be introduced with or without a carrier gas. Alternatively, the tungsten containing compound 405 may be a liquid and may be introduced by bubbling a carrier gas therethrough. Examples of carrier gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), and combinations thereof. The carrier gas may be provided as pulses to provide pulses of the tungsten containing compound 405. Alternatively, the carrier gas may be provided as a continuous flow into the chamber in which pulses of the tungsten containing compound 405 is provided by dosing the carrier gas with the tungsten containing compound.
[0032] After a pulse of a tungsten containing compound 405 is introduced into the chamber, a purge gas is introduced. Examples of purge gases which may be used include, but are not limited to, hydrogen (H2), helium (He), argon (Ar), nitrogen (N2), other gases, and combinations thereof. The purge gas may be provided as pulses or may be provided as a continuous flow into the chamber. The purge gas and the carrier gas may comprise or different gas flows or may comprise the same gas flow. If the purge gas and the carrier gas comprise different gas flows, the purge gas and the carrier gas preferably comprise the same composition.
[0033] Referring to Figure 4B, after a purge gas has been introduced, a pulse of a reducing gas 425 is introduced into the process chamber in which the purge gas separates the pulse of the tungsten containing compound 405 and the pulse of the reducing gas 425. Suitable reducing gases may include for example, silane (SiH4), borane (BH3), diborane (B2H6), triborane (B3H9), tetraborane (B4H12), pentaborane (B5H15), hexaborane (B6H18), heptaborane (B7H21), octaborane (B8H24), nanoborane (B9H27), and decaborane (B10H30), among others. The reducing gas may be introduced alone or may be introduced with a carrier. For example, the reducing gas, such as diborane, may be a gas and may be introduced with or without a carrier gas. Alternatively, the reducing gas may be introduced by bubbling a carrier gas therethrough. Examples of carrier gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), and combinations thereof. The carrier gas may be provided as pulses to provide pulses of the reducing gas. Alternatively, the carrier gas may be provided as a continuous flow into the chamber in which pulses of the reducing gas is provided by dosing the carrier gas with the reducing gas. A monolayer of the reducing gas 425 may be adsorbed on the monolayer of the tungsten containing compound 405.
[0034] As shown in Figure 4C, it is believed that the adsorbed monolayer of the reducing gas 425 reacts with the monolayer of the tungsten containing compound 405 to form a tungsten layer 409. The reactive species (a) 415 form by-products (ab) 440, that are transported from the substrate surface by the vacuum system, carrier gas flow, and/or purge gas flow. It is believed that the reaction of the reducing gas 425 with the tungsten containing compound 405 is self-limited since only one monolayer of the tungsten containing compound 405 was adsorbed onto the substrate surface. As a consequence, as a pulse of a reducing gas 425 flows across the surface of a substrate, the reducing gas 425 may adsorb onto the surface of the substrate. Any of the reducing gas 425 not adsorbed will flow out of the chamber as a result of the vacuum system, carrier gas, and/or purge gas. In another theory, the tungsten containing compound 405 may be in an intermediate state when on a surface of the substrate 400. In addition, the deposited tungsten layer 409 may also contain more than simply elements of tungsten.
[0035] After a pulse of a reducing gas 425 is introduced into the chamber, a purge gas may be introduced. Thereafter, as shown in Figure 4D, the tungsten layer deposition sequence of alternating introduction of pulses of the tungsten containing compound 405 and of the reducing gas 425 separated by a purge gas may be repeated, if necessary, until a desired thickness of the tungsten layer 409 is achieved. [0036] In one aspect, pulses of the tungsten containing compound 405 and the reducing gas 425 may be present at the same time in the chamber. For example, each pulse of the tungsten containing compound 405 and the reducing gas 425 and the purge gas flow therebetween may flow across the surface of the substrate as waves or zones present in the chamber at the same time but flowing across different portions of the substrate. [0037] In Figures 4A-4D, the tungsten layer formation is depicted as starting with the adsorption of a monolayer of a tungsten containing compound on the substrate followed by a monolayer of a reducing gas. Alternatively, the tungsten layer formation may start with the adsorption of a monolayer of a reducing gas on the substrate followed by a monolayer of the tungsten containing compound. Furthermore, in an alternative embodiment, a pump evacuation alone between pulses of reactant gases may be used to prevent simultaneous introduction of the reactant gases and to provide for alternating exposure of the substrate to a plurality of reactants.
[0038] The time duration for the pulses of the tungsten containing compound, the reducing gas, and the purge gas are variable and depends on the volume capacity of a deposition chamber employed as well as a vacuum system coupled thereto. For example, (1) a lower chamber pressure of a gas may require a longer pulse time; (2) a lower gas flow rate may require a longer time for chamber pressure to rise and stabilize requiring a longer pulse time; and (3) a large-volume chamber may take longer to fill and longer for chamber pressure to stabilize thus requiring a longer pulse time. In general, while considering the volume of the chamber and chamber conditions, the time duration of a pulse of the tungsten containing compound or the reducing gas should be long enough for adsorption of a monolayer thereof. In general, the time duration of a pulse of the purge gas should be long enough to facilitate removal of the reaction by-products and/or any residual materials in the process chamber.
[0039] In general, the tungsten layer may be formed over a structure at a substrate temperature between about 20°C and 800°C, and a chamber pressure less than about 100 torr. A pulse time of less than about 5 seconds for a tungsten containing compound and a pulse time of less than about 2 seconds for the reducing gas are typically sufficient to form the tungsten layer on the structure. A pulse time of about 2 seconds for a purge gas is typically sufficient to clean a surface of a substrate from reaction by-products as well as any residual materials for a following pulse of reactant to adsorb thereon. [0040] One exemplary process of depositing a tungsten layer by cyclical deposition in a process chamber, such as the system 10 of Figure 2 comprises sequentially providing pulses of tungsten hexafluoride (WF6) and pulses of diborane (B2H6). The tungsten hexafluoride may be provided at an undiluted flow rate of between about 10 seem about 400 seem, preferably between about 20 seem and 100 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less. A carrier gas, such as an argon carrier gas, may be provided with the tungsten hexafluoride. The diborane may be provided at an undiluted flow rate between about 5 seem and 150 seem, preferably between about 5 seem and about 25 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less. A carrier gas, such as an argon carrier gas, may be provided with the diborane. Whether a pulse or a continuous flow, a purge gas, such as an Argon purge gas, is provided for a time period of about 1.0 second or less, preferably about 0.3 seconds or less, between the pulses of tungsten hexafluoride and the diborane. Preferably, the cycle time of introducing the tungsten hexafluoride and diborane separated by a purge gas is about 2 seconds or less. The substrate temperature may be maintained at a temperature between about 250°C and about 350°C at a chamber pressure of between about 1 torr and about 10 torr.
[0041] Another exemplary process of depositing a tungsten layer by cyclical deposition in a process chamber comprises sequentially providing pulses of tungsten hexafluoride (WF6) and pulses of silane (SiH4). The tungsten hexafluoride may be provided at an undiluted flow rate of between about 20 seem and 100 seem in pulses of about 1.0 second or less, preferably about 0.2 seconds or less. A carrier gas, such as an argon carrier gas, may be provided with the tungsten hexafluoride. The silane may be provided at an undiluted flow rate between about 10 seem and 500 seem, preferably between 50 seem and 200 seem, in pulses of about 1.0 second or less, preferably about 0.2 seconds or less. A carrier gas, such as an argon carrier gas, may be provided with the silane. Whether a pulse or a continuous flow, a purge gas, such as an Argon purge gas, is provided for a time period of about 1.0 second or less, preferably about 0.3 seconds or less between pulses of the tungsten hexafluoride and the silane. Preferably, the cycle time of introducing the tungsten hexafluoride and silane separated by a purge gas is about 2 seconds or less. The substrate temperature may be maintained at a temperature between about 300°C and about 400°C at a chamber pressure of between about 1 torr and about 10 torr.
[0042] After the tungsten layer 352 (Figure 3C) has been deposited using any reducing gas, such as diborane or silane, the tungsten layer 352 may be annealed to form a tungsten suicide layer 362 from the tungsten layer 352 and from the polysilicon layer 342 (Figure 3C) to serve as the second electrode in the trench capacitor. In the embodiment shown in Figure 3D, the tungsten layer 352 is annealed so that the polysilicon layer 342 is only partially consumed to leave a thin polysilicon layer 343. In another embodiment (not shown), the tungsten layer 352 is annealed so that the polysilicon layer is entirely consumed. In another embodiment (now shown), one or more tungsten layers may be deposited in which each layer is annealed. [0043] Annealing of the tungsten layer may be performed in any suitable anneal chamber, such as a Radiance CenturaTM rapid thermal anneal chamber available from Applied Materials, Inc., located in Santa Clara, California. One exemplary process of annealing the tungsten layer 352 comprises annealing the tungsten layer 352 at a substrate temperature of between about 750°C and about 1 ,000°C for a time period of between about 45 seconds and about 120 seconds in a nitrogen gas (N2) atmosphere, although other inert gas environments may be used, such as a noble gas environment. Another exemplary process of annealing the tungsten layer 352 comprises annealing the tungsten layer 352 in a furnace anneal chamber at a substrate temperature of between about 800°C and about 900°C for a time period of about 30 minutes. After the tungsten suicide layer 362 has been formed, a polysilicon layer 372 is deposited over the tungsten suicide layer 362 to fill the trench 314. The structure 302 may be further processed, such as to complete formation of the capacitor structure and to form other devices over the capacitor structure. [0044] Figures 7A-B are cross sectional views of a substrate illustrating another embodiment of the sequential fabrication steps in the formation of a capacitor. Some of the layers of structure 302a are the same or similar to those described in reference to Figure 3A-3D, described above. Accordingly, like numbers have been used where appropriate. Figure 7A shows a tungsten layer 352a deposited by cyclical deposition over the polysilicon layer 342a to fill the trench 314a. Figure 7B shows a tungsten suicide layer 362a formed from the tungsten layer 352a and the polysilicon layer 342a after annealing. In the embodiment shown in Figure 7B, the tungsten layer 352a is annealed so that the polysilicon layer 342a is only partially consumed to leave a thin polysilicon layer 343a. In other embodiments, the tungsten layer 352a is annealed so that the polysilicon layer is entirely consumed. The structure 302a may be further processed, such as to complete formation of the capacitor structure and to form other devices over the capacitor structure.
[0045] Figures 5A-C are cross-sectional views of a substrate illustrating still another embodiment of the sequential fabrication steps in the formation of a capacitor. Figure 5A shows a structure 502 at one stage in the formation of a crown capacitor. In this embodiment, the structure 502 comprises a substrate 512, such as a silicon substrate, germanium substrate, or a gallium arsenide substrate, having a dielectric layer 514, such as a silicon oxide film, formed thereover. The dielectric layer 514 may include access devices formed therein. The dielectric layer 514 is patterned and etched to form an aperture 516. A polysilicon layer 518 is formed over the dielectric layer 514 and the aperture 516. The polysilicon layer 518 is doped with dopants, such as arsenic, antimony, phosphorus, boron, or other dopants. A polysilicon layer 520 having a hemi-spherical silicon grain surface or a rough surface 522 is formed over the polysilicon layer 518 by depositing an amorphous film over the polysilicon layer, etching the amorphous film and the polysilicon layer 518, and subjecting the amorphous film to a heat treatment. The polysilicon layer 520 may also be doped. The polysilicon layer 520 having a rough surface 522 and the polysilicon layer 518 form a crown structure which acts as a first electrode. The structure 502 further includes an insulating layer 532 comprising a dielectric material, such as Ta205, silicon oxide/silicon nitride/oxynitride ("ONO"), other dielectric materials, and other high dielectric constant materials. In one aspect, the insulating layer 532 preferably comprises Ta205 or other high dielectric constant materials because a high dielectric constant material allows the insulating layer 532 to be thinner and thus allows larger capacitance densities. Examples of other high dielectric constant materials include, but are not limited to, barium strontium titanate, barium titanate, lead zirconate titanate, lead lanthanium titanate, strontium titanate, and strontium bismuth titanate. [0046] Figure 5B is a schematic cross-section view of forming a second electrode over the crown structure of Figure 5A. A polysilicon layer 542 is deposited over the insulating layer 532 and a tungsten layer 552 is deposited by cyclical deposition over the polysilicon layer 542 by methods as described elsewhere herein.
[0047] Referring to Figure 5C, the tungsten layer 552 (Figure 5B) may be annealed to form a tungsten suicide layer 562 from the tungsten layer 552 and from the polysilicon layer 542 (Figure 5B) to serve as the second electrode in the capacitor. In one embodiment as shown in Figure 5C, the tungsten layer 552 is annealed so that the polysilicon layer 542 is only partially consumed to leave a thin polysilicon layer 542A. In another embodiment (not shown), the tungsten layer 552 is annealed so that the polysilicon layer 542 is entirely consumed. The structure 502 may be further processed, such as to complete formation of the capacitor structure and to form other devices over the capacitor structure.
[0048] Figures 3A-D, 5A-C, and 7A-B illustrate the formation of specific embodiments of capacitors. The present invention includes forming a tungsten suicide electrode in other embodiments of trench capacitors, crown capacitors, and other capacitor structures including three-dimensional capacitors. Forming a tungsten suicide electrode by depositing tungsten by cyclical deposition may be used to advantage in depositing a conformal tungsten layer over difficult to cover topographies, such as over narrow openings, rough surfaces, and/or steep surfaces. For example, a conformal ALD tungsten layer may be used to advantage in forming trench capacitors over structures having a high aspect ratio, in forming crown capacitors to cover the varied topography of the crown structure, or in covering the rough topographies of hemi-spherical silicon grain layers or of materials deposited over hemi-spherical silicon grain layers. In one specific embodiment, a conformal ALD tungsten layer may be used to advantage in forming three-dimensional capacitors over structures having small openings, such as openings of about 0.15 μm or less, and/or over structures having high aspect ratios, such as an aspect ratio of about 15:1 or more, about 20:1 or more, or even about 40:1 or more. In one specific embodiment, in forming a capacitor structure in an aperture having an opening of about 0.15 μm or less and having an aspect ratio between about 15:1 and about 20:1 , a polysilicon layer is deposited over the aperture to a sidewall and bottom coverage of between about 10θA and about 200A and an ALD tungsten layer is deposited over the polysilicon layer to a sidewall and bottom coverage between about 50A and about 200A.
Platform for Forming Tungsten Suicide Electrode
[0049] The processes as disclosed herein may be carried out in separate chambers or may be carried out in a multi-chamber processing system having a plurality of chambers. Figure 6 is a schematic top view of one example of a multi-chamber processing system 600 which may be adapted to perform processes as disclosed herein. The apparatus is a CenturaTM system and is commercially available from Applied Materials, Inc., located in Santa Clara, California. The particular embodiment of the system 600 is provided to illustrate the invention and should not be used to limit the scope of the invention.
[0050] The system 600 generally includes load lock chambers 606 for the transfer of substrates into and out from the system 600. Typically, since the system 600 is under vacuum, the load lock chambers 606 may "pump down" the substrates introduced into the system 200. A robot 602 may transfer the substrates between the load lock chambers 606 and processing chambers 604A, 604B, 604C, 604D. The robot 602 may be a dual blade robot having two blades 634 for transferring two substrates. Any of the processing chambers 604A, 604B, 604C, 604D may be removed from the system 600 if not necessary for the particular process to be performed by the system 600. [0051] In one embodiment, the system 600 is configured to form a tungsten suicide electrode, such as tungsten suicide electrode 362, 362A, or 562 as described in relation to Figures 3A-3D, Figures 7A-B, or Figures 5A-5C. For example, one embodiment of system 600 comprises a process chamber 604A adapted to deposit a polysilicon layer, such as polysilicon layer 352 of Figure 3B, polysilicon layer 352A of Figure 7A, or polysilicon layer 552 of Figure 5B; process chamber 604B may be adapted to deposit a tungsten layer by cyclical deposition, such as tungsten layer 362 of Figure 3C, tungsten layer 362a of Figure 7A, or tungsten layer 562 of Figure 5B; and process chamber 604C may be adapted to anneal the tungsten layer to form a tungsten suicide layer, such as tungsten suicide layer 362 of Figure 3D, tungsten suicide layer 362A of Figure 7B, or tungsten suicide layer 562 of Figure 5C. This embodiment of the system 600 may optionally further include process chamber 604D adapted to deposit a polysilicon layer, such as polysilicon layer 372 of Figure 3D or may further include chamber 604A adapted to deposit both a polysilicon layer 352 of Figure 3B and a polysilicon layer 372 of Figure 3D. Other configurations of system 600 are possible. For example, the position of a particular processing chamber on the system 600 may be altered. Other embodiments of the system are within the scope of the present invention. For example, an Endura SLTM multi-chamber processing system, commercially available from Applied Materials, Inc., located in Santa Clara, California, may be used. [0052] While foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A method of forming an electrode for a three-dimensional capacitor structure, comprising: depositing a polysilicon layer over a structure; depositing a tungsten layer over the polysilicon layer by cyclical deposition; and annealing the tungsten layer to form a tungsten suicide layer from the polysilicon layer and the tungsten layer.
2. The method of claim 1 , wherein annealing the tungsten layer comprises partially consuming the polysilicon layer.
3. The method of claim 1 , wherein annealing the tungsten layer comprises entirely consuming the polysilicon layer.
4. The method of claim 1 , wherein the tungsten layer is deposited to a thickness between about 5θA and about 200A.
5. The method of claim 1 , wherein the tungsten layer is deposited over an aperture having an opening of about 0.15 μm or less.
6. The method of claim 1 , wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 15:1 or more.
7. The method of claim 6, wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 20:1 or more.
8. The method of claim 7, wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 40:1 or more.
9. The method of claim 1 , wherein the structure is a crown structure.
10. The method of claim 1 , wherein the structure is a trench structure.
11. A method of forming a capacitor structure, comprising: forming a rough polysilicon surface; depositing a high dielectric constant material layer over the rough polysilicon surface; depositing a polysilicon layer over the high dielectric constant material layer; depositing a tungsten layer over the polysilicon layer by cyclical deposition; and annealing the tungsten layer to form a tungsten suicide layer from the polysilicon layer and the tungsten layer.
12. The method of claim 11 , wherein annealing the tungsten layer comprises partially consuming the polysilicon layer.
13. The method of claim 11 , wherein annealing the tungsten layer comprises entirely consuming the polysilicon layer.
14. The method of claim 11 , wherein the tungsten layer is deposited to a thickness between about 5θA and about 200A.
15. The method of claim 11 , wherein the tungsten layer is deposited over an aperture having an opening of about 0.15 μm or less.
16. The method of claim 11 , wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 15:1 or more.
17. The method of claim 16, wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 20:1 or more.
18. The method of claim 17, wherein the tungsten layer is deposited over an aperture having an aspect ratio of about 40:1 or more.
19. The method of claim 11 , wherein the capacitor structure comprises a crown structure.
20. The method of claim 11 , wherein the structure is a trench structure.
21. A three-dimensional capacitor, comprising: a conformal tungsten suicide layer formed over a structure having an opening of about 0.15 μm or less.
22. The capacitor of claim 21 , wherein the structure has an aspect ratio of about 15:1 or more.
23. The capacitor of claim 22, wherein the structure has an aspect ratio of about 20:1 or more.
24. The capacitor of claim 23, wherein the structure has an aspect ratio of about 40:1 or more.
25. The capacitor of claim 21 , wherein the structure comprises a dielectric layer.
26. The capacitor of claim 25, wherein the dielectric layer comprises a high dielectric constant material layer.
27. The capacitor of claim 25, wherein the structure further comprises a rough polysilicon layer, the dielectric layer being formed over the rough polysilicon layer.
28. The capacitor of claim 25, further comprising a polysilicon layer between the dielectric layer and the tungsten suicide layer.
29. The capacitor of claim 21 , wherein the three-dimensional capacitor comprises a trench capacitor.
30. A three-dimensional capacitor, comprising: a rough polysilicon layer; a high dielectric constant material layer formed over the rough polysilicon layer; and a conformal tungsten suicide layer formed over the high dielectric constant material layer.
31. The capacitor of claim 30, further comprising a polysilicon layer between the high dielectric constant material layer and the tungsten suicide layer.
32. The capacitor of claim 30, wherein the three-dimensional capacitor comprises a crown capacitor.
33. The capacitor of claim 30, wherein the three-dimensional capacitor comprises a trench capacitor.
34. A system for processing a substrate, comprising: a first chamber adapted to deposit a polysilicon layer; a second chamber adapted to deposit a tungsten layer by cyclical deposition over the polysilicon layer; and a third chamber adapted to anneal the tungsten layer.
35. The system of claim 34, wherein the third chamber is adapted to anneal the tungsten layer to form a tungsten suicide layer.
36. The system of claim 35, further comprising a fourth chamber adapted to deposit a polysilicon layer over the tungsten suicide layer.
37. The system of claim 35, wherein the first chamber is further adapted to deposit a second polysilicon layer over the tungsten suicide layer.
PCT/US2002/040944 2001-12-27 2002-12-23 Deposition of tungsten for the formation of conformal tungsten silicide WO2003058690A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/033,545 US20030123216A1 (en) 2001-12-27 2001-12-27 Deposition of tungsten for the formation of conformal tungsten silicide
US10/033,545 2001-12-27

Publications (2)

Publication Number Publication Date
WO2003058690A2 true WO2003058690A2 (en) 2003-07-17
WO2003058690A3 WO2003058690A3 (en) 2003-10-30

Family

ID=21871029

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/040944 WO2003058690A2 (en) 2001-12-27 2002-12-23 Deposition of tungsten for the formation of conformal tungsten silicide

Country Status (3)

Country Link
US (1) US20030123216A1 (en)
TW (1) TW200411749A (en)
WO (1) WO2003058690A2 (en)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI119941B (en) * 1999-10-15 2009-05-15 Asm Int A process for preparing nanolaminates
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6475276B1 (en) * 1999-10-15 2002-11-05 Asm Microchemistry Oy Production of elemental thin films using a boron-containing reducing agent
EP1221178A1 (en) 1999-10-15 2002-07-10 ASM America, Inc. Method for depositing nanolaminate thin films on sensitive surfaces
FI20000099A0 (en) 2000-01-18 2000-01-18 Asm Microchemistry Ltd A method for growing thin metal films
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
TW581822B (en) * 2001-07-16 2004-04-01 Applied Materials Inc Formation of composite tungsten films
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
EP1425435A2 (en) * 2001-09-14 2004-06-09 Asm International N.V. Metal nitride deposition by ald using gettering reactant
TW589684B (en) * 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US6911391B2 (en) 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US7279432B2 (en) 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US7398090B2 (en) * 2002-09-13 2008-07-08 Hewlett-Packard Development Company, L.P. Defining a smart area
JP4204840B2 (en) * 2002-10-08 2009-01-07 株式会社日立国際電気 Substrate processing equipment
US6703296B1 (en) * 2003-04-17 2004-03-09 Macronix International Co. Ltd. Method for forming metal salicide
US20040238876A1 (en) * 2003-05-29 2004-12-02 Sunpil Youn Semiconductor structure having low resistance and method of manufacturing same
US7534709B2 (en) * 2003-05-29 2009-05-19 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US6995451B2 (en) * 2003-12-30 2006-02-07 Promos Technologies, Inc. Buried collar trench capacitor formed by LOCOS using self starved ALD nitride as an oxidation mask
US7405143B2 (en) 2004-03-25 2008-07-29 Asm International N.V. Method for fabricating a seed layer
FR2871935A1 (en) * 2004-06-18 2005-12-23 St Microelectronics Crolles 2 INTEGRATED CIRCUIT COMPRISING A METAL ELECRODES CAPACITOR AND METHOD OF MANUFACTURING SUCH CAPACITOR
WO2006019603A2 (en) * 2004-07-30 2006-02-23 Applied Materials, Inc. Thin tungsten silicide layer deposition and gate metal integration
FR2885452A1 (en) * 2005-05-04 2006-11-10 St Microelectronics Sa INTEGRATED CIRCUIT COMPRISING AT LEAST ONE CAPACITOR AND CAPACITOR FORMATION METHOD
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
TWI332532B (en) 2005-11-04 2010-11-01 Applied Materials Inc Apparatus and process for plasma-enhanced atomic layer deposition
US8268409B2 (en) * 2006-10-25 2012-09-18 Asm America, Inc. Plasma-enhanced deposition of metal carbide films
US7611751B2 (en) 2006-11-01 2009-11-03 Asm America, Inc. Vapor deposition of metal carbide films
US7713874B2 (en) * 2007-05-02 2010-05-11 Asm America, Inc. Periodic plasma annealing in an ALD-type process
US20090087550A1 (en) * 2007-09-27 2009-04-02 Tokyo Electron Limited Sequential flow deposition of a tungsten silicide gate electrode film
JP5551681B2 (en) 2008-04-16 2014-07-16 エーエスエム アメリカ インコーポレイテッド Atomic layer deposition of metal carbide films using aluminum hydrocarbon compounds
US7666474B2 (en) 2008-05-07 2010-02-23 Asm America, Inc. Plasma-enhanced pulsed deposition of metal carbide films
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10513772B2 (en) 2009-10-20 2019-12-24 Asm International N.V. Process for passivating dielectric films
US8785310B2 (en) * 2012-01-27 2014-07-22 Tokyo Electron Limited Method of forming conformal metal silicide films
CN113862634A (en) 2012-03-27 2021-12-31 诺发系统公司 Tungsten feature fill
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9412602B2 (en) 2013-03-13 2016-08-09 Asm Ip Holding B.V. Deposition of smooth metal nitride films
US8846550B1 (en) 2013-03-14 2014-09-30 Asm Ip Holding B.V. Silane or borane treatment of metal thin films
US8841182B1 (en) 2013-03-14 2014-09-23 Asm Ip Holding B.V. Silane and borane treatments for titanium carbide films
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9394609B2 (en) 2014-02-13 2016-07-19 Asm Ip Holding B.V. Atomic layer deposition of aluminum fluoride thin films
US10643925B2 (en) 2014-04-17 2020-05-05 Asm Ip Holding B.V. Fluorine-containing conductive films
WO2016046909A1 (en) * 2014-09-24 2016-03-31 株式会社日立国際電気 Method for manufacturing semiconductor device, substrate processing apparatus, semiconductor device and program
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10002936B2 (en) 2014-10-23 2018-06-19 Asm Ip Holding B.V. Titanium aluminum and tantalum aluminum thin films
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9941425B2 (en) 2015-10-16 2018-04-10 Asm Ip Holdings B.V. Photoactive devices and materials
US9786491B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
US9786492B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
KR102378021B1 (en) 2016-05-06 2022-03-23 에이에스엠 아이피 홀딩 비.브이. Formation of SiOC thin films
US10186420B2 (en) 2016-11-29 2019-01-22 Asm Ip Holding B.V. Formation of silicon-containing thin films
US10847529B2 (en) 2017-04-13 2020-11-24 Asm Ip Holding B.V. Substrate processing method and device manufactured by the same
US10504901B2 (en) 2017-04-26 2019-12-10 Asm Ip Holding B.V. Substrate processing method and device manufactured using the same
KR20240010760A (en) 2017-05-05 2024-01-24 에이에스엠 아이피 홀딩 비.브이. Plasma Enhanced Deposition Processes for Controlled Formation of Oxygen Containing Thin Film
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
TWI761636B (en) 2017-12-04 2022-04-21 荷蘭商Ａｓｍ Ｉｐ控股公司 PLASMA ENHANCED ATOMIC LAYER DEPOSITION PROCESS AND METHOD OF DEPOSITING SiOC THIN FILM
SG11202008268RA (en) 2018-03-19 2020-10-29 Applied Materials Inc Methods for depositing coatings on aerospace components
EP3784815A4 (en) 2018-04-27 2021-11-03 Applied Materials, Inc. Protection of components from corrosion
CN112262457A (en) 2018-05-03 2021-01-22 朗姆研究公司 Methods of depositing tungsten and other metals in 3D NAND structures
US11009339B2 (en) 2018-08-23 2021-05-18 Applied Materials, Inc. Measurement of thickness of thermal barrier coatings using 3D imaging and surface subtraction methods for objects with complex geometries
US10636705B1 (en) 2018-11-29 2020-04-28 Applied Materials, Inc. High pressure annealing of metal gate structures
WO2020219332A1 (en) 2019-04-26 2020-10-29 Applied Materials, Inc. Methods of protecting aerospace components against corrosion and oxidation
US11794382B2 (en) 2019-05-16 2023-10-24 Applied Materials, Inc. Methods for depositing anti-coking protective coatings on aerospace components
US11697879B2 (en) 2019-06-14 2023-07-11 Applied Materials, Inc. Methods for depositing sacrificial coatings on aerospace components
US11466364B2 (en) 2019-09-06 2022-10-11 Applied Materials, Inc. Methods for forming protective coatings containing crystallized aluminum oxide
JP7396947B2 (en) * 2020-03-27 2023-12-12 ラピスセミコンダクタ株式会社 Semiconductor device and semiconductor device manufacturing method
US11519066B2 (en) 2020-05-21 2022-12-06 Applied Materials, Inc. Nitride protective coatings on aerospace components and methods for making the same
WO2022005696A1 (en) 2020-07-03 2022-01-06 Applied Materials, Inc. Methods for refurbishing aerospace components

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245206A (en) * 1992-05-12 1993-09-14 International Business Machines Corporation Capacitors with roughened single crystal plates
US5804488A (en) * 1995-08-24 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a tungsten silicide capacitor having a high breakdown voltage
US6218298B1 (en) * 1999-05-19 2001-04-17 Infineon Technologies North America Corp. Tungsten-filled deep trenches

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245206A (en) * 1992-05-12 1993-09-14 International Business Machines Corporation Capacitors with roughened single crystal plates
US5804488A (en) * 1995-08-24 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a tungsten silicide capacitor having a high breakdown voltage
US6218298B1 (en) * 1999-05-19 2001-04-17 Infineon Technologies North America Corp. Tungsten-filled deep trenches

Also Published As

Publication number Publication date
US20030123216A1 (en) 2003-07-03
WO2003058690A3 (en) 2003-10-30
TW200411749A (en) 2004-07-01

Similar Documents

Publication Publication Date Title
US20030123216A1 (en) Deposition of tungsten for the formation of conformal tungsten silicide
KR102636173B1 (en) Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US6797340B2 (en) Method for depositing refractory metal layers employing sequential deposition techniques
US9818885B2 (en) Deposited material and method of formation
US7115499B2 (en) Cyclical deposition of tungsten nitride for metal oxide gate electrode
US8158512B2 (en) Atomic layer deposition method and semiconductor device formed by the same
US7279432B2 (en) System and method for forming an integrated barrier layer
US7745333B2 (en) Methods for depositing tungsten layers employing atomic layer deposition techniques
US8273639B2 (en) Atomic layer deposition method and semiconductor device formed by the same
US20030157760A1 (en) Deposition of tungsten films for dynamic random access memory (DRAM) applications
US7709386B2 (en) Atomic layer deposition method and semiconductor device formed by the same
KR20080101745A (en) Atomic layer deposition of tungsten materials
KR20020068670A (en) Method for forming dielectric layer and capacitor using thereof
US11728160B2 (en) Method of forming oxide film including two non-oxygen elements, method of manufacturing semiconductor device, method of forming dielectric film, and semiconductor device
US7335594B1 (en) Method for manufacturing a memory device having a nanocrystal charge storage region
CN113862635A (en) Method of forming material layer, semiconductor device, and method of manufacturing semiconductor device
CN114080681A (en) Liner for V-NAND word line stack
US7947597B2 (en) Methods of titanium deposition

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR SG

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP