WO2003058722A1 - High voltage power mosfet includes doped columns - Google Patents
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- WO2003058722A1 WO2003058722A1 PCT/US2002/041790 US0241790W WO03058722A1 WO 2003058722 A1 WO2003058722 A1 WO 2003058722A1 US 0241790 W US0241790 W US 0241790W WO 03058722 A1 WO03058722 A1 WO 03058722A1
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- 239000000463 material Substances 0.000 claims abstract description 31
- 239000002019 doping agent Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000945 filler Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 39
- 210000000746 body region Anatomy 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims 6
- 239000004020 conductor Substances 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to semiconductor devices, and more particularly to power MOSFET devices.
- Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state while having a low voltage drop and high current flow in the on-state.
- FIG. 1 illustrates a typical structure for an N-channel power MOSFET.
- An N- epitaxial silicon layer 1 formed over an N+ silicon substrate 2 contains p-body regions 5a and 6a, and N+ source regions 7 and 8 for two MOSFET cells in the device.
- P-body regions 5 and 6 may also include deep p-body regions 5b and 6b.
- a source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions.
- the N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1.
- a drain electrode is provided at the bottom of N+ substrate 2.
- An insulated gate electrode 18 typically of polysilicon lies primarily over the body and portions of the drain of the device, separated from the body and drain by a thin layer of dielectric, often silicon dioxide.
- a channel is formed between the source and drain at the surface of the body region when the appropriate positive voltage is applied to the gate with respect to the source and body electrode.
- the on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1.
- the drift zone resistance is in um determined by the doping and the layer thickness of epitaxial layer 1.
- the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased. Curve 20 in FIG.
- FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance.
- This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683.
- This MOSFET is similar to the conventional MOSFET shown in FIG. 1 except that it includes p-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into the drift region of the device.
- the p-type doped regions 40 and 42 define columns in the drift region that are separated by n-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the p-doped regions 40 and 42.
- the alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well.
- this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone.
- Curve 25 in FIG. 2 shows the on- resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG 3.
- the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1, essentially increasing linearly with the breakdown voltage.
- the improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type. The blocking voltage of the transistor thus remains unaltered.
- the charge compensating columns do not contribute to the current conduction when the device is in its on state.
- FIG. 3 The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant.
- epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture.
- Another technique for fabricating these devices is shown in copending U.S. Appl. Serial No. 09/970,972, in which a trench is successively etched to different depths.
- a dopant material is implanted and diffused through the bottom of the trench after each etching step to form a series of doped regions (so-called "floating islands") that collectively function like the p-type doped regions 40 and 42 seen in FIG. 3.
- the on-resistance of a device that uses the floating island technique is not as low as an identical device that uses continuous columns.
- a method for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate.
- the voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer.
- a barrier material is deposited along the walls of the trench.
- a dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench.
- the trench is etched through the first doped layer.
- a second doped layer is formed in the same manner as the first doped layer.
- the second doped layer is located vertically below the first doped layer.
- a filler material is deposited in the trench to substantially fill the trench.
- the dopant in the first and second doped layers are diffused to cause the first and second doped layers to overlap one another, thus completing the voltage sustaining region.
- at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
- the power semiconductor device formed by the inventive method may be selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a bipolar transistor, and a diode.
- a power semiconductor device in accordance with another aspect of the invention, includes a substrate of a first conductivity type and a voltage sustaining region disposed on the substrate.
- the voltage sustaining region includes an epitaxial layer having a first conductivity type and at least one trench located in the epitaxial layer.
- At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench.
- the column is formed from a plurality of doped layers that are arranged vertically one over the other and which are diffused into one another.
- a filler material is also provided, which substantially fills the trench.
- At least one region of the second conductivity is disposed over the voltage sustaining region to define a junction therebetween.
- FIG. 1 shows a cross-sectional view of a conventional power MOSFET structure.
- FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional power MOSFET.
- FIG. 3 shows a MOSFET structure that includes a voltage sustaining region with columns of p-type dopant located below the body region, which is designed to operate with a lower on-resistance per unit area at the same voltage than the structure depicted in FIG. 1.
- FIGs. 4(a)-4(f) show a sequence of exemplary process steps that may be employed to fabricate a voltage sustaining region constructed in accordance with the present invention.
- a method of forming the p-type columns in the voltage sustaining layer of a semiconductor power device may be generally described as follows. First, one or more trenches are etched in the epitaxial layer that is to form the voltage sustaining region of the device. Each trench is centered where a doped column is to be located. A first doped section of the column is formed by implanting p-type dopant material into the bottom of the trench. The implanted material is diffused into the portion of the voltage sustaining region located immediately adjacent to and below the trench bottom. The trenches are subsequently etched to a greater depth so that a second doped section of the column is formed by again implanting and diffusing a p-type dopant material.
- the aforementioned process is repeated until the desired number of vertically arranged segments of each column have been formed.
- the trenches are filled with a material that does not adversely affect the characteristics of the device.
- Exemplary materials that may be used for the material filling the trenches include highly resistive polysilicon, a dielectric such as silicon dioxide, or other materials and combinations of materials.
- a thermal diffusion step is performed to cause adjacent doped section to overlap one another, thus forming a continous doped column of the type depicted in FIG. 3.
- the power semiconductor device shown in FIG. 3 may be fabricated in accordance with the following exemplary steps, which are illustrated in FIGS. 4(a)-4(f).
- the N-type doped epitaxial layer 501 is grown on a conventionally N+ doped substrate 502.
- Epitaxial layer 501 is typically 15-50 microns in thickness for a 400-800 V device with a resistivity of 5-40 ohm-cm.
- a dielectric masking layer is formed by covering the surface of epitaxial layer 501 with a dielectric layer, which is then conventionally exposed and patterned to leave a mask portion that defines the location of the trench 520.
- the trench 520 is dry etched through the mask openings by reactive ion etching to an initial depth that may range, for example, from 5-15 microns.
- the trench depth should be selected so that after the final diffusion step is performed at the end of the fabrication process the different doped sections will overlap adjacent doped sections.
- the trench depths, dopant dose and the magnitude and duration of the diffusion process should be selected to achieve the desired charge compensation.
- the sidewalls of each trench may be smoothed, if needed.
- a dry chemical etch may be used to remove a thin layer of oxide (typically about 500 - 1000 A) from the trench sidewalls to eliminate damage caused by the reactive ion etching process.
- a sacrificial silicon dioxide layer is grown over the trench 520. The sacrificial layer is removed either by a buffer oxide etch or an HF etch so that the resulting trench sidewalls are as smooth as possible.
- a layer of silicon dioxide 524 is grown in trench 520.
- the thickness of the silicon dioxide layer 524 should be sufficient to prevent implanted atoms from penetrating the silicon adjacent to and below the sidewalls of the trench 520, while allowing the implanted atoms to penetrate the oxide layer 524 at the bottom of the trench 520 so that they can be deposited into the silicon adjacent and beneath the trench bottom.
- a dopant 528 such as boron is implanted through the oxide layer at the bottom of the trench 520.
- the total dose of dopant and the implant energy should be chosen such that the amount of dopant left in the epitaxial layer 501 after the subsequent diffusion and etching steps are performed satisfies the breakdown requirements of the resulting device.
- a high temperature diffusion step is performed to "drive-in" the implanted dopant 528 both vertically and laterally.
- Oxide layer 524 is removed from the bottom of the trench 520.
- the oxide layer 524 may or may not be removed from the sidewalls of the trench 520.
- the depth of the trench 520 is increased by an amount no greater than that which will allow the subsequently formed doped sections to overlap one another after the final diffusion step is performed at the end of the fabrication process.
- a second doped segment of the column is fabricated by repeating the steps of growing an oxide layer on the trench walls, implanting and diffusing dopant through the bottom of the trench, and removing the oxide layer from the bottom of the trench. This process can be repeated as many times as necessary to form the appropriate number of doped segments to provide the desired breakdown voltage. For example, in FIG. 4(d), four such doped segments 528, 530, 532, and 534 are shown. As seen in FIG.
- the trench etching process is complete prior to the formation of the final doped segment 534.
- the trench may undergo another etch step to etch through the final doped segment 534, ensuring that the proper total charge dosage and overlap of the doped segments is achieved.
- the trench 520 is filled with a material that does not adversely affect the characteristics of the device.
- exemplary materials include, but are not limited to, thermally grown silicon dioxide, a deposited dielectric such as silicon dioxide, silicon nitride, or a combination of thermally grown and deposited layers of these or other materials, high resistivity single crystal silicon, high resistivity polysilicon, or a sandwich of thermal oxide, a deposited dielectric and high resistivity polysilicon.
- the trench may also be filled with sedimented glass, either by itself in combination with any one or more of the aforementioned materials. If high resistivity polysilicon is employed, it may be converted to single crystal silicon using a recrystallization procedure such as a high temperature anneal step.
- FIGs. 4f(i) and 4f(ii) after planarizing the surface of the structure, the structure undergoes a high temperature diffusion step to cause the doped segments to overlap so that a continuous doped column 540 is formed.
- the aforementioned sequence of processing steps resulting in the structures depicted in FIG. 4f(i) and 4f(ii) provides a voltage sustaining layer with p-type doped columns on which any of a number of different power semiconductor devices can be fabricated.
- power semiconductor devices include vertical DMOS, V-groove DMOS, and trench DMOS MOSFETs, IGBTs and other MOS-gated devices. For instance, FIG.
- FIG. 3 shows an example of a MOSFET that includes a voltage sustaining layer with doped columns constructed in accordance with the principles of the present invention. It should be noted that while FIG. 4 shows a single trench that is used to form the doped column, the present invention encompasses a voltage sustaining regions having single or multiple trenches to form any number of doped columns. For example, a doped column or columns may be located below the center of the gate or in other locations when appropriate to decrease the on-resistance of the device. [0027] Once the voltage sustaining region and the doped column or columns have been formed as shown in FIG. 4, the MOSFET shown in FIG. 3 can be completed in the following manner. The gate oxide is grown after an active region mask is formed.
- a layer of polycrystalline silicon is deposited, doped, and oxidized.
- the polysilcon layer is then masked to form the gate regions.
- the p+ doped deep body regions 5b and 6b are formed using conventional masking, implantation and diffusion steps.
- the p+-doped deep body regions are boron implanted at 20 to 200 KeV with a dosage from about lxlO 14 to 5xl0 15 / cm 2 .
- the shallow body regions 5a and 6a are formed in a similar fashion.
- the implant dose for this region will be lxlO 13 to 5xl0 14 /cm 2 at an energy of 20 to 100 KeV.
- Source regions 7 and 8 are then formed by an implantation and diffusion process.
- the source regions may be implanted with arsenic at 20 to 100 KeV to a concentration that is typically in the range of 2x10* 5 to
- the arsenic is diffused to a depth of approximately 0.5 to 2.0 microns.
- the depth of the body region typically ranges from about 1-3 microns, with the P+ doped deep body region (if present) being slightly deeper.
- the DMOS transistor is completed in a conventional manner by etching the oxide layer to form contact openings on the front surface.
- a metallization layer is also deposited and masked to define the source-body and gate electrodes.
- a pad mask is used to define pad contacts.
- a drain contact layer is formed on the bottom surface of the substrate.
- the deep p+ doped body region may be formed before the gate region is defined. It is also possible to form the deep p+ doped body region prior to forming the trenches. In some DMOS structures, the P+ doped deep body region may be shallower than the P-doped body region, or in some cases, there may not even be a P+ doped body region.
- a power semiconductor device in accordance with the present invention may be provided in which the conductivities of the various semiconductor regions are reversed from those described herein.
- a vertical DMOS transistor has been used to illustrate exemplary steps required to fabricate a device in accordance with the present invention
- other DMOS FETs and other power semiconductor devices such as diodes, bipolar transistors, power JFETs, IGBTs, MCTs, and other MOS-gated power devices may also be fabricated following these teachings.
Abstract
Description
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2003558933A JP4741187B2 (en) | 2001-12-31 | 2002-12-30 | High voltage power MOSFET including doped column |
EP02799348.4A EP1468452B1 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet includes doped columns |
KR1020047010417A KR100990294B1 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet includes doped columns |
AU2002364365A AU2002364365A1 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet includes doped columns |
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US10/038,845 | 2001-12-31 | ||
US10/038,845 US6656797B2 (en) | 2001-12-31 | 2001-12-31 | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation |
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WO2003058722A1 true WO2003058722A1 (en) | 2003-07-17 |
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PCT/US2002/041790 WO2003058722A1 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet includes doped columns |
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EP (1) | EP1468452B1 (en) |
JP (1) | JP4741187B2 (en) |
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CN (1) | CN100342544C (en) |
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EP1468452A4 (en) | 2009-01-07 |
EP1468452B1 (en) | 2018-10-10 |
US7091552B2 (en) | 2006-08-15 |
CN1610973A (en) | 2005-04-27 |
US20040110333A1 (en) | 2004-06-10 |
US6656797B2 (en) | 2003-12-02 |
CN100342544C (en) | 2007-10-10 |
KR20040071773A (en) | 2004-08-12 |
AU2002364365A1 (en) | 2003-07-24 |
US20030122188A1 (en) | 2003-07-03 |
JP4741187B2 (en) | 2011-08-03 |
JP2005514794A (en) | 2005-05-19 |
KR100990294B1 (en) | 2010-10-26 |
TWI263282B (en) | 2006-10-01 |
EP1468452A1 (en) | 2004-10-20 |
TW200301525A (en) | 2003-07-01 |
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