WO2003065440A1 - Method to arrange silicon structures on top of each other and arrangement herefor - Google Patents

Method to arrange silicon structures on top of each other and arrangement herefor Download PDF

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Publication number
WO2003065440A1
WO2003065440A1 PCT/SE2003/000119 SE0300119W WO03065440A1 WO 2003065440 A1 WO2003065440 A1 WO 2003065440A1 SE 0300119 W SE0300119 W SE 0300119W WO 03065440 A1 WO03065440 A1 WO 03065440A1
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WIPO (PCT)
Prior art keywords
silicon
intermediate layer
silicon substrates
silicon substrate
substrates
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Application number
PCT/SE2003/000119
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French (fr)
Inventor
Björn EKSTRÖM
Original Assignee
Strand Interconnect Ab
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Publication of WO2003065440A1 publication Critical patent/WO2003065440A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H01L23/4926—Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/043—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a method of stacking silicon structures and also to a device for this purpose.
  • HDMI High Density Interconnect
  • MCM Multi Chip Modules
  • 3D Packaging three dimensional packaging
  • the conventional technique for 3D packaging of silicon substrates i.e. silicon plates that carry one or more electronic circuits, either involves an intermediate layer of an organic material between the silicon substrates, said intermediate layer being poorly adapted to the coefficient of linear thermal expansion of the silicon substrates.
  • organic intermediate layers carry a low density of conductors, or no conductors at all. This solution also results in poor impedance matching between the circuits, which, in turn, results in poor signal matching.
  • So-called PCB board (Printed Circuit Boards) also include a number of superposed electrically conductive layers, which can be connected to each other by means of vias. Such boards are, however, expensive.
  • the present invention provides a solution to these problems and makes significant advances in the endeavour to produce small multicircuit units with a high degree of integration.
  • the present invention relates to a method of mutually superposing silicon structures which include an intermediate layer between two mutually adjacent silicon structures, and is characterised by the steps of providing said intermediate layer in the form of a silicon substrate, by providing said silicon substrate with a pattern of conductors, and by connecting the silicon substrates on both sides of an intermediate layer by virtue of connecting respective silicon structures with the conductor pattern of the intermediate layer.
  • the invention also relates to an arrangement of the kind defined in Claim 7 and having the principle features set forth therein.
  • FIG. 2 illustrates an example of a module in which the present invention is applied
  • FIG. 3 is a perspective, partially cut-away view of a module according to Figure 2; and - Figure 4 is a schematic sectional view of a lead frame package that includes a mounting plate.
  • Figure 1 is an illustration of known technology where two silicon substrates 21, 22 are superposed on a PCB board 23. Connection points 24 on the board and on the substrates are connected to one another by bond wires 25, 26. It will be evident that certain bond wires will be extremely long, resulting in impaired signal quality.
  • FIG. 2 illustrates a 3D-packaged module in accordance with the invention.
  • This module includes an electronic circuit in the form of a bottom silicon substrate 3, which rests on a BGA laminate 4.
  • a top silicon substrate 6 that includes an electronic circuit.
  • an intermediate layer 2 Located between these silicon substrates is an intermediate layer 2, which may have the form of a silicon substrate in accordance with the present invention.
  • the silicon substrate 2 is provided with a conductor pattern 1.
  • the silicon substrates 3, 6 on respective sides of the intermediate layer 2 are interconnected by virtue of being connected to the conductor pattern 1 of the intermediate layer 2.
  • the silicon substrates may contain processors, memories, different types of chips, etc.
  • the bottom silicon substrate 3 in a substrate pile 3, 6 is in abutment with a terminal-carrying board 4.
  • said board is a so called PCB board 4.
  • the printed circuit board 4 is provided with terminals in the form of so called BGA balls 12 which are connected to electrically conductive layers and connection points 8 by means of vias routed in the printed circuit board 4, on that side of said PCB board with which the silicon substrate 3 is in abutment.
  • the numeral 8 identifies connection points on the BGA laminate 4
  • the numeral 9 identifies connection points on the bottom silicon substrate 3
  • the numeral 10 identifies connection points on the intermediate layer 2
  • the numeral 11 identifies connection points on the top silicon substrate.
  • the numeral 12 identifies the BGA balls.
  • the numeral 7 identifies a moulded plastic top cover.
  • connection between the silicon substrates 3, 6 and the intermediate layer 1 is effected with the aid of so called bond wires 5 routed between relevant connection points 9, 10, 11.
  • the signals from a mother board not shown are applied to the bottom silicon substrate 3 via the BGA balls, and to the connection points 8 through vias in the BGA laminate.
  • Bond wires 5 are routed from the connection points 8 to the points 9 on the bottom silicon substrate 3.
  • Bond wires 5 extend from the points 9 on the bottom silicon substrate 3 to a connection point 10 on the intermediate layer 1.
  • the left-hand point 10 in Figure 2 is connected to the right-hand point 10 in said figure via a conductor network formed on the intermediate layer 1 by means of thin film technique ' .
  • the right-hand point 10 is connected to the point 11 on the top silicon substrate 6 by means of a bond wire 5.
  • a corresponding connection between the BGA laminate and the two silicon substrates is shown to the right in Figure 2. It is pointed out that the connections in Figure 2 illustrate solely how the connection is achieved. Many connections may be included.
  • Figure 2 illustrates the technique of connecting silicon substrates together through the medium of an intermediate layer 1 provided with a conductor pattern.
  • the dimensions of the silicon substrates 3,6 in a stack of silicon substrates 3, 6 with intermediate layers 1 are caused to be smaller with the increase in the height of the stack from the board 4 on which the silicon substrate is located, where the dimensions of the intermediate layers 1 are caused to lie between the dimensions of respective top and bottom silicon substrates that sandwich said intermediate layer, so as to enable said intermediate layers 1 to be provided with connection points 8 on the free surface of the intermediate layers.
  • Figure 2 shows only two silicon substrates, it will be understood that a plurality of silicon substrates with intermediate layers therebetween can be stacked one upon the other, where each intermediate layer has a free surface on which connection points are found.
  • intermediate layers provided with conductor patterns results in bond wires that are shorter than those used with conventional techniques. This enhances signal quality, due to the fact that the bond wires are unable to emit and take-up electromagnetic waves equally as readily as when they are longer. Because the intermediate layer is comprised of silicon, it has the same coefficient of linear expansion as the circuits or silicon substrates, therewith avoiding mechanical-thermic stresses. Moreover, the intermediate layer is electrically insulating.
  • the intermediate layers provided with conductor patterns in accordance with the invention can also be produced and mounted relatively cheaply with the aid of those techniques used to produce the silicon substrates.
  • Figure 4 illustrates a module in the form of a capsule that includes a lead frame and a mounting plate and in which the invention has been applied.
  • the module is ready for connection, e.g., to a motherboard.
  • the numeral 13 identifies existing intermediate layers
  • the numeral 14 identifies the bottom silicon substrate
  • the numeral 15 illustrates the top silicon substratet
  • the numeral 16 illustrates the mounting plate (lead frame paddle) which, e.g., is a copper plate or some other appropriate plate or board
  • the numeral 17 identifies terminals
  • the numeral 18 identifies a moulded plastic cap.
  • the numeral 19 identifies bond wires and the numeral 20 identifies the conductor pattern on the intermediate layer.

Abstract

A method of superposing silicon structures with an intermediate layer between two mutually adjacent silicon structures. The invention is characterised by using a silicon substrate as the intermediate layer (2) and by providing the silicon substrate with a conductor pattern (1) and by connecting the silicon substrates (3, 6) on both sides of an intermediate layer (2) to the conductor pattern (1) on the intermediate layer (2).

Description

METHOD TO ARRANGE SILICON STRUCTURES ON TOP OF EACH OTHER
AND ARRANGEMENT HEREFOR
The present invention relates to a method of stacking silicon structures and also to a device for this purpose.
Developments in the electronic industry constantly place higher demands on the integration of components and circuits. Demands for smaller electronic elements and enhancement of their performances are also increasing. This means, among other things, that the thermal conditions become more difficult to resolve with each new generation of circuits. Such electronic elements are also expected to cost less.
High Density Interconnect (HDI) technology, Multi Chip Modules (MCM) and three dimensional packaging (3D Packaging) are important techniques in achieving smaller units, since complexity and the number of terminals increases concurrently with the successive increase in frequencies.
As an example of applications in which highly complex small units are desired can be mentioned different types of portable units, such as handheld computers and mobile telephones.
The conventional technique for 3D packaging of silicon substrates, i.e. silicon plates that carry one or more electronic circuits, either involves an intermediate layer of an organic material between the silicon substrates, said intermediate layer being poorly adapted to the coefficient of linear thermal expansion of the silicon substrates. Moreover, organic intermediate layers carry a low density of conductors, or no conductors at all. This solution also results in poor impedance matching between the circuits, which, in turn, results in poor signal matching.
An alternative solution is to lay the circuits directly one upon the other, in the absence of an intermediate layer. This results in long bond wires used to connect the circuits together and, to terminals. The resultant signal quality is thus very poor, at the same time as problems concerning reliability occur. The necessary conductor layout to terminals, such as so called BGA balls ( Ball Grid Arrays), is therewith effected in the laminate on which the BGA balls are located. Such a laminate is referred to as a BGA laminate.
So-called PCB board (Printed Circuit Boards) also include a number of superposed electrically conductive layers, which can be connected to each other by means of vias. Such boards are, however, expensive.
The present invention provides a solution to these problems and makes significant advances in the endeavour to produce small multicircuit units with a high degree of integration.
Accordingly, the present invention relates to a method of mutually superposing silicon structures which include an intermediate layer between two mutually adjacent silicon structures, and is characterised by the steps of providing said intermediate layer in the form of a silicon substrate, by providing said silicon substrate with a pattern of conductors, and by connecting the silicon substrates on both sides of an intermediate layer by virtue of connecting respective silicon structures with the conductor pattern of the intermediate layer.
The invention also relates to an arrangement of the kind defined in Claim 7 and having the principle features set forth therein.
The invention will now be described partially with reference to an exemplifying embodiment of the invention shown in the accompanying drawings, in which Figure 1 illustrates an example of a conventional technique;
- Figure 2 illustrates an example of a module in which the present invention is applied;
- Figure 3 is a perspective, partially cut-away view of a module according to Figure 2; and - Figure 4 is a schematic sectional view of a lead frame package that includes a mounting plate.
Figure 1 is an illustration of known technology where two silicon substrates 21, 22 are superposed on a PCB board 23. Connection points 24 on the board and on the substrates are connected to one another by bond wires 25, 26. It will be evident that certain bond wires will be extremely long, resulting in impaired signal quality.
Figure 2 illustrates a 3D-packaged module in accordance with the invention. This module includes an electronic circuit in the form of a bottom silicon substrate 3, which rests on a BGA laminate 4. Located above the bottom silicon substrate or circuit 3 is a top silicon substrate 6 that includes an electronic circuit. Located between these silicon substrates is an intermediate layer 2, which may have the form of a silicon substrate in accordance with the present invention. The silicon substrate 2 is provided with a conductor pattern 1. The silicon substrates 3, 6 on respective sides of the intermediate layer 2 are interconnected by virtue of being connected to the conductor pattern 1 of the intermediate layer 2.
The silicon substrates may contain processors, memories, different types of chips, etc.
It is preferred that the bottom silicon substrate 3 in a substrate pile 3, 6 is in abutment with a terminal-carrying board 4.
It is also preferred that said board is a so called PCB board 4.
According to one preferred embodiment, the printed circuit board 4 is provided with terminals in the form of so called BGA balls 12 which are connected to electrically conductive layers and connection points 8 by means of vias routed in the printed circuit board 4, on that side of said PCB board with which the silicon substrate 3 is in abutment.
In Figure 2, the numeral 8 identifies connection points on the BGA laminate 4, the numeral 9 identifies connection points on the bottom silicon substrate 3, the numeral 10 identifies connection points on the intermediate layer 2, and the numeral 11 identifies connection points on the top silicon substrate. The numeral 12 identifies the BGA balls. The numeral 7 identifies a moulded plastic top cover.
The connection between the silicon substrates 3, 6 and the intermediate layer 1 is effected with the aid of so called bond wires 5 routed between relevant connection points 9, 10, 11. Referring to Figure 2, the signals from a mother board not shown are applied to the bottom silicon substrate 3 via the BGA balls, and to the connection points 8 through vias in the BGA laminate. Bond wires 5 are routed from the connection points 8 to the points 9 on the bottom silicon substrate 3. Bond wires 5 extend from the points 9 on the bottom silicon substrate 3 to a connection point 10 on the intermediate layer 1. The left-hand point 10 in Figure 2 is connected to the right-hand point 10 in said figure via a conductor network formed on the intermediate layer 1 by means of thin film technique'.
The right-hand point 10 is connected to the point 11 on the top silicon substrate 6 by means of a bond wire 5. A corresponding connection between the BGA laminate and the two silicon substrates is shown to the right in Figure 2. It is pointed out that the connections in Figure 2 illustrate solely how the connection is achieved. Many connections may be included.
Thus, Figure 2 illustrates the technique of connecting silicon substrates together through the medium of an intermediate layer 1 provided with a conductor pattern.
According to a highly preferred embodiment, the dimensions of the silicon substrates 3,6 in a stack of silicon substrates 3, 6 with intermediate layers 1 are caused to be smaller with the increase in the height of the stack from the board 4 on which the silicon substrate is located, where the dimensions of the intermediate layers 1 are caused to lie between the dimensions of respective top and bottom silicon substrates that sandwich said intermediate layer, so as to enable said intermediate layers 1 to be provided with connection points 8 on the free surface of the intermediate layers.
Although Figure 2 shows only two silicon substrates, it will be understood that a plurality of silicon substrates with intermediate layers therebetween can be stacked one upon the other, where each intermediate layer has a free surface on which connection points are found.
The use of intermediate layers provided with conductor patterns results in bond wires that are shorter than those used with conventional techniques. This enhances signal quality, due to the fact that the bond wires are unable to emit and take-up electromagnetic waves equally as readily as when they are longer. Because the intermediate layer is comprised of silicon, it has the same coefficient of linear expansion as the circuits or silicon substrates, therewith avoiding mechanical-thermic stresses. Moreover, the intermediate layer is electrically insulating.
The intermediate layers provided with conductor patterns in accordance with the invention can also be produced and mounted relatively cheaply with the aid of those techniques used to produce the silicon substrates.
Figure 4 illustrates a module in the form of a capsule that includes a lead frame and a mounting plate and in which the invention has been applied. The module is ready for connection, e.g., to a motherboard. In Figure 4, the numeral 13 identifies existing intermediate layers, the numeral 14 identifies the bottom silicon substrate, the numeral 15 illustrates the top silicon substratet, the numeral 16 illustrates the mounting plate (lead frame paddle) which, e.g., is a copper plate or some other appropriate plate or board, the numeral 17 identifies terminals, and the numeral 18 identifies a moulded plastic cap. In Figure 3, the numeral 19 identifies bond wires and the numeral 20 identifies the conductor pattern on the intermediate layer.
It will be obvious that the present invention can be applied in a great number of different electronic devices, such as handheld computers, mobile telephones, GPS receivers, digital cameras, automobile electronics, etc.
Although the invention has been described with reference to a number of exemplifying embodiments thereof, it will be obvious to the person skilled in this art that the intermediate layer and its conductor pattern must be adapted to the silicon substrate concerned.
It will therefore be understood that the present invention is not restricted to the aforesaid exemplifying embodiments, but that variations can be made within the scope of the accompanying Claims.

Claims

1 A method of arranging silicon structures (circuits) in superposed relationship, with an intermediate layer located between two mutually adjacent silicon structures, characterised by causing the intermediate layer (2) to be a silicon substrate, by providing the silicon disc with a conductor pattern (1), and by connecting the silicon substrates (3, 6) on both sides of an intermediate layer (2) to the conductor pattern (1) of said intermediate layer (2)
2 A method according to Claim 1, characterised by causing the lowermost silicon substrate (3) of a stack of silicon substrates to abut a mounting pad (4)
3 A method according to Claim 1 or 2, characterised by causing the dimensions of the silicon substrates in a stack of substrate (3, 6) with intermediate layers (2) therebetween to become smaller the higher the silicon substrate is located from said pad, and by causing the dimensions of the intermediate layers (2) to lie between the dimensions of two surrounding silicon substrates (3, 6) such as to enable the intermediate layers to be provided with connection points (10) on the free surface of respective intermediate layers (2)
4 A method according to Claim 2 or 3, characterised in that said mounting pad is a terminal-carrying board (4)
5 A method according to Claim 2, 3 or 4, characterised in that the mounting pad is a printed circuit board (4) provided with so called BGA balls (12) which are connected to electrically conductive layers and connection points (8) on that side of the printed circuit board (4) with which a silicon substrate (3) abuts by means of vias routed in the printed circuit board
6 A method according to Claim 1, 2, 3, 4 or 5, characterised by effecting said connection between the silicon substrates and the intermediate layer by means of so called bond wires (5)
7 An arrangement for mutually superimposing silicon structures with an intermediate layer between two mutually adjacent silicon structures, characterised in that the intermediate layer (2) is a silicon substrate; in that the silicon disc includes a conductor pattern (1); and in that the silicon substrates (3, 6) on respective sides of an intermediate layer (2) are connected to the conductor pattern (1) of the intermediate layer.
8. An arrangement according to Claim 7, characterised in that the lowermost silicon substrate (3) of a stack of silicon substrates (3, 6) is in abutment with a mounting pad (4).
9. An arrangement according to Claim 7 or 8, characterised in that the dimensions of respective silicon substrates in a stack of silicon substrates (3, 6) with intermediate layers (2) therebetween are smaller the higher the silicon substrate is located from said board; and in that the dimensions of the intermediate layers (2) lie between the dimensions of two surrounding silicon substrates (3, 6) so that the intermediate layers may have connection points (10) on the free surface of the intermediate layers (2).
10. An arrangement according to Claim 8 or 9, characterised in that said mounting pad (4) is a terminal-carrying board.
11. . An arrangement according to Claim 8, 9 or 10, characterised in that said mounting pad is a PCB board (4) provided with so called BGA balls (12) which are connected to electrically conductive layers and connection points (8) on that side of the PCB board with which a silicon substrate (3) abuts, through the medium of vias routed in said printed circuit board.
12. An arrangement according to Claim 7, 8, 9, 10 or 11, characterised in that the connection between the silicon substrates (3, 6) and the intermediate layer (2) is achieved with so called bond wires (5).
PCT/SE2003/000119 2002-02-01 2003-01-23 Method to arrange silicon structures on top of each other and arrangement herefor WO2003065440A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0200297-0 2002-02-01
SE0200297A SE0200297L (en) 2002-02-01 2002-02-01 Method for arranging silicon structures on top of each other and apparatus therefor

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768108A (en) * 1993-03-11 1998-06-16 Hitachi, Ltd. Multi-layer wiring structure
US6239495B1 (en) * 1998-07-29 2001-05-29 Kabushiki Kaisha Toshiba Multichip semiconductor device and memory card
US20010005046A1 (en) * 1999-01-14 2001-06-28 Hsuan Min Chih Direct contact through hole type wafer structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768108A (en) * 1993-03-11 1998-06-16 Hitachi, Ltd. Multi-layer wiring structure
US6239495B1 (en) * 1998-07-29 2001-05-29 Kabushiki Kaisha Toshiba Multichip semiconductor device and memory card
US20010005046A1 (en) * 1999-01-14 2001-06-28 Hsuan Min Chih Direct contact through hole type wafer structure

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SE0200297L (en) 2003-08-02
SE0200297D0 (en) 2002-02-01

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