WO2003065454A2 - Split-gate power module and method for suppressing oscillation therein - Google Patents
Split-gate power module and method for suppressing oscillation therein Download PDFInfo
- Publication number
- WO2003065454A2 WO2003065454A2 PCT/US2003/002326 US0302326W WO03065454A2 WO 2003065454 A2 WO2003065454 A2 WO 2003065454A2 US 0302326 W US0302326 W US 0302326W WO 03065454 A2 WO03065454 A2 WO 03065454A2
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- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Definitions
- the present invention relates to power modules containing plural transistor dies providing a single external gate terminal. More particularly, it concerns a power module that operates at a first frequency without oscillation at a second higher frequency that is below a cutoff frequency of the transistors.
- FIGs. 1 and 2 illustrate two such prior art configurations, Fig. 1 illustrating a device known as the SGS Thompson TH430 and Fig. 2 illustrating a device known as the Toshiba TPM1919.
- the SGS Thompson TH430 shown in Fig. 1 is a four-die bipolar device incorporating a center base feed with the emitters on the outside of the rectangular array. There is no provision in this design for equalizing the path length from the base terminal to the individual die bases. It is believed that the upper frequency of the die, referred to herein as the cutoff frequency of the transistors, is close to the 50MHz upper frequency limit of the four-die device.
- the Toshiba TPM1919 shown in Fig. 2 is a 2GHz device having four MESFET dies in a linear array. It uses an "echelon" divider structure to divide the gate signal four ways. There are matching networks between the gate connections and the ends of the divider structure. It is believed that these matching networks provide impedance transformation at the intended frequency of operation which facilitates implementation of the device.
- the device's input structure provides certain balancing and isolation functions. Its frequency of operation is believed to be near the upper limit of the individual dies. Accordingly, the known prior art devices operate at the top end of the dies' frequency capability.
- the prior art gate and/or base wires are necessarily short because of the very high frequencies involved. As a result, their parasitic resonant (and potential oscillation) frequency is higher than the frequency at which the dies run out of gain. Thus, there is little or no oscillation.
- the Motorola design MRF 154 (FIG. 2') is described in U.S. Patent No. 4,639,760 uses series gate resistors to intentionally substantially reduce the gain of the individual gate cells to substantially prevent oscillation.
- the die has gain response to >500 MHz, but the intended frequency range of the total device was ⁇ 100 MHz. Thus, the Motorola design has excess gain.
- the invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors.
- the method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.
- the leads are sized to substantially the same electrical length and provide a first impedance corresponding to said electrical length from the common area to each gate that will pass the first frequency substantially unattenuated and providing a second impedance from the gate of one die to the gate of a second die that will substantially attenuate the second frequency.
- the leads take the form of one or more jumper wires in series with a film resistor.
- they take the form of one or more meandering striplines having predefined impedance characteristics and one or more gate bonding pads connected to their respective gates with long jumper wires.
- FIG. 4 is a schematic diagram of a second embodiment of the present invention.
- FIG. 5 is a more detailed schematic diagram of the gate structure of the embodiment shown in FIG. 3.
- FIG. 6 is a more detailed schematic diagram of the gate structure of the embodiment shown in FIG. 4.
- the input capacitance of the transistors in accordance with the invention, is high. This high capacitance lowers the resonant frequency of the parasitic structure of the transistors, which can cause oscillation when the transistors are coupled in parallel in a power module. Because of the higher input capacitance and the use of source resistors, in accordance with a first embodiment of the invention, the gain at the intended frequency of operation is not very high to begin with.
- a second embodiment of the invention utilizes gate inductors instead of gate resistors, and provides higher gain without oscillation.
- Fig. 3 illustrates a first embodiment of the invention having balanced gate input connections that utilize printed series resistors.
- a relatively lower gain amplifier is obtained, but one that performs without undesirable oscillation.
- smaller dies having greater gain may be used so that the series resistors do not consume most of the gain margin at the desired operating frequency.
- Fig. 3 shows the four-die (each labeled 1) array mounted on a preferably ceramic (e.g. BeO) substrate 2 providing a conductive source connection area 3, a conductive drain connection area 4 and a conductive gate connection area 5.
- Thin- film source resistors 6 e.g. palladium gold
- Gate bond wires 7 and source bond wires 8 e.g. aluminum
- source bond pads 9 e.g. silver
- Jumper wires 10 e.g. aluminum
- the far ends of gate resistors 13 are wire bonded by gate bond wires 7 to plural corresponding gate connections on each of the dies 1.
- Fig. 4 shows a second embodiment of the invention having balanced gate input connections that utilize printed meandering striplines or stripline connection lines 11 exhibiting a relatively high intrinsic inductance. Because the impedance of the inductive striplines is frequency-dependent (unlike that of the resistors, which is frequency-independent), it is possible to achieve higher gain without oscillation in this second embodiment of the invention. It will be appreciated that the layout topology of the second embodiment is like that of the first: the gates' first off-die connection is to be in a common interior central location therein. Those of skill in the art will appreciate that the striplines also intrinsically have a characteristic resistance and capacitance, however low.
- the meandering striplines are of substantially equal electrical length, i.e. they exhibit nearly identical impedances (including . resistance, inductance and capacitance), and extend from an external gate terminal 5' through jumper wires 10 to a central common landing region L' within the die array and between adjacent dies.
- the meandering inductors terminate in gate bonding pads 12' for wire bonding using gate bond wires 7' to the plural corresponding gate pads on each of the dies 1.
- substrate 2, source connection area 3, drain connection area 4, source resistors 6, source bond wires 8 and source bond pads 9 are substantially identical to those of the first embodiment of the invention described above relative to Fig. 3.
- Fig. 5 is a detailed schematic diagram showing only the gate connection area of the device of Fig. 3.
- Fig. 5 features the above-described gate connection 5 for the device and bond wires 7. It also shows second (central) gate connection bond wires 10 (six in accordance with the first embodiment shown) providing a controlled-impedance (e.g. resistive/inductive/capacitive) path between gate connection 5 and the centrally located gate landing L. It further shows the gate bonding pads 12 (one per die). Finally, it shows preferably printed circuit resistors 13 (also one per die).
- the number of jumper wires 10 and their lengths may be adjusted to achieve desired inductance, resistance and current capacity for a given application.
- the gate series resistors are approximately 3 ⁇ or less. Those of skill in the art will appreciate that the series resistance value is selected to effectively suppress oscillation at a given operating frequency of the device, while not reducing the overall gain of the device more than is necessary. Also, as illustrated in the preferred first embodiment, the six thin jumper wires 10 are arranged in parallel.
- Fig. 6 is a detailed schematic diagram showing only the gate connection area of the device of Fig. 4.
- the second embodiment of the invention omits the gate series resistors 13, reconfigures the gate bonding pads 12' to a smaller footprint, and incorporates four controlled-impedance stripline connection lines 11 extending as shown between a common central landing L' and bonding pads 12'.
- the landing L' may be seen to be connected to the gate connection 5' via six parallel jumper wires 10, as in Figs. 3 and 5.
- the typical characteristic impedance of the controlled-impedance striplines- -compatible with the selected dies- is approximately 90 ⁇ , as determined by their width and the thickness and dielectric properties of the substrate 2.
- the striplines are approximately 0.65 inch long and 0.013 inch wide, while the substrate is approximately 40 mils thick.
- the input impedance of the dies 1 themselves is less than approximately 0.2 ⁇ .
- striplines may be differently characterized, formed and/or routed, within the spirit and scope of the invention.
- a rectangular array of four-die is represented.
- Other geometric arrangements, circular, triangular, etc., with more or less die could also be used with the method described, and are within the spirit and scope of the invention. Accordingly, having illustrated and described the principles of our invention in a preferred embodiment thereof, it should be readily apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications coming within the spirit and scope of the accompanying claims.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003564937A JP4732692B2 (en) | 2002-01-29 | 2003-01-27 | Power module and manufacturing method thereof |
KR10-2004-7011632A KR20040085169A (en) | 2002-01-29 | 2003-01-27 | Split-gate power module and method for suppressing oscillation therein |
DE60308148T DE60308148T2 (en) | 2002-01-29 | 2003-01-27 | POWER MODULE WITH PARTITIONED GATE AND METHOD FOR SUPPRESSING VIBRATIONS THEREIN |
EP03705914A EP1470588B1 (en) | 2002-01-29 | 2003-01-27 | Split-gate power module and method for suppressing oscillation therein |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35380902P | 2002-01-29 | 2002-01-29 | |
US60/353,809 | 2002-01-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003065454A2 true WO2003065454A2 (en) | 2003-08-07 |
WO2003065454A3 WO2003065454A3 (en) | 2004-02-26 |
Family
ID=27663256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/002326 WO2003065454A2 (en) | 2002-01-29 | 2003-01-27 | Split-gate power module and method for suppressing oscillation therein |
Country Status (8)
Country | Link |
---|---|
US (2) | US6939743B2 (en) |
EP (1) | EP1470588B1 (en) |
JP (1) | JP4732692B2 (en) |
KR (1) | KR20040085169A (en) |
CN (1) | CN100380661C (en) |
AT (1) | ATE339013T1 (en) |
DE (1) | DE60308148T2 (en) |
WO (1) | WO2003065454A2 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4342232B2 (en) * | 2003-07-11 | 2009-10-14 | 三菱電機株式会社 | Semiconductor power module and main circuit current measuring system for measuring main circuit current value of the module |
GB201105912D0 (en) * | 2011-04-07 | 2011-05-18 | Diamond Microwave Devices Ltd | Improved matching techniques for power transistors |
US8581660B1 (en) * | 2012-04-24 | 2013-11-12 | Texas Instruments Incorporated | Power transistor partial current sensing for high precision applications |
CN104380463B (en) * | 2012-06-19 | 2017-05-10 | Abb 技术有限公司 | Substrate for mounting multiple power transistors thereon and power semiconductor module |
DE102014111931B4 (en) * | 2014-08-20 | 2021-07-08 | Infineon Technologies Ag | Low-inductance circuit arrangement with load current busbar |
WO2018109069A1 (en) | 2016-12-16 | 2018-06-21 | Abb Schweiz Ag | Power semiconductor module with low gate path inductance |
JP6838243B2 (en) | 2017-09-29 | 2021-03-03 | 日立Astemo株式会社 | Power converter |
DE102019112935B4 (en) | 2019-05-16 | 2021-04-29 | Danfoss Silicon Power Gmbh | Semiconductor module |
JP6772355B1 (en) * | 2019-10-15 | 2020-10-21 | 株式会社京三製作所 | Switching module |
JP7351209B2 (en) | 2019-12-17 | 2023-09-27 | 富士電機株式会社 | semiconductor equipment |
JP2021097146A (en) | 2019-12-18 | 2021-06-24 | 富士電機株式会社 | Semiconductor device |
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US4907068A (en) * | 1987-01-21 | 1990-03-06 | Siemens Aktiengesellschaft | Semiconductor arrangement having at least one semiconductor body |
EP0645815A2 (en) * | 1993-09-07 | 1995-03-29 | Delco Electronics Corporation | High power semiconductor switch module |
US5731970A (en) * | 1989-12-22 | 1998-03-24 | Hitachi, Ltd. | Power conversion device and semiconductor module suitable for use in the device |
DE19644009A1 (en) * | 1996-10-31 | 1998-05-07 | Siemens Ag | Large-area high-current module of a field-controlled, switchable power semiconductor switch |
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US4639760A (en) * | 1986-01-21 | 1987-01-27 | Motorola, Inc. | High power RF transistor assembly |
JP2751707B2 (en) * | 1992-01-29 | 1998-05-18 | 株式会社日立製作所 | Semiconductor module and power conversion device using the same |
JPH04183001A (en) * | 1990-11-16 | 1992-06-30 | Mitsubishi Electric Corp | Package for microwave ic |
JPH0575314A (en) * | 1991-09-13 | 1993-03-26 | Matsushita Electron Corp | Microwave integrated circuit element |
JP3053298B2 (en) * | 1992-08-19 | 2000-06-19 | 株式会社東芝 | Semiconductor device |
DE59304797D1 (en) * | 1992-08-26 | 1997-01-30 | Eupec Gmbh & Co Kg | Power semiconductor module |
US6291878B1 (en) * | 1993-04-22 | 2001-09-18 | Sundstrand Corporation | Package for multiple high power electrical components |
JP2973799B2 (en) * | 1993-04-23 | 1999-11-08 | 富士電機株式会社 | Power transistor module |
JP2000323647A (en) * | 1999-05-12 | 2000-11-24 | Toshiba Corp | Module semiconductor device and manufacture thereof |
JP4163818B2 (en) * | 1999-07-07 | 2008-10-08 | 三菱電機株式会社 | Internally matched transistor |
JP4138192B2 (en) * | 1999-12-27 | 2008-08-20 | 三菱電機株式会社 | Semiconductor switch device |
US6617679B2 (en) * | 2002-02-08 | 2003-09-09 | Advanced Energy Industries, Inc. | Semiconductor package for multiple high power transistors |
-
2003
- 2003-01-27 WO PCT/US2003/002326 patent/WO2003065454A2/en active IP Right Grant
- 2003-01-27 KR KR10-2004-7011632A patent/KR20040085169A/en not_active Application Discontinuation
- 2003-01-27 JP JP2003564937A patent/JP4732692B2/en not_active Expired - Lifetime
- 2003-01-27 CN CNB03802909XA patent/CN100380661C/en not_active Expired - Fee Related
- 2003-01-27 AT AT03705914T patent/ATE339013T1/en not_active IP Right Cessation
- 2003-01-27 DE DE60308148T patent/DE60308148T2/en not_active Expired - Fee Related
- 2003-01-27 EP EP03705914A patent/EP1470588B1/en not_active Expired - Lifetime
- 2003-01-27 US US10/352,314 patent/US6939743B2/en not_active Expired - Lifetime
-
2005
- 2005-06-03 US US11/145,042 patent/US7342262B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US4907068A (en) * | 1987-01-21 | 1990-03-06 | Siemens Aktiengesellschaft | Semiconductor arrangement having at least one semiconductor body |
US5731970A (en) * | 1989-12-22 | 1998-03-24 | Hitachi, Ltd. | Power conversion device and semiconductor module suitable for use in the device |
EP0645815A2 (en) * | 1993-09-07 | 1995-03-29 | Delco Electronics Corporation | High power semiconductor switch module |
DE19644009A1 (en) * | 1996-10-31 | 1998-05-07 | Siemens Ag | Large-area high-current module of a field-controlled, switchable power semiconductor switch |
Also Published As
Publication number | Publication date |
---|---|
JP4732692B2 (en) | 2011-07-27 |
EP1470588B1 (en) | 2006-09-06 |
EP1470588A2 (en) | 2004-10-27 |
WO2003065454A3 (en) | 2004-02-26 |
CN1625807A (en) | 2005-06-08 |
US7342262B2 (en) | 2008-03-11 |
ATE339013T1 (en) | 2006-09-15 |
CN100380661C (en) | 2008-04-09 |
DE60308148T2 (en) | 2007-08-16 |
KR20040085169A (en) | 2004-10-07 |
US20030141587A1 (en) | 2003-07-31 |
DE60308148D1 (en) | 2006-10-19 |
US20050218500A1 (en) | 2005-10-06 |
JP2006502560A (en) | 2006-01-19 |
US6939743B2 (en) | 2005-09-06 |
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