WO2003073265A3 - METHOD AND SYSTEM FOR CREATING A CUSTOMIZED SUPPORT PACKAGE FOR AN FPGA-BASED SYSTEM-ON-CHIP (SoC) - Google Patents
METHOD AND SYSTEM FOR CREATING A CUSTOMIZED SUPPORT PACKAGE FOR AN FPGA-BASED SYSTEM-ON-CHIP (SoC) Download PDFInfo
- Publication number
- WO2003073265A3 WO2003073265A3 PCT/US2003/004956 US0304956W WO03073265A3 WO 2003073265 A3 WO2003073265 A3 WO 2003073265A3 US 0304956 W US0304956 W US 0304956W WO 03073265 A3 WO03073265 A3 WO 03073265A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- fpga
- soc
- creating
- chip
- support package
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/343—Logical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
Abstract
A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/082,440 US6754882B1 (en) | 2002-02-22 | 2002-02-22 | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
US10/082,440 | 2002-02-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003073265A2 WO2003073265A2 (en) | 2003-09-04 |
WO2003073265A3 true WO2003073265A3 (en) | 2004-08-26 |
Family
ID=27765276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/004956 WO2003073265A2 (en) | 2002-02-22 | 2003-02-21 | METHOD AND SYSTEM FOR CREATING A CUSTOMIZED SUPPORT PACKAGE FOR AN FPGA-BASED SYSTEM-ON-CHIP (SoC) |
Country Status (2)
Country | Link |
---|---|
US (3) | US6754882B1 (en) |
WO (1) | WO2003073265A2 (en) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
NZ508052A (en) * | 2000-11-09 | 2003-06-30 | Derek Ward | Programmable controller |
US6754882B1 (en) * | 2002-02-22 | 2004-06-22 | Xilinx, Inc. | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
US6941538B2 (en) * | 2002-02-22 | 2005-09-06 | Xilinx, Inc. | Method and system for integrating cores in FPGA-based system-on-chip (SoC) |
US7073158B2 (en) * | 2002-05-17 | 2006-07-04 | Pixel Velocity, Inc. | Automated system for designing and developing field programmable gate arrays |
WO2004019239A2 (en) * | 2002-08-21 | 2004-03-04 | Windmill Microsystems Holding Bv | Object-oriented design method for the time-effective and cost-effective development of production-grade embedded systems based on a standardized system architecture |
US8046206B1 (en) * | 2002-09-27 | 2011-10-25 | Cypress Semiconductor Corporation | Method and system using subgraph isomorphism to configure hardware resources |
US7007264B1 (en) * | 2003-05-02 | 2006-02-28 | Xilinx, Inc. | System and method for dynamic reconfigurable computing using automated translation |
US7210116B2 (en) * | 2003-06-27 | 2007-04-24 | Robert Zeidman | Method and apparatus for synthesizing a hardware system from a software description |
US7676194B2 (en) | 2003-08-22 | 2010-03-09 | Rappaport Theodore S | Broadband repeater with security for ultrawideband technologies |
TWI249127B (en) * | 2003-08-22 | 2006-02-11 | Hon Hai Prec Ind Co Ltd | System and method of BSP initializing hardware |
US7885320B1 (en) | 2003-09-11 | 2011-02-08 | Xilinx, Inc. | MGT/FPGA clock management system |
EP1632825B1 (en) * | 2004-09-03 | 2008-10-29 | Derek Ward | Improvements in or relating to programmable logic controller and related electronic devices |
US7225285B1 (en) * | 2004-09-07 | 2007-05-29 | Altera Corporation | Assigning interrupts in multi-master systems |
US7788625B1 (en) * | 2005-04-14 | 2010-08-31 | Xilinx, Inc. | Method and apparatus for precharacterizing systems for use in system level design of integrated circuits |
US7370310B1 (en) * | 2005-08-08 | 2008-05-06 | Xilinx, Inc. | Static address mapping |
US8387019B1 (en) * | 2006-02-16 | 2013-02-26 | Cypress Semiconductor Corporation | Graphical user assignable register map |
US20080036864A1 (en) * | 2006-08-09 | 2008-02-14 | Mccubbrey David | System and method for capturing and transmitting image data streams |
US7702893B1 (en) | 2006-09-22 | 2010-04-20 | Altera Corporation | Integrated circuits with configurable initialization data memory addresses |
US20080151049A1 (en) * | 2006-12-14 | 2008-06-26 | Mccubbrey David L | Gaming surveillance system and method of extracting metadata from multiple synchronized cameras |
GB2459602B (en) * | 2007-02-21 | 2011-09-21 | Pixel Velocity Inc | Scalable system for wide area surveillance |
US8397206B2 (en) | 2007-07-13 | 2013-03-12 | Digi International Inc. | XML board support customization |
US20090086023A1 (en) * | 2007-07-18 | 2009-04-02 | Mccubbrey David L | Sensor system including a configuration of the sensor as a virtual sensor device |
US8032852B1 (en) | 2008-06-17 | 2011-10-04 | Xilinx, Inc. | Method of automating clock signal provisioning within an integrated circuit |
US8441298B1 (en) | 2008-07-01 | 2013-05-14 | Cypress Semiconductor Corporation | Analog bus sharing using transmission gates |
US8015530B1 (en) | 2008-08-05 | 2011-09-06 | Xilinx, Inc. | Method of enabling the generation of reset signals in an integrated circuit |
US8079009B1 (en) * | 2008-12-08 | 2011-12-13 | Xilinx, Inc. | Managing interrupt requests from IP cores |
US8135884B1 (en) | 2009-05-04 | 2012-03-13 | Cypress Semiconductor Corporation | Programmable interrupt routing system |
US9448964B2 (en) | 2009-05-04 | 2016-09-20 | Cypress Semiconductor Corporation | Autonomous control in a programmable system |
US8179161B1 (en) | 2009-05-05 | 2012-05-15 | Cypress Semiconductor Corporation | Programmable input/output circuit |
US8487655B1 (en) | 2009-05-05 | 2013-07-16 | Cypress Semiconductor Corporation | Combined analog architecture and functionality in a mixed-signal array |
US9612987B2 (en) * | 2009-05-09 | 2017-04-04 | Cypress Semiconductor Corporation | Dynamically reconfigurable analog routing circuits and methods for system on a chip |
EP2499827A4 (en) * | 2009-11-13 | 2018-01-03 | Pixel Velocity, Inc. | Method for tracking an object through an environment across multiple cameras |
US8516433B1 (en) | 2010-06-25 | 2013-08-20 | Cadence Design Systems, Inc. | Method and system for mapping memory when selecting an electronic product |
US8375344B1 (en) * | 2010-06-25 | 2013-02-12 | Cadence Design Systems, Inc. | Method and system for determining configurations |
CN102637157B (en) * | 2011-02-15 | 2014-12-03 | 郑磊 | DTSOC (digital template system on chip) |
US8555217B1 (en) * | 2011-06-20 | 2013-10-08 | Lattice Semiconductor Corporation | Integrated circuit design software with cross probing between tool graphical user interfaces (GUIs) |
US10061626B2 (en) | 2013-06-05 | 2018-08-28 | Splunk Inc. | Application framework providing a registry for mapping names to component instances |
US9594545B2 (en) * | 2013-06-05 | 2017-03-14 | Splunk Inc. | System for displaying notification dependencies between component instances |
US8756614B2 (en) | 2013-06-05 | 2014-06-17 | Splunk Inc. | Central registry for binding features using dynamic pointers |
US9558129B2 (en) | 2014-06-10 | 2017-01-31 | Xilinx, Inc. | Circuits for and methods of enabling the access to data |
US9514093B2 (en) * | 2014-09-26 | 2016-12-06 | Intel Corporation | Method and apparatus for stacking core and uncore dies having landing slots |
US9792250B1 (en) | 2015-04-21 | 2017-10-17 | National Technology & Engineering Solutions Of Sandia, Llc | System on chip module configured for event-driven architecture |
US9438269B1 (en) | 2015-09-02 | 2016-09-06 | International Business Machines Corporation | Accelerating codeset conversion in a computing environment |
US10248585B2 (en) | 2016-06-14 | 2019-04-02 | Oracle International Corporation | System and method for filtering field programmable gate array input/output |
CN113722271B (en) * | 2021-07-20 | 2023-11-21 | 湖南艾科诺维科技有限公司 | File management method, system and medium for data acquisition and playback |
CN115033230B (en) * | 2022-06-27 | 2024-02-27 | 中国电力科学研究院有限公司 | Method, device, equipment and medium for generating drive program of embedded hardware platform |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5889990A (en) * | 1996-11-05 | 1999-03-30 | Sun Microsystems, Inc. | Information appliance software architecture with replaceable service module providing abstraction function between system library and platform specific OS |
WO2001044934A1 (en) * | 1999-12-15 | 2001-06-21 | Sun Microsystems, Inc. | Preparation of a software configuration using an xml type programming language |
WO2002008888A2 (en) * | 2000-07-20 | 2002-01-31 | Celoxica Limited | System, method, and article of manufacture for a reconfigurable hardware-based multimedia device |
Family Cites Families (94)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US98587A (en) * | 1870-01-04 | Improvement in gymnastic apparatus | ||
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4706216A (en) | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US5142625A (en) | 1985-06-12 | 1992-08-25 | Minolta Camera Kabushiki Kaisha | One-chip microcomputer including a programmable logic array for interrupt control |
US5072418A (en) | 1989-05-04 | 1991-12-10 | Texas Instruments Incorporated | Series maxium/minimum function computing devices, systems and methods |
US4855669A (en) | 1987-10-07 | 1989-08-08 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US4878174A (en) | 1987-11-03 | 1989-10-31 | Lsi Logic Corporation | Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions |
JPH02235156A (en) | 1989-03-08 | 1990-09-18 | Canon Inc | Information processor |
US5274570A (en) | 1989-05-22 | 1993-12-28 | Mazda Motor Corporation | Integrated circuit having metal substrate |
JPH03210649A (en) | 1990-01-12 | 1991-09-13 | Fujitsu Ltd | Microcomputer and its bus cycle control method |
US5550782A (en) | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US5347181A (en) | 1992-04-29 | 1994-09-13 | Motorola, Inc. | Interface control logic for embedding a microprocessor in a gate array |
WO1993025968A1 (en) | 1992-06-10 | 1993-12-23 | Furtek Frederick C | A modular computer based on reconfigurable logic |
US5671355A (en) | 1992-06-26 | 1997-09-23 | Predacomm, Inc. | Reconfigurable network interface apparatus and method |
US5339262A (en) | 1992-07-10 | 1994-08-16 | Lsi Logic Corporation | Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC |
US5311114A (en) | 1992-10-27 | 1994-05-10 | Seeq Technology, Incorporated | Apparatus and method for full-duplex ethernet communications |
GB9223226D0 (en) | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5361373A (en) | 1992-12-11 | 1994-11-01 | Gilson Kent L | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
GB9303084D0 (en) | 1993-02-16 | 1993-03-31 | Inmos Ltd | Programmable logic circuit |
JPH0736858A (en) | 1993-07-21 | 1995-02-07 | Hitachi Ltd | Signal processor |
US5457410A (en) | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
WO1995004402A1 (en) | 1993-08-03 | 1995-02-09 | Xilinx, Inc. | Microprocessor-based fpga |
US5740404A (en) | 1993-09-27 | 1998-04-14 | Hitachi America Limited | Digital signal processor with on-chip select decoder and wait state generator |
US5500943A (en) | 1993-11-02 | 1996-03-19 | Motorola, Inc. | Data processor with rename buffer and FIFO buffer for in-order instruction completion |
EP0734573B1 (en) | 1993-12-13 | 2002-04-03 | Lattice Semiconductor Corporation | Application specific modules in a programmable logic device |
US5742179A (en) | 1994-01-27 | 1998-04-21 | Dyna Logic Corporation | High speed programmable logic architecture |
US5574942A (en) | 1994-02-28 | 1996-11-12 | Intel Corporation | Hybrid execution unit for complex microprocessor |
US5543640A (en) | 1994-03-15 | 1996-08-06 | National Semiconductor Corporation | Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module |
US5600845A (en) | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
US5574930A (en) | 1994-08-12 | 1996-11-12 | University Of Hawaii | Computer system and method using functional memory |
US5732250A (en) | 1994-09-15 | 1998-03-24 | Intel Corporation | Multi-function microprocessor wait state mechanism using external control line |
US5742180A (en) | 1995-02-10 | 1998-04-21 | Massachusetts Institute Of Technology | Dynamically programmable gate array with multiple contexts |
US5892961A (en) | 1995-02-17 | 1999-04-06 | Xilinx, Inc. | Field programmable gate array having programming instructions in the configuration bitstream |
US5748979A (en) | 1995-04-05 | 1998-05-05 | Xilinx Inc | Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table |
US5737631A (en) | 1995-04-05 | 1998-04-07 | Xilinx Inc | Reprogrammable instruction set accelerator |
US5752035A (en) | 1995-04-05 | 1998-05-12 | Xilinx, Inc. | Method for compiling and executing programs for reprogrammable instruction set accelerator |
WO1996034346A1 (en) | 1995-04-28 | 1996-10-31 | Xilinx, Inc. | Microprocessor with distributed registers accessible by programmable logic device |
GB9508931D0 (en) | 1995-05-02 | 1995-06-21 | Xilinx Inc | Programmable switch for FPGA input/output signals |
EP0780017A1 (en) | 1995-07-10 | 1997-06-25 | Xilinx, Inc. | System comprising field programmable gate array and intelligent memory |
US6175952B1 (en) | 1997-05-27 | 2001-01-16 | Altera Corporation | Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions |
US5933023A (en) | 1996-09-03 | 1999-08-03 | Xilinx, Inc. | FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines |
KR19990071991A (en) * | 1996-10-10 | 1999-09-27 | 파레 호세 마리아 인센서 | Process for prototyping of mixed-signal applications and field programmable systems on chip for application of these processes |
US6102964A (en) | 1996-10-28 | 2000-08-15 | Altera Corporation | Fitting for incremental compilation of electronic designs |
US5889788A (en) | 1997-02-03 | 1999-03-30 | Motorola, Inc. | Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation |
US6172990B1 (en) | 1997-06-19 | 2001-01-09 | Xaqti Corporation | Media access control micro-RISC stream processor and method for implementing the same |
US5914616A (en) | 1997-02-26 | 1999-06-22 | Xilinx, Inc. | FPGA repeatable interconnect structure with hierarchical interconnect lines |
US5874834A (en) | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
US6011407A (en) | 1997-06-13 | 2000-01-04 | Xilinx, Inc. | Field programmable gate array with dedicated computer bus interface and method for configuring both |
US5970254A (en) | 1997-06-27 | 1999-10-19 | Cooke; Laurence H. | Integrated processor and programmable data path chip for reconfigurable computing |
US5995424A (en) | 1997-07-16 | 1999-11-30 | Tanisys Technology, Inc. | Synchronous memory test system |
US6311149B1 (en) * | 1997-08-18 | 2001-10-30 | National Instruments Corporation | Reconfigurable test system |
US6020755A (en) | 1997-09-26 | 2000-02-01 | Lucent Technologies Inc. | Hybrid programmable gate arrays |
US6034542A (en) * | 1997-10-14 | 2000-03-07 | Xilinx, Inc. | Bus structure for modularized chip with FPGA modules |
US6279045B1 (en) | 1997-12-29 | 2001-08-21 | Kawasaki Steel Corporation | Multimedia interface having a multimedia processor and a field programmable gate array |
US6096091A (en) | 1998-02-24 | 2000-08-01 | Advanced Micro Devices, Inc. | Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip |
US6178541B1 (en) | 1998-03-30 | 2001-01-23 | Lsi Logic Corporation | PLD/ASIC hybrid integrated circuit |
US6163166A (en) | 1998-05-27 | 2000-12-19 | Altera Corporation | Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers |
US6282627B1 (en) | 1998-06-29 | 2001-08-28 | Chameleon Systems, Inc. | Integrated processor and programmable data path chip for reconfigurable computing |
US6480989B2 (en) | 1998-06-29 | 2002-11-12 | Lsi Logic Corporation | Integrated circuit design incorporating a power mesh |
US6467009B1 (en) | 1998-10-14 | 2002-10-15 | Triscend Corporation | Configurable processor system unit |
US6300049B2 (en) | 1998-10-15 | 2001-10-09 | Eastman Kodak Company | Imaging element containing an electrically-conductive layer |
US6343207B1 (en) | 1998-11-03 | 2002-01-29 | Harris Corporation | Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor |
US6154051A (en) | 1998-11-05 | 2000-11-28 | Vantis Corporation | Tileable and compact layout for super variable grain blocks within FPGA device |
US6181163B1 (en) | 1999-01-21 | 2001-01-30 | Vantis Corporation | FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals |
US6356987B1 (en) | 1999-03-10 | 2002-03-12 | Atmel Corporation | Microprocessing device having programmable wait states |
US6301696B1 (en) | 1999-03-30 | 2001-10-09 | Actel Corporation | Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template |
US6211697B1 (en) | 1999-05-25 | 2001-04-03 | Actel | Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure |
US6272451B1 (en) * | 1999-07-16 | 2001-08-07 | Atmel Corporation | Software tool to allow field programmable system level devices |
JP3512166B2 (en) | 1999-11-26 | 2004-03-29 | 松下電器産業株式会社 | How to set up a programmable logic device |
US6618839B1 (en) * | 1999-11-30 | 2003-09-09 | Synplicity, Inc. | Method and system for providing an electronic system design with enhanced debugging capabilities |
US6519753B1 (en) | 1999-11-30 | 2003-02-11 | Quicklogic Corporation | Programmable device with an embedded portion for receiving a standard circuit design |
US6588006B1 (en) * | 1999-12-16 | 2003-07-01 | Lsi Logic Corporation | Programmable ASIC |
US6434735B1 (en) * | 1999-12-16 | 2002-08-13 | Lsi Logic Corporation | Method for programming an FPGA and implementing an FPGA interconnect |
GB2382498B (en) * | 2000-01-24 | 2003-11-05 | Radioscape Ltd | Digital wireless basestation |
US6539522B1 (en) * | 2000-01-31 | 2003-03-25 | International Business Machines Corporation | Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs |
US6539508B1 (en) | 2000-03-15 | 2003-03-25 | Xilinx, Inc. | Methods and circuits for testing programmable logic |
US6587995B1 (en) * | 2000-04-19 | 2003-07-01 | Koninklijke Philips Electronics N.V. | Enhanced programmable core model with integrated graphical debugging functionality |
US6535043B2 (en) * | 2000-05-26 | 2003-03-18 | Lattice Semiconductor Corp | Clock signal selection system, method of generating a clock signal and programmable clock manager including same |
KR100374328B1 (en) * | 2000-06-03 | 2003-03-03 | 박현숙 | chip design verification and test apparatus and method |
US6353331B1 (en) | 2000-07-10 | 2002-03-05 | Xilinx, Inc. | Complex programmable logic device with lookup table |
US6507942B1 (en) | 2000-07-11 | 2003-01-14 | Xilinx , Inc. | Methods and circuits for testing a circuit fabrication process for device uniformity |
US6518787B1 (en) | 2000-09-21 | 2003-02-11 | Triscend Corporation | Input/output architecture for efficient configuration of programmable input/output cells |
US20020072893A1 (en) * | 2000-10-12 | 2002-06-13 | Alex Wilson | System, method and article of manufacture for using a microprocessor emulation in a hardware application with non time-critical functions |
US6611951B1 (en) | 2000-11-30 | 2003-08-26 | Lsi Logic Corporation | Method for estimating cell porosity of hardmacs |
US6522167B1 (en) | 2001-01-09 | 2003-02-18 | Xilinx, Inc. | User configurable on-chip memory system |
US6532572B1 (en) | 2001-03-14 | 2003-03-11 | Lsi Logic Corporation | Method for estimating porosity of hardmacs |
US6541991B1 (en) | 2001-05-04 | 2003-04-01 | Xilinx Inc. | Interface apparatus and method for testing different sized ball grid array integrated circuits |
US6578174B2 (en) * | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
US6601227B1 (en) | 2001-06-27 | 2003-07-29 | Xilinx, Inc. | Method for making large-scale ASIC using pre-engineered long distance routing structure |
US7207041B2 (en) * | 2001-06-28 | 2007-04-17 | Tranzeo Wireless Technologies, Inc. | Open platform architecture for shared resource access management |
US6510548B1 (en) | 2001-08-03 | 2003-01-21 | Xilinx, Inc. | Method for providing pre-designed modules for programmable logic devices |
US6798239B2 (en) | 2001-09-28 | 2004-09-28 | Xilinx, Inc. | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry |
US6779168B2 (en) * | 2002-02-01 | 2004-08-17 | Lsi Logic Corporation | Magnetoresistive memory for a complex programmable logic device |
US6754882B1 (en) * | 2002-02-22 | 2004-06-22 | Xilinx, Inc. | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
-
2002
- 2002-02-22 US US10/082,440 patent/US6754882B1/en not_active Expired - Lifetime
-
2003
- 2003-02-21 WO PCT/US2003/004956 patent/WO2003073265A2/en active Application Filing
-
2004
- 2004-05-18 US US10/847,704 patent/US6996796B2/en not_active Expired - Lifetime
- 2004-05-18 US US10/848,084 patent/US7552415B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5889990A (en) * | 1996-11-05 | 1999-03-30 | Sun Microsystems, Inc. | Information appliance software architecture with replaceable service module providing abstraction function between system library and platform specific OS |
WO2001044934A1 (en) * | 1999-12-15 | 2001-06-21 | Sun Microsystems, Inc. | Preparation of a software configuration using an xml type programming language |
WO2002008888A2 (en) * | 2000-07-20 | 2002-01-31 | Celoxica Limited | System, method, and article of manufacture for a reconfigurable hardware-based multimedia device |
Non-Patent Citations (2)
Title |
---|
MICROSOFT CORPORATION: "Microsoft Windows CE Platform Builder 3.0: Getting Started", MICROSOFT MSDN WEBSITE, - May 2000 (2000-05-01), redmond, pages 1 - 21, XP002273531, Retrieved from the Internet <URL:http://msdn.microsoft.com/library/en-us/dnce30/html/gettingstarted30.asp> [retrieved on 20040315] * |
NEUGASS H ET AL: "VxWorks: an interactive development environment and real-time kernel for Gmicro", TRON PROJECT SYMPOSIUM, 1991. PROCEEDINGS., EIGHTH TOKYO, JAPAN 21-27 NOV. 1991, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 21 November 1991 (1991-11-21), pages 196 - 207, XP010026506, ISBN: 0-8186-2475-2 * |
Also Published As
Publication number | Publication date |
---|---|
US20040225992A1 (en) | 2004-11-11 |
US6996796B2 (en) | 2006-02-07 |
US20040210855A1 (en) | 2004-10-21 |
US7552415B2 (en) | 2009-06-23 |
WO2003073265A2 (en) | 2003-09-04 |
US6754882B1 (en) | 2004-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2003073265A3 (en) | METHOD AND SYSTEM FOR CREATING A CUSTOMIZED SUPPORT PACKAGE FOR AN FPGA-BASED SYSTEM-ON-CHIP (SoC) | |
WO2003073314A3 (en) | Method and system for integrating cores in fpga-based system-on-chip (soc) | |
WO2007044018A3 (en) | Methods of model compilation | |
AU2003214552A1 (en) | Method and apparatus for modeling extensible markup language (xml) applications using the unified modeling language (uml) | |
WO2006019718A3 (en) | System and method for updating software on a computer | |
WO2001037170A3 (en) | Forms creation method and e-commerce method | |
WO2004079973A3 (en) | Systems and methods for an extensible software proxy | |
WO2001092903A3 (en) | Method and apparatus for maximizing test coverage | |
AU2002311865A1 (en) | Method and apparatus for computer modeling diabetes | |
AU2001238677A1 (en) | Method for preparing anti-mif antibodies | |
EP1579287A3 (en) | Dynamic resource allocation platform and method for time related resources | |
WO2004102382A3 (en) | Methods and apparatus for generating upgraded software from initial software and software upgrade packages | |
AU2003293543A1 (en) | System and method for stabilizing antibodies with histidine | |
ZA200401485B (en) | Method and system for enhancing paste functionality of a computer software application. | |
WO2006130265A3 (en) | Split download for electronic software downloads | |
WO2001065332A3 (en) | System and method for automatic software code generation | |
EP1536325A4 (en) | Gui application development support device and method, and computer program | |
AU2001289124A1 (en) | A testing device for semiconductor components and a method of using the device | |
AU2003221964A1 (en) | Biomolecule diagnostic devices and method for producing biomolecule diagnostic devices | |
AU2003262015A1 (en) | Requirement defining method, method for developing software, method for changing requirement word, and newly defining method | |
WO2003058441A3 (en) | Method and apparatus for xml schema publishing into a user interface | |
WO2004032328A3 (en) | Integrated software and method for authenticating same | |
AU2002304071A1 (en) | Automatic knowledge creating method, automatic knowledge creating system, automatic knowledge creating program, automatic designing method and automatic designing system | |
AU2003271145A1 (en) | Restaurant menu providing method and device | |
AU2001292726A1 (en) | Interface component a positioning system and method for designing an interface component |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): CA |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
122 | Ep: pct application non-entry in european phase |