WO2003073357A1 - Methods and apparatus for fabricating chip-on-board modules - Google Patents
Methods and apparatus for fabricating chip-on-board modules Download PDFInfo
- Publication number
- WO2003073357A1 WO2003073357A1 PCT/US2003/005846 US0305846W WO03073357A1 WO 2003073357 A1 WO2003073357 A1 WO 2003073357A1 US 0305846 W US0305846 W US 0305846W WO 03073357 A1 WO03073357 A1 WO 03073357A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- selectively
- settable material
- circuit board
- unpackaged
- board
- Prior art date
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03716193A EP1483723A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
KR10-2004-7013249A KR20050004787A (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
CA002477763A CA2477763A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
AU2003219909A AU2003219909A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US36003602P | 2002-02-26 | 2002-02-26 | |
US60/360,036 | 2002-02-26 | ||
US10/371,800 US7238550B2 (en) | 2002-02-26 | 2003-02-20 | Methods and apparatus for fabricating Chip-on-Board modules |
US10/371,800 | 2003-02-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003073357A1 true WO2003073357A1 (en) | 2003-09-04 |
WO2003073357A8 WO2003073357A8 (en) | 2005-07-21 |
Family
ID=27760588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/005846 WO2003073357A1 (en) | 2002-02-26 | 2003-02-24 | Methods and apparatus for fabricating chip-on-board modules |
Country Status (2)
Country | Link |
---|---|
US (1) | US7238550B2 (en) |
WO (1) | WO2003073357A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
US7443023B2 (en) | 2004-09-03 | 2008-10-28 | Entorian Technologies, Lp | High capacity thin module system |
US7473568B2 (en) * | 2006-05-17 | 2009-01-06 | Kingston Technology Corp. | Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in |
US9743513B2 (en) * | 2014-12-26 | 2017-08-22 | Industrial Technology Research Institute | Flexible electronic device |
KR20210006121A (en) * | 2019-07-08 | 2021-01-18 | 에스케이하이닉스 주식회사 | Memory system and operation method thereof |
CN111385980B (en) * | 2020-05-19 | 2022-06-14 | 桂林智慧产业园有限公司 | Particle swarm-based PCB (printed Circuit Board) surface mounting method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5237508A (en) * | 1989-08-10 | 1993-08-17 | Fujitsu Limited | Production control system |
US6154957A (en) * | 1996-10-11 | 2000-12-05 | Matsushita Electric Industrial Co., Ltd. | Method of and apparatus for mounting electronic parts |
US6161277A (en) * | 1996-11-27 | 2000-12-19 | Fuji Machine Co., Ltd. | Circuit-component mounting system |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4647959A (en) * | 1985-05-20 | 1987-03-03 | Tektronix, Inc. | Integrated circuit package, and method of forming an integrated circuit package |
FR2705832B1 (en) * | 1993-05-28 | 1995-06-30 | Commissariat Energie Atomique | Method for producing a sealing bead and mechanical strength between a substrate and a chip hybridized by balls on the substrate. |
US5477611A (en) * | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
US6119049A (en) * | 1996-08-12 | 2000-09-12 | Tandon Associates, Inc. | Memory module assembly using partially defective chips |
US5981314A (en) * | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
KR100251859B1 (en) * | 1997-01-28 | 2000-04-15 | 마이클 디. 오브라이언 | Singulation method of ball grid array semiconductor package manufacturing by using flexible circuit board strip |
US5962810A (en) * | 1997-09-09 | 1999-10-05 | Amkor Technology, Inc. | Integrated circuit package employing a transparent encapsulant |
US6049124A (en) * | 1997-12-10 | 2000-04-11 | Intel Corporation | Semiconductor package |
US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
US6238948B1 (en) * | 1999-03-03 | 2001-05-29 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material |
US6528345B1 (en) * | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
US6306688B1 (en) * | 1999-04-28 | 2001-10-23 | Teravicta Technologies, Inc. | Method of reworkably removing a fluorinated polymer encapsulant |
US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
US6841412B1 (en) * | 1999-11-05 | 2005-01-11 | Texas Instruments Incorporated | Encapsulation for particle entrapment |
US6441481B1 (en) * | 2000-04-10 | 2002-08-27 | Analog Devices, Inc. | Hermetically sealed microstructure package |
US6214644B1 (en) * | 2000-06-30 | 2001-04-10 | Amkor Technology, Inc. | Flip-chip micromachine package fabrication method |
JP2002203865A (en) * | 2001-01-05 | 2002-07-19 | Mitsubishi Electric Corp | Semiconductor device, its die bonding apparatus and die bonding method |
US20020182774A1 (en) * | 2001-05-29 | 2002-12-05 | Heckman James Kent | Die-attach method and assemblies using film and epoxy bonds |
US6603183B1 (en) * | 2001-09-04 | 2003-08-05 | Amkor Technology, Inc. | Quick sealing glass-lidded package |
US6784555B2 (en) * | 2001-09-17 | 2004-08-31 | Dow Corning Corporation | Die attach adhesives for semiconductor applications utilizing a polymeric base material with inorganic insulator particles of various sizes |
US6512286B1 (en) * | 2001-10-09 | 2003-01-28 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with no void in encapsulant and method for fabricating the same |
US6569709B2 (en) * | 2001-10-15 | 2003-05-27 | Micron Technology, Inc. | Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods |
JP3956199B2 (en) * | 2002-02-20 | 2007-08-08 | シャープ株式会社 | Manufacturing method of solid-state imaging device and mask used in the manufacturing method |
US6798074B2 (en) * | 2002-03-04 | 2004-09-28 | Motorola, Inc. | Method of attaching a die to a substrate |
-
2003
- 2003-02-20 US US10/371,800 patent/US7238550B2/en not_active Expired - Lifetime
- 2003-02-24 WO PCT/US2003/005846 patent/WO2003073357A1/en not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5237508A (en) * | 1989-08-10 | 1993-08-17 | Fujitsu Limited | Production control system |
US6154957A (en) * | 1996-10-11 | 2000-12-05 | Matsushita Electric Industrial Co., Ltd. | Method of and apparatus for mounting electronic parts |
US6161277A (en) * | 1996-11-27 | 2000-12-19 | Fuji Machine Co., Ltd. | Circuit-component mounting system |
Also Published As
Publication number | Publication date |
---|---|
WO2003073357A8 (en) | 2005-07-21 |
US7238550B2 (en) | 2007-07-03 |
US20030159278A1 (en) | 2003-08-28 |
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