WO2003073469A3 - Delay circuit with delay relatively independent of process, voltage, and temperature variations - Google Patents

Delay circuit with delay relatively independent of process, voltage, and temperature variations Download PDF

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Publication number
WO2003073469A3
WO2003073469A3 PCT/US2003/004874 US0304874W WO03073469A3 WO 2003073469 A3 WO2003073469 A3 WO 2003073469A3 US 0304874 W US0304874 W US 0304874W WO 03073469 A3 WO03073469 A3 WO 03073469A3
Authority
WO
WIPO (PCT)
Prior art keywords
delay
voltage
relatively independent
temperature variations
delay circuit
Prior art date
Application number
PCT/US2003/004874
Other languages
French (fr)
Other versions
WO2003073469A2 (en
Inventor
Janardhanan S Ajit
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of WO2003073469A2 publication Critical patent/WO2003073469A2/en
Publication of WO2003073469A3 publication Critical patent/WO2003073469A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay

Abstract

Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature ('PVT') variations include sensing an output signal after a number of inverters and activating different numbers of transistors (116, 118, 124) and/or adjusting strength of transistors in a delay path to compensate for PVT variations.
PCT/US2003/004874 2002-02-21 2003-02-21 Delay circuit with delay relatively independent of process, voltage, and temperature variations WO2003073469A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US35787802P 2002-02-21 2002-02-21
US60/357,878 2002-02-21
US10/180,501 2002-06-27
US10/180,501 US6646488B2 (en) 2002-02-21 2002-06-27 Delay circuit with delay relatively independent of process, voltage, and temperature variations

Publications (2)

Publication Number Publication Date
WO2003073469A2 WO2003073469A2 (en) 2003-09-04
WO2003073469A3 true WO2003073469A3 (en) 2003-12-31

Family

ID=27737021

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/004874 WO2003073469A2 (en) 2002-02-21 2003-02-21 Delay circuit with delay relatively independent of process, voltage, and temperature variations

Country Status (2)

Country Link
US (3) US6646488B2 (en)
WO (1) WO2003073469A2 (en)

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TW503620B (en) * 2000-02-04 2002-09-21 Sanyo Electric Co Drive apparatus for CCD image sensor
US7256617B2 (en) * 2003-03-13 2007-08-14 Sun Microsystems, Inc. Method and apparatus to linearize output buffer and on-chip termination
KR100501634B1 (en) * 2003-05-28 2005-07-18 주식회사 하이닉스반도체 Temperature detecting circuit
US7208984B1 (en) * 2004-07-15 2007-04-24 Linear Technology Corporation CMOS driver with minimum shoot-through current
US7276946B2 (en) * 2004-07-16 2007-10-02 Micron Technology, Inc. Measure-controlled delay circuits with reduced phase error
US20060176096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Power supply insensitive delay element
US7355435B2 (en) * 2005-02-10 2008-04-08 International Business Machines Corporation On-chip detection of power supply vulnerabilities
JP2006279883A (en) * 2005-03-30 2006-10-12 Sanyo Electric Co Ltd Driver circuit
JP4542975B2 (en) * 2005-09-27 2010-09-15 株式会社アドバンテスト Electronic device, load fluctuation compensation circuit, power supply apparatus, and test apparatus
US7692598B1 (en) 2005-10-26 2010-04-06 Niitek, Inc. Method and apparatus for transmitting and receiving time-domain radar signals
EP1801975A1 (en) * 2005-12-21 2007-06-27 STMicroelectronics S.r.l. Output buffer
US7411436B2 (en) * 2006-02-28 2008-08-12 Cornell Research Foundation, Inc. Self-timed thermally-aware circuits and methods of use thereof
US9316729B2 (en) * 2007-05-25 2016-04-19 Niitek, Inc. Systems and methods for providing trigger timing
US7649492B2 (en) * 2007-05-25 2010-01-19 Niitek, Inc. Systems and methods for providing delayed signals
US7652619B1 (en) 2007-05-25 2010-01-26 Niitek, Inc. Systems and methods using multiple down-conversion ratios in acquisition windows
US7675454B2 (en) * 2007-09-07 2010-03-09 Niitek, Inc. System, method, and computer program product providing three-dimensional visualization of ground penetrating radar data
US8207885B2 (en) * 2007-09-19 2012-06-26 Niitek, Inc. Adjustable pulse width ground penetrating radar
KR20110037923A (en) * 2009-10-07 2011-04-13 페어차일드 세미컨덕터 코포레이션 Edge rate control
US20120206191A1 (en) * 2011-02-11 2012-08-16 Llewellyn William D Edge rate control (erc) pre-biasing technique
US8633738B2 (en) * 2012-01-18 2014-01-21 Qualcomm Incorporated Slew-rate limited output driver with output-load sensing feedback loop
US8873311B2 (en) 2012-02-14 2014-10-28 Micron Technology, Inc. Supply independent delayer
US8779819B1 (en) * 2012-04-30 2014-07-15 Pmc-Sierra Us, Inc. Transmitter output impedance calibration for output rise and fall time equalization and edge rate control
TWI485988B (en) * 2012-05-18 2015-05-21 Elite Semiconductor Esmt Delay circuit and delay stage thereof
WO2014210192A1 (en) * 2013-06-25 2014-12-31 Ess Technology, Inc. Delay circuit independent of supply voltage
US10126206B2 (en) * 2015-06-29 2018-11-13 General Electric Company Method and system for portable engine health monitoring
EP3319274B1 (en) * 2016-11-02 2019-04-17 NXP USA, Inc. Can module and method therefor
US10782347B2 (en) 2017-10-23 2020-09-22 Nxp B.V. Method for identifying a fault at a device output and system therefor
US10436839B2 (en) * 2017-10-23 2019-10-08 Nxp B.V. Method for identifying a fault at a device output and system therefor
TWI690160B (en) * 2019-06-13 2020-04-01 瑞昱半導體股份有限公司 Delay circuit

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5175445A (en) * 1990-04-26 1992-12-29 Kabushiki Kaisha Toshiba Mos type input circuit
US5767728A (en) * 1996-09-05 1998-06-16 International Business Machines Corporation Noise tolerant CMOS inverter circuit having a resistive bias
US6177819B1 (en) * 1999-04-01 2001-01-23 Xilinx, Inc. Integrated circuit driver with adjustable trip point

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US5545955A (en) * 1994-03-04 1996-08-13 International Rectifier Corporation MOS gate driver for ballast circuits
US6380770B1 (en) * 1998-10-08 2002-04-30 National Semiconductor Corporation Low ground bounce and low power supply bounce output driver with dual, interlocked, asymmetric delay lines
US6518794B2 (en) * 2000-04-24 2003-02-11 International Business Machines Corporation AC drive cross point adjust method and apparatus
US6256235B1 (en) * 2000-06-23 2001-07-03 Micron Technology, Inc. Adjustable driver pre-equalization for memory subsystems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175445A (en) * 1990-04-26 1992-12-29 Kabushiki Kaisha Toshiba Mos type input circuit
US5767728A (en) * 1996-09-05 1998-06-16 International Business Machines Corporation Noise tolerant CMOS inverter circuit having a resistive bias
US6177819B1 (en) * 1999-04-01 2001-01-23 Xilinx, Inc. Integrated circuit driver with adjustable trip point

Also Published As

Publication number Publication date
US6815995B2 (en) 2004-11-09
US20050030078A1 (en) 2005-02-10
US20040090255A1 (en) 2004-05-13
US6930528B2 (en) 2005-08-16
US6646488B2 (en) 2003-11-11
WO2003073469A2 (en) 2003-09-04
US20030155954A1 (en) 2003-08-21

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