WO2003075477A3 - High speed configurable transceiver architecture - Google Patents

High speed configurable transceiver architecture Download PDF

Info

Publication number
WO2003075477A3
WO2003075477A3 PCT/US2003/006249 US0306249W WO03075477A3 WO 2003075477 A3 WO2003075477 A3 WO 2003075477A3 US 0306249 W US0306249 W US 0306249W WO 03075477 A3 WO03075477 A3 WO 03075477A3
Authority
WO
WIPO (PCT)
Prior art keywords
transceivers
high speed
integrated circuit
transceiver architecture
contain
Prior art date
Application number
PCT/US2003/006249
Other languages
French (fr)
Other versions
WO2003075477A2 (en
Inventor
Suresh M Menon
Atul V Ghia
Warren E Cory
Paul T Sasaki
Philip M Freidin
Santiago G Asuncion
Philip D Costello
Vasisht M Vadi
Adebabay M Bekele
Hare K Verma
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27787603&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2003075477(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Xilinx Inc filed Critical Xilinx Inc
Priority to JP2003573797A priority Critical patent/JP4263105B2/en
Priority to EP03711327A priority patent/EP1504537B1/en
Priority to CA2478023A priority patent/CA2478023C/en
Priority to DE60328016T priority patent/DE60328016D1/en
Publication of WO2003075477A2 publication Critical patent/WO2003075477A2/en
Publication of WO2003075477A3 publication Critical patent/WO2003075477A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.
PCT/US2003/006249 2002-03-01 2003-02-28 High speed configurable transceiver architecture WO2003075477A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003573797A JP4263105B2 (en) 2002-03-01 2003-02-28 Fast configurable transceiver architecture
EP03711327A EP1504537B1 (en) 2002-03-01 2003-02-28 High speed configurable transceiver architecture
CA2478023A CA2478023C (en) 2002-03-01 2003-02-28 High speed configurable transceiver architecture
DE60328016T DE60328016D1 (en) 2002-03-01 2003-02-28 FAST, RECONFIGURABLE SEND RECEIVER ARCHITECTURE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/090,250 US7187709B1 (en) 2002-03-01 2002-03-01 High speed configurable transceiver architecture
US10/090,250 2002-03-01

Publications (2)

Publication Number Publication Date
WO2003075477A2 WO2003075477A2 (en) 2003-09-12
WO2003075477A3 true WO2003075477A3 (en) 2004-12-02

Family

ID=27787603

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/006249 WO2003075477A2 (en) 2002-03-01 2003-02-28 High speed configurable transceiver architecture

Country Status (6)

Country Link
US (1) US7187709B1 (en)
EP (1) EP1504537B1 (en)
JP (1) JP4263105B2 (en)
CA (1) CA2478023C (en)
DE (1) DE60328016D1 (en)
WO (1) WO2003075477A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7885320B1 (en) 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
US7519747B1 (en) 2003-09-11 2009-04-14 Xilinx, Inc. Variable latency buffer and method of operation
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7751442B2 (en) * 2003-12-19 2010-07-06 Intel Corporation Serial ethernet device-to-device interconnection
US8964547B1 (en) 2004-06-08 2015-02-24 Oracle America, Inc. Credit announcement
US7210056B2 (en) 2004-06-08 2007-04-24 Sun Microsystems, Inc. Low latency comma detection and clock alignment
US7860096B2 (en) 2004-06-08 2010-12-28 Oracle America, Inc. Switching method and apparatus for use in a communications network
US7733855B1 (en) 2004-06-08 2010-06-08 Oracle America, Inc. Community separation enforcement
US7639616B1 (en) 2004-06-08 2009-12-29 Sun Microsystems, Inc. Adaptive cut-through algorithm
US20060136606A1 (en) * 2004-11-19 2006-06-22 Guzy D J Logic device comprising reconfigurable core logic for use in conjunction with microprocessor-based computer systems
EP1764940A1 (en) 2005-09-20 2007-03-21 Istituto Superiore Mario Boella A media converter and a system for converting a packet-based data stream into a serial data stream und vice versa
US7492291B2 (en) * 2006-10-20 2009-02-17 Agere Systems Inc. Methods and apparatus for interfacing a plurality of encoded serial data streams to a serializer/deserializer circuit
CN101191819B (en) * 2006-11-21 2012-05-23 国际商业机器公司 FPGAFPGA, FPGA configuration, debug system and method
WO2008134884A1 (en) * 2007-05-03 2008-11-13 Icera Canada ULC System and method for transceiver control of peripheral components
US8565119B2 (en) * 2009-04-14 2013-10-22 Schweitzer Engineering Laboratories Inc Network discovery and data transfer using SNMP in an electric power transmission or distribution system
US8261357B2 (en) * 2009-10-14 2012-09-04 Schweitzer Engineering Laboratories, Inc. Systems and methods for license entitlement key distribution
US8509101B2 (en) * 2009-10-14 2013-08-13 Schweitzer Engineering Laboratories Inc Systems and methods for a configurable communication device
US8417867B2 (en) 2010-11-17 2013-04-09 Xilinx, Inc. Multichip module for communications
US8629691B2 (en) * 2011-05-17 2014-01-14 Altera Corporation Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device
CN103812800A (en) * 2012-11-09 2014-05-21 辉达公司 Wireless base station device and communication system comprising the same
US9967135B2 (en) 2016-03-29 2018-05-08 Schweitzer Engineering Laboratories, Inc. Communication link monitoring and failover
US10573598B2 (en) 2017-09-28 2020-02-25 Xilinx, Inc. Integration of a programmable device and a processing system in an integrated circuit package
CN113098518B (en) * 2021-03-29 2023-04-11 成都振芯科技股份有限公司 Fixed time delay serial transceiver with coding and decoding functions and control method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907566A (en) * 1997-05-29 1999-05-25 3Com Corporation Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array

Family Cites Families (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698051A (en) * 1980-01-07 1981-08-07 Hitachi Ltd Signal transmitting device of lsi component
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5142625A (en) 1985-06-12 1992-08-25 Minolta Camera Kabushiki Kaisha One-chip microcomputer including a programmable logic array for interrupt control
US5072418A (en) 1989-05-04 1991-12-10 Texas Instruments Incorporated Series maxium/minimum function computing devices, systems and methods
US4855669A (en) 1987-10-07 1989-08-08 Xilinx, Inc. System for scan testing of logic circuit networks
US4878174A (en) 1987-11-03 1989-10-31 Lsi Logic Corporation Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions
JPH02235156A (en) 1989-03-08 1990-09-18 Canon Inc Information processor
US5274570A (en) 1989-05-22 1993-12-28 Mazda Motor Corporation Integrated circuit having metal substrate
JPH03210649A (en) 1990-01-12 1991-09-13 Fujitsu Ltd Microcomputer and its bus cycle control method
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5347181A (en) 1992-04-29 1994-09-13 Motorola, Inc. Interface control logic for embedding a microprocessor in a gate array
WO1993025968A1 (en) 1992-06-10 1993-12-23 Furtek Frederick C A modular computer based on reconfigurable logic
US5671355A (en) 1992-06-26 1997-09-23 Predacomm, Inc. Reconfigurable network interface apparatus and method
US5412782A (en) * 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
US5339262A (en) 1992-07-10 1994-08-16 Lsi Logic Corporation Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC
US5311114A (en) 1992-10-27 1994-05-10 Seeq Technology, Incorporated Apparatus and method for full-duplex ethernet communications
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
GB9303084D0 (en) 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH0736858A (en) 1993-07-21 1995-02-07 Hitachi Ltd Signal processor
US5457410A (en) 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
WO1995004402A1 (en) 1993-08-03 1995-02-09 Xilinx, Inc. Microprocessor-based fpga
US5740404A (en) 1993-09-27 1998-04-14 Hitachi America Limited Digital signal processor with on-chip select decoder and wait state generator
US5500943A (en) 1993-11-02 1996-03-19 Motorola, Inc. Data processor with rename buffer and FIFO buffer for in-order instruction completion
WO1995016993A1 (en) 1993-12-13 1995-06-22 Lattice Semiconductor Corporation Application specific modules in a programmable logic device
US5742179A (en) 1994-01-27 1998-04-21 Dyna Logic Corporation High speed programmable logic architecture
US5574942A (en) 1994-02-28 1996-11-12 Intel Corporation Hybrid execution unit for complex microprocessor
US5543640A (en) 1994-03-15 1996-08-06 National Semiconductor Corporation Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module
US5600845A (en) 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
US5732250A (en) 1994-09-15 1998-03-24 Intel Corporation Multi-function microprocessor wait state mechanism using external control line
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5737631A (en) 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
EP0823091A1 (en) 1995-04-28 1998-02-11 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US5701091A (en) * 1995-05-02 1997-12-23 Xilinx, Inc. Routing resources for hierarchical FPGA
GB9508931D0 (en) 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
WO1997003444A1 (en) 1995-07-10 1997-01-30 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
US5594367A (en) * 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic
US6175952B1 (en) 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
KR19990071991A (en) 1996-10-10 1999-09-27 파레 호세 마리아 인센서 Process for prototyping of mixed-signal applications and field programmable systems on chip for application of these processes
US6317860B1 (en) 1996-10-28 2001-11-13 Altera Corporation Electronic design automation tool for display of design profile
US5889788A (en) 1997-02-03 1999-03-30 Motorola, Inc. Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
US6172990B1 (en) 1997-06-19 2001-01-09 Xaqti Corporation Media access control micro-RISC stream processor and method for implementing the same
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US5874834A (en) 1997-03-04 1999-02-23 Xilinx, Inc. Field programmable gate array with distributed gate-array functionality
US6011407A (en) 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US5995424A (en) 1997-07-16 1999-11-30 Tanisys Technology, Inc. Synchronous memory test system
US6020755A (en) 1997-09-26 2000-02-01 Lucent Technologies Inc. Hybrid programmable gate arrays
US6279045B1 (en) 1997-12-29 2001-08-21 Kawasaki Steel Corporation Multimedia interface having a multimedia processor and a field programmable gate array
US6091962A (en) * 1998-01-30 2000-07-18 Motorola, Inc. Method and apparatus for re-establishing a communication in a wireless communication system
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6115763A (en) * 1998-03-05 2000-09-05 International Business Machines Corporation Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit
US6237124B1 (en) * 1998-03-16 2001-05-22 Actel Corporation Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array
US6178541B1 (en) 1998-03-30 2001-01-23 Lsi Logic Corporation PLD/ASIC hybrid integrated circuit
US6594275B1 (en) * 1998-04-03 2003-07-15 Texas Instruments Incorporated Fibre channel host bus adapter having multi-frequency clock buffer for reduced power consumption
US6163166A (en) 1998-05-27 2000-12-19 Altera Corporation Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6480989B2 (en) 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6467009B1 (en) 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6343207B1 (en) 1998-11-03 2002-01-29 Harris Corporation Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor
US6154051A (en) 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device
US6181163B1 (en) 1999-01-21 2001-01-30 Vantis Corporation FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals
US6356987B1 (en) 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
US6301696B1 (en) 1999-03-30 2001-10-09 Actel Corporation Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template
US6211697B1 (en) 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6272451B1 (en) 1999-07-16 2001-08-07 Atmel Corporation Software tool to allow field programmable system level devices
JP3512166B2 (en) 1999-11-26 2004-03-29 松下電器産業株式会社 How to set up a programmable logic device
US6519753B1 (en) 1999-11-30 2003-02-11 Quicklogic Corporation Programmable device with an embedded portion for receiving a standard circuit design
US6588006B1 (en) 1999-12-16 2003-07-01 Lsi Logic Corporation Programmable ASIC
US6434735B1 (en) 1999-12-16 2002-08-13 Lsi Logic Corporation Method for programming an FPGA and implementing an FPGA interconnect
US6539508B1 (en) 2000-03-15 2003-03-25 Xilinx, Inc. Methods and circuits for testing programmable logic
US6587995B1 (en) 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality
US6535043B2 (en) 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same
US6353331B1 (en) 2000-07-10 2002-03-05 Xilinx, Inc. Complex programmable logic device with lookup table
US6507942B1 (en) 2000-07-11 2003-01-14 Xilinx , Inc. Methods and circuits for testing a circuit fabrication process for device uniformity
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US6611951B1 (en) 2000-11-30 2003-08-26 Lsi Logic Corporation Method for estimating cell porosity of hardmacs
US6522167B1 (en) 2001-01-09 2003-02-18 Xilinx, Inc. User configurable on-chip memory system
US6541991B1 (en) 2001-05-04 2003-04-01 Xilinx Inc. Interface apparatus and method for testing different sized ball grid array integrated circuits
US6578174B2 (en) 2001-06-08 2003-06-10 Cadence Design Systems, Inc. Method and system for chip design using remotely located resources
US6601227B1 (en) 2001-06-27 2003-07-29 Xilinx, Inc. Method for making large-scale ASIC using pre-engineered long distance routing structure
US6510548B1 (en) 2001-08-03 2003-01-21 Xilinx, Inc. Method for providing pre-designed modules for programmable logic devices
US7068650B1 (en) * 2001-09-06 2006-06-27 Cisco Technology, Inc. Apparatus and method for SerDes rate matching using symbol interleaving
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5907566A (en) * 1997-05-29 1999-05-25 3Com Corporation Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"MIXTURE OF FIELD AND FACTORY PROGRAMMED LOGIC CELLS IN A SINGLE DEVICE", 1 April 1995, IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, PAGE(S) 499, ISSN: 0018-8689, XP000516233 *
AGERE SYSTEMS: "ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver Data Sheet", August 2001, XP002292334 *

Also Published As

Publication number Publication date
JP2005519518A (en) 2005-06-30
CA2478023C (en) 2014-07-15
WO2003075477A2 (en) 2003-09-12
EP1504537B1 (en) 2009-06-17
CA2478023A1 (en) 2003-09-12
DE60328016D1 (en) 2009-07-30
US7187709B1 (en) 2007-03-06
EP1504537A2 (en) 2005-02-09
JP4263105B2 (en) 2009-05-13

Similar Documents

Publication Publication Date Title
WO2003075477A3 (en) High speed configurable transceiver architecture
AU2001243392A1 (en) An integrated circuit architecture with standard blocks
AU2002305806A1 (en) Integrated circuit design with library cells
GB9818377D0 (en) An integrated circuit with multiple processing cores
AU2002340506A1 (en) Integrated circuit package including miniature antenna
WO2002086969A3 (en) Non-optical signal isolator
AU2001251089A1 (en) Cooling module incorporating communication port and related circuits
CA2458060A1 (en) Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
WO2006071570A3 (en) Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an fpga
AU2003287421A1 (en) Integrated circuit having multiple modes of operation
EP1746727A3 (en) Multi-channel communication circuitry for programmable logic device integrated circuits and the like
WO2006028828A3 (en) Integrated circuit with shared hotsocket architecture
EP1753143A3 (en) Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
EP1835703A4 (en) Electronic device
WO2003075189A3 (en) An interconnect-aware methodology for integrated circuit design
WO2004030034A3 (en) Test mode control circuit for reconfiguring a device pin of an integrated circuit chip
DE69217524T2 (en) Test circuit provided in digital logic circuits
WO2005048454A3 (en) Multiplexer circuits
DE50003281D1 (en) CIRCUIT WITH BUILT-IN SELF-TEST
AU2002257622A1 (en) Device for crossing optical beams, in particular in an integrated optical circuit
DE50107889D1 (en) Integrated circuit with self-test circuit
AU2001235923A1 (en) An integrated circuit chip for use as an electronic thermostat
WO2003038647A3 (en) Packaged combination memory for electronic devices
WO2007067423A8 (en) Integrated circuit with configurable bypass capacitance
AU2003295372A1 (en) Integrated circuit with automatic pin-strapping configuration

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CA JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003711327

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2478023

Country of ref document: CA

Ref document number: 2003573797

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2003711327

Country of ref document: EP