WO2003077119A1 - Hardware implementation of the secure hash standard - Google Patents
Hardware implementation of the secure hash standard Download PDFInfo
- Publication number
- WO2003077119A1 WO2003077119A1 PCT/US2003/007000 US0307000W WO03077119A1 WO 2003077119 A1 WO2003077119 A1 WO 2003077119A1 US 0307000 W US0307000 W US 0307000W WO 03077119 A1 WO03077119 A1 WO 03077119A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data path
- integrated circuit
- address
- memory
- controller
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000003044 adaptive effect Effects 0.000 description 6
- 101100457843 Schizosaccharomyces pombe (strain 972 / ATCC 24843) tit1 gene Proteins 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Definitions
- the present invention generally relates to the secure hash standard. More specifically, the present invention relates to a method and system for implementing a secure hash algorithm (SHA-1) specified by the secure hash standard with hardware resources.
- the SHA-1 generally operates as follows. The SHA-1 takes as input a message of maximum length which is less than 2 64 bits. The message is padded, if necessary, to render the total message length a multiple of 512. The message is then converted into 512- bit blocks. The 512-bit blocks are processed sequentially and the cumulative results represent a 160-bit message digest.
- the SHA-1 performs eighty rounds of processing for each 512-bit block. For each of four groups of twenty rounds, the SHA-1 uses one of four Boolean functions and one of four constant values, to be further described below. Once all eighty processing rounds are completed, five 32-bit intermediate variables are updated. The process is then repeated for the next 512-bit block. Once all the 512-bit blocks are processed, the final, cumulative values of the five intermediate variables represent the 160-bit message digest. The details with respect to the processing of the 512-bit blocks will be further described below. [05] As mentioned above, the SHA-1 converts the message into 512-bit blocks and then processes the 512-bit blocks one at a time.
- each 512-bit block to be processed is divided into sixteen (16) longwords Wo, Wi , ... , W 15 , where Wo is the leftmost longword.
- Each longword is thirty-two (32) bits in length.
- the SHA-1 uses a five longword circular buffer to maintain the five 32-bit intermediate variables, a, b, c, d and e.
- H 512-bit blocks takes place as follows:
- the message digest is the 160-bit string represented by the five (5) longwords, a, b, c, d and e.
- the foregoing is a brief description of the SHA-1. Details with respect to the operations of the SHA-1 are well understood. [12] The SHA-1 is typically implemented using software.
- a person of ordinary skill in the art will know how to implement the SHA-1 using software.
- Using software to implement the SHA-1 has a number of shortcomings. For example, it is relatively easy to break into a software program designed to implement the SHA-1 thereby revealing that the SHA-1 is used for encrypting messages. By ascertaining the type of encryption algorithm that is being used to encrypt messages, a hacker may then successfully decrypt the message digests to obtain the messages.
- an integrated circuit for implementing the secure hash algorithm includes a data path and a controller controlling operation of the data path.
- the data path is capable of handling each round of processing reiteratively.
- the data path includes a data multiplexor, an address multiplexor, a memory, a first processing multiplexor, a second processing multiplexor, a first register, a second register, a shifter and an arithmetic logic unit.
- the controller includes an address control module and a finite state machine.
- the address control module further includes a pico code ROM and a number of counters.
- the address control module uses a pico code memory address, the state of the finite state machine and various counter bits to generate a physical memory address and appropriate control bits to control the operation of the data path.
- FIG. 1 is a simplified block diagram illustrating an exemplary embodiment of a data path for data processed pursuant to the SHA-1 in accordance with the present invention
- FIG. 2 is a simplified block diagram illustrating an exemplary embodiment of a controller used to control operation of the data path shown in Fig. 1 in accordance with the present invention
- FIG. 3 is an illustrative diagram showing an exemplary embodiment of a data structure used to store data for controlling operation of the controller and the data path in accordance with the present invention
- FIG. 4 is an illustrative diagram showing an exemplary embodiment of a memory map in accordance with the present invention.
- FIG. 5 is an illustrative diagram showing an exemplary embodiment of pico code for memory address generation in accordance with the present invention.
- FIGs. 6a-c are selected illustrative timing diagrams showing operations of the respective components of the data path in accordance with the present invention.
- an integrated circuit is provided to implement the Secure Hash Algorithm (SHA-1) specified by the Secure Hash Standard as promulgated by the National Institute of Standards and Technology.
- SHA-1 Secure Hash Algorithm
- FIG. 1 is a simplified block diagram illustrating the data path of data processed pursuant to the SHA-1 in accordance with the present invention. As shown in Fig.
- the data path 10 includes a data multiplexor 12, an address multiplexor 14, a memory 16, a first processing multiplexor 18, a first register 20, a second register 22, a shifter 24, a second processing multiplexor 26 and an arithmetic logic unit 28. More specifically, the data multiplexor 12 and the address multiplexor 14 are coupled to the memory 16 to control the output of the memory 16. The output from the memory 16, in turn, is coupled to the first and second processing multiplexors 18, 26. In addition, the first processing multiplexor 18 also receives the output of the arithmetic logic unit 28. The output of the first processing multiplexor 18 is coupled to the first register 20. The output of the first register 20 is coupled to the shifter 24.
- the output of the shifter 24 is provided to both the arithmetic logic unit 28 and the data multiplexor 12. Furthermore, the output of the arithmetic logic unit 28 is also fed to the second register 22. The output of the second register 22 is coupled to the second processing multiplexor 26. The output of the second processing multiplexor 26 is provided to the arithmetic logic unit 28. It should be noted that the data path 10 does not address issues such as messaging padding, endianness, input/output etc. A person of ordinary skill in the art will be able to address these issues.
- the data path 10 shown in Fig. 1 is controlled by a controller.
- An exemplary embodiment of the controller is shown in Fig. 2.
- the controller 30 includes a finite state machine 32 and an address control module 34.
- the finite state machine 32 functions in cooperation with the address control module 34 to control the data path 10.
- the address control module 34 is comprised of a number of components, including a first mod-16 counter 36, a second mod-16 counter 38, a third mod-16 counter 40, a mod-5 counter 42, a ROM 44 and a memory address generator 46.
- the output of the second mod-16 counter 38 is coupled to the third mod-16 counter 40, the mod-5 counter 42 and the ROM 44.
- the output of the mod-5 counter 42 is provided to the first mod-16 counter 36.
- the ROM 44 is coupled to the memory address generator 46.
- the respective outputs of the ROM 44 and the memory address generator 46 are provided to the data path 10.
- the finite state machine 32 is capable of assuming a number of states. In the exemplary embodiment shown in Fig. 2, the finite state machine 32 can assume one of four (4) different states. The inputs, outputs and respective logic conditions that produce the different states for the finite state machine 32 are shown in Fig. 2.
- the data stored within the ROM 44 is organized in a pico code format.
- Fig. 3 shows an exemplary embodiment of the Pico code format.
- the data stored within the ROM 44 is used to control operation of the controller and the data path 10. More specifically, the ROM 44 contains a number of pico codes. Each pico code is designed to direct the controller and the data path 10 to perform a specific operation. As shown in Fig. 3, each Pico code has a length of sixteen (16) bits. Bits (0-7) and (13) are used to control the operation of the various components of the data path 10.
- bits (0) and (1) are respectively used to control the first and second registers 20, 22; bits (2) and (3) are respectively used to control the first and second processing multiplexor 18, 26; bits (4) and (5) are used to control the arithmetic logic unit 28; bits (6) and (7) are used to control the shifter (24); bits (8-12) are used to represent the pico code memory address which is then used to generate the physical memory address for accessing the memory 16; and bit (13) is used to control the type of operation to be performed in the memory 16.
- the memory 16 is organized based on a memory map.
- Fig. 4 shows an exemplary embodiment of the memory map. Referring to Fig. 4, the physical memory address, A[4:0], is five (5) bits in length.
- the use of the 5-bit physical memory address means that there are thirty-two (32) addressable words in the memory 16. Each word is preferably sixteen (16) bits in length.
- the pico code memory address is used to generate the physical memory address for accessing the memory 16.
- the physical memory address is generated from the pico code memory address, the state of the finite state machine 32, and various counter bits from the second mod-16 counter 38.
- Fig. 5 shows an exemplary embodiment of the pico code memory address used for generating the physical memory address to access the memory 16.
- A[4:0] used to access the memory 16 is generated from the pico code memory address in the following manner.
- A[4] is set to "0"
- A[3:0] is determined as follows: (constant + 1 (mod 16)) mod 16, where the constant is: pico code memory address bits [8] [9] constant
- A[l] are set to "1".
- A[4] is set to "1" and A[3] is set to "0".
- FIG. 6a is a timing diagram illustrating the operation of various components of the data path 10 when initializing the intermediate variables (a, b, c, d and e) with the initialization constants (Ho-EL ;
- Fig. 6c is a timing diagram illustrating the operation of various components of the data path 10 for the intermediate variable update round.
- the data path 10 and the controller including the finite state machine 32 and the address control module 34 are implemented as part of an integrated circuit using hardware.
- the integrated circuit can be embedded in a mobile communication device, such as a mobile phone, where encryption and decryption functions are desired for security purposes.
- the data path 10 and the controller can be implemented using reconfigurable hardware resources within an adaptive computing architecture. Details relating to the adaptive computing architecture and how reconfigurable hardware resources are used to implement functions on an on-demand basis are disclosed in U.S. patent application serial no.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003217991A AU2003217991A1 (en) | 2002-03-05 | 2003-03-05 | Hardware implementation of the secure hash standard |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/093,156 US7489779B2 (en) | 2001-03-22 | 2002-03-05 | Hardware implementation of the secure hash standard |
US10/093,156 | 2002-03-05 |
Publications (1)
Publication Number | Publication Date |
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WO2003077119A1 true WO2003077119A1 (en) | 2003-09-18 |
Family
ID=27804197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/007000 WO2003077119A1 (en) | 2002-03-05 | 2003-03-05 | Hardware implementation of the secure hash standard |
Country Status (3)
Country | Link |
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US (2) | US7489779B2 (en) |
AU (1) | AU2003217991A1 (en) |
WO (1) | WO2003077119A1 (en) |
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EP1814026A2 (en) * | 2005-12-29 | 2007-08-01 | Intel Corporation | Method and apparatus to attain direct communication between accelerator and instruction sequencer |
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TWI238636B (en) * | 2003-06-19 | 2005-08-21 | Yen-Fu Liu | Operation device and method of fast secure hash algorithm |
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US9489318B2 (en) | 2006-06-19 | 2016-11-08 | Broadcom Corporation | Method and system for accessing protected memory |
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US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
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JP6238774B2 (en) | 2013-02-21 | 2017-11-29 | キヤノン株式会社 | Hash value generator |
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Also Published As
Publication number | Publication date |
---|---|
US7489779B2 (en) | 2009-02-10 |
US20090161863A1 (en) | 2009-06-25 |
US20030135743A1 (en) | 2003-07-17 |
AU2003217991A1 (en) | 2003-09-22 |
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