WO2003077315A3 - Multi-row leadframe - Google Patents

Multi-row leadframe Download PDF

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Publication number
WO2003077315A3
WO2003077315A3 PCT/US2003/005220 US0305220W WO03077315A3 WO 2003077315 A3 WO2003077315 A3 WO 2003077315A3 US 0305220 W US0305220 W US 0305220W WO 03077315 A3 WO03077315 A3 WO 03077315A3
Authority
WO
WIPO (PCT)
Prior art keywords
terminals
row
leadframe
paddle ring
surrounds
Prior art date
Application number
PCT/US2003/005220
Other languages
French (fr)
Other versions
WO2003077315A2 (en
Inventor
Man Hon Cheng
Wai Wong Chow
Fei Ying Wong
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2003213173A priority Critical patent/AU2003213173A1/en
Priority to JP2003575421A priority patent/JP2005519485A/en
Priority to KR1020047013939A priority patent/KR100930841B1/en
Priority to EP03709219A priority patent/EP1481422A2/en
Publication of WO2003077315A2 publication Critical patent/WO2003077315A2/en
Publication of WO2003077315A3 publication Critical patent/WO2003077315A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01Chemical elements
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    • H01L2924/102Material of the semiconductor or solid state bodies
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).
PCT/US2003/005220 2002-03-06 2003-02-19 Multi-row leadframe WO2003077315A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2003213173A AU2003213173A1 (en) 2002-03-06 2003-02-19 Multi-row leadframe
JP2003575421A JP2005519485A (en) 2002-03-06 2003-02-19 Multi-row lead frame
KR1020047013939A KR100930841B1 (en) 2002-03-06 2003-02-19 Multi-column leadframe
EP03709219A EP1481422A2 (en) 2002-03-06 2003-02-19 Multi-row leadframe

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/092,683 2002-03-06
US10/092,683 US6838751B2 (en) 2002-03-06 2002-03-06 Multi-row leadframe

Publications (2)

Publication Number Publication Date
WO2003077315A2 WO2003077315A2 (en) 2003-09-18
WO2003077315A3 true WO2003077315A3 (en) 2004-01-08

Family

ID=27787865

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/005220 WO2003077315A2 (en) 2002-03-06 2003-02-19 Multi-row leadframe

Country Status (8)

Country Link
US (1) US6838751B2 (en)
EP (1) EP1481422A2 (en)
JP (1) JP2005519485A (en)
KR (1) KR100930841B1 (en)
CN (1) CN100350601C (en)
AU (1) AU2003213173A1 (en)
TW (1) TWI237878B (en)
WO (1) WO2003077315A2 (en)

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