WO2003090048A2 - Method and apparatus for communicating securely with a token - Google Patents
Method and apparatus for communicating securely with a token Download PDFInfo
- Publication number
- WO2003090048A2 WO2003090048A2 PCT/US2003/010246 US0310246W WO03090048A2 WO 2003090048 A2 WO2003090048 A2 WO 2003090048A2 US 0310246 W US0310246 W US 0310246W WO 03090048 A2 WO03090048 A2 WO 03090048A2
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- WO
- WIPO (PCT)
- Prior art keywords
- bus
- token
- request
- trusted
- chipset
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
- G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
Definitions
- the Trusted Platform Computing Alliance (TPCA) in the TPCA's Main Specification, Version 1.1a, dated 1 December 2001 describes a Trusted Platform Module (TPM) or token that provides increased confidence and that enables enhancements of existing services and new services.
- the token supports auditing and logging of softw.are processes, platform boot integrity, file integrity, and software licensing.
- the token provides a protected information store for the platform (e.g., a personal computer), and can be used to attest to the identity of the platform as defined by the hardware that is present (e.g. processors, chipsets, firmware, etc.) on the platform.
- the secure features of the token encourage third parties to grant the platform access to information that would otherwise be denied.
- the token contains an isolated computing engine whose processes can be trusted because they cannot be altered. These processes and the binding of the subsystem to the platform combine to reliably measure and report the state of the main computing environment inside the platform.
- the token provides a root of trust for the booting of the platform.
- a local or remote entity may query the token to reliably obtain security information a nd d ecide w hether t he p latform' s behavior e nables i 11 o b e t rusted for t he intended purpose. Confidence in the loading of software is improved, because the token can attest to the current state of the operating system.
- the token may include several registers, that may be used to store encrypted digests of files, including software programs, which may be retrieved and authenticated. Information written to and read from the token is to be secure in order for third parties to trust the platform.
- the mapping of the registers as traditional Input/Output (I/O) mapped registers is undesirable as a device on the same interface as the token may be programmed to map to the same I/O addresses, thereby compromising the security of the token.
- FIG. 1 illustrates a computing device comprising a token according to one embodiment of the invention.
- FIG. 2 illustrates a flow diagram for communicating with a token according to one embodiment of the invention.
- FIG. 3 illustrates a token write cycle according to one embodiment of the invention.
- FIG. 4 illustrates a token read cycle according to one embodiment of the invention.
- FIG. 5 illustrates a computing device comprising a chipset with a dual ported register according to one embodiment of the invention.
- FIG. 6 illustrates a flow diagram for writing to a token using dual ported registers according to one embodiment of the invention.
- FIG. 7 illustrates a flow diagram for reading from a token using dual ported registers according to one embodiment of the invention.
- references in the specification to "one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- Coupled may mean that two or more elements are in direct physical or electrical contact.
- coupled may also mean that two or more elements .are not in direct contact with each other, but yet still co-operate or interact with each other.
- Figure 1 illustrates a computing device comprising a token according to one embodiment of the invention.
- An example computing device 100 shown in Figure 1 may comprise one or more processors 110, a chipset 120, and a token 155.
- the processors 110 may support one or more operating modes such as, for example, a real mode, a protected mode, a virtual 8086 mode, and/or a virtual machine mode (VMX mode). Further, the processors 110 may support one or more privilege levels or rings in each of the supported operating modes. In general, the operating modes and privilege levels of a processor 110 define the instructions available for execution and the effect of executing such instructions. More specifically, a processor 110 may be permitted to e xecute certain p rivileged i nstructions o nly if t he p rocessor l lO is in an appropriate mode and/or privilege level. In one embodiment of the invention, a processor 110 may comprise a microcode memory 102 to store trusted microcode.
- Processors 110 are coupled to chipset 120 via a processor bus 164.
- Figure 1 illustrates two processors 110 connected to chipset 120 via a common processor bus 164
- alternate embodiments of the invention may have multiple processors 110 with each processor 110 connected to chipset 120 directly by, e.g., a point-to-point processor bus.
- the processor bus 164 is a front side bus (FSB) as used with Intel® corporation's Pentium 4 processor.
- Chipset 120 may comprise one or more integrated circuit packages or chips.
- chipset 120 includes processor bus interface (I/F) logic 104 coupled between processor bus 164 and decoder logic 103.
- chipset 120 includes memory bus interface logic 106 to couple the chipset 120 to a memory 130 via a memory bus 166.
- memory 130 includes trusted code 131.
- trusted code 131 may be program code and/or data that is authenticated by a processor 110 and stored as trusted code 102 in a processor 110.
- chipset 120 includes Input/Output (I/O) bus interface logic 112 connected to I/O devices 113 via, e.g., I/O bus 168.
- I/O Input/Output
- a second I/O bus interface logic 107 couples chipset 120 to a network controller 140 using, e.g., I/O bus 169.
- network controller 140 connects computing device 100 to one or more remote computing devices 119 via a network 122.
- network controller 140 may comprise a 10 Mb or 100 Mb Ethernet controller, a cable modem, a digital subscriber line (DSL) modem, plain old telephone service (POTS) modem, etc. to couple the computing device 100 to one or more remote computing devices 119.
- a third I/O bus interface logic 108 couples chipset 120 to one or more storage devices 114 using, e.g., a I/O bus 171.
- a graphics bus interface logic 109 couples chipset 120 to a graphics controller 115 via a graphics bus 174. Graphics controller 115 is coupled to display device 116.
- I/O bus I/F logic 105 couples chipset 120 to token 155 using an I/O bus 162.
- I/O bus 162 may be a low pin count (LPC) bus.
- Token 155 comprises one or more registers 156, bus master engine 157, and I/O bus interface logic 158.
- a super I/O controller 118 is also connected to I/O bus 162 that is coupled to, e.g., a keyboard, a mouse etc.
- Figure 2 illustrates a flow diagram for communicating with a token according to one embodiment of the invention.
- a processor 110 issues a read or write request to chipset 120.
- chipset 120 receives the request from processor 110 via processor bus 164.
- chipset 120 decodes the address in the request. In one embodiment of the invention, in addition to decoding the address the chipset 120 decodes the cycle type in the request.
- the processor bus I/F logic 104 determines whether the request is a trusted request. In one embodiment of the invention, the processor bus I/F logic 104 determines this by determining whether the decoded address is within the trusted configuration space, and by determining whether a value in a request identity field in the request is a value that indicates the request is a trusted request.
- the processor bus I/F logic 104 determines whether the request targets token 155. If the processor bus I/F logic 104 determines that the request targets token 155 e.g., by determining the offset range is within the specified range, at 235 the processor bus I/F logic 104 forwards the request to the I/O bus I/F logic 105. If the request does not target the token 155, at 255, the chipset 120 aborts the request. At 240, the I/O bus I/F logic 105 forwards the request over I/O bus 162 to I/O bus interface logic 158.
- the I/O bus interface logic 158 uses a token cycle that includes a code that ensures that other devices on the I/O bus ignore the forwarded request, one embodiment of the invention, the code comprises a reserved binary number that is ignored by other devices on the I/O bus 162.
- the I/O bus I/F logic 105 ensures that information in the request is suppressed on one or more other busses except on the I/O bus 162.
- the information in the request may be suppressed by sending false data on one or more busses other than the I/O bus 162 to suppress information from the request echoed on one or more other busses.
- both the address and the data contained in the echoed code may be distorted e.g., by writing a series of invalid bits in the address and data fields.
- the request is completed.
- processor bus interface (I/F) logic 104 comprises buffers and logic circuits to receive a trusted cycle (e.g., a read, or a write cycle) from a processor 110.
- a trusted cycle e.g., a read, or a write cycle
- the processor bus I/F logic 104 identifies the trusted cycle by identifying a unique value in a field in the trusted cycle.
- the trusted cycle may address a location in a trusted configuration space.
- a trusted cycle may comprise a standard memory read or write cycle to the configuration space provided that the chipset 120 has been preprogrammed to allow standard memory read or write cycles.
- the preprogramming of the chipset 120 is done using a trusted memory cycle to execute the program that preprograms the chipset 120.
- the processor bus I/F logic 104 sends the trusted cycle to decoder logic 103. Decoder logic 103 decodes the trusted cycle and determines whether the address in the trusted cycle is a valid address in token 155. If the address in the trusted cycle is a valid address in token 155, the trusted cycle or the information in the trusted cycle is sent to I/O bus I/F logic 105. However, if the address in the trusted cycle is not a valid address, in one embodiment of the invention, the decoder logic 103 may inform the processor bus I/F logic 104 to abort the trusted cycle.
- processor bus I/F logic 104 discards the trusted cycle if the decoded address is not a valid address.
- the processor bus I/F logic 104 may return some arbitrary data, e.g., a series of 0's or l's or may reset computing device 100.
- Other processor cycles may also be received by processor bus interface logic 104 e.g., a non trusted memory cycle or a non trusted I/O.
- Processor bus I/F logic 104 may be coupled to other bus interface logic e.g., to memory bus I/F logic 106. So also the other bus I/F logic may be connected to each other via busses in order to communicate with each other and to communicate between the different peripherals connected to the bus I/F logic as needed.
- processor bus interface logic 104 When non trusted processor cycles are received by processor bus interface logic 104, they are analyzed by the processor bus interface logic 104 and sent to the appropriate bus interface logic.
- the processor bus interface logic 104 may respond to the processor 110 from which the trusted cycle or other processor cycles are received with appropriate acknowledgment replies, data cycles, or other cycles.
- the I/O bus I/F logic 105 When I/O bus I/F logic 105 receives the trusted cycle, or the information therein, the I/O bus I/F logic 105 generates a token cycle (i.e., a token read cycle or a special write cycle).
- a token cycle i.e., a token read cycle or a special write cycle.
- the token cycle to the token 155 is not to appear on one or more busses other than the I/O bus 162.
- the token cycle is not to appear on I/O bus 168, I/O bus 169 or I/O 171.
- the token cycle that is generated by the I/O bus interface logic 105 is encoded such that other devices on the I/O bus 162, e.g., the super I/O controller 118 ignore the information contained in the token cycle.
- the I/O bus interface logic 105 receives the trusted cycle and while generating the token cycle sends false data or distorted data on one or more other busses to prevent any information of the token cycle from being echoed and therefore observed on another bus. Only the token cycle sent to token 155, and in particular the I/O bus 162, has the information received from processor bus interface logic 104. So also the information retrieved from token 155 is sent only to processor 110 via processor bus 164.
- FIG. 5 illustrates a computing device comprising a chipset with a dual ported register according to one embodiment of the invention, h one embodiment of the invention, chipset 120 comprises dual ported registers 111 that couples processor bus I/F logic 104 to I/O bus I/F logic 105.
- Figure 6 illustrates a flow diagram for writing to a token using the dual ported registers according to one embodiment of the invention.
- a processor 110 issues a read or write request to chipset 120.
- chipset 120 receives the request from processor 110 via processor bus 164.
- chipset 120 decodes the address in the request.
- the chipset 120 in addition to decoding the address the chipset 120 decodes the cycle type in the request.
- the processor bus I/F logic 104 determines whether the request is a trusted request.
- the processor bus I/F logic 104 determines this by determining whether the decoded address is within the trusted configuration space, and by determining whether a value in a request identity field in the request is a value that indicates the request is a trusted request. If the request is not a trusted request, at 625, the chipset 120 aborts the request. At 630 the processor bus I/F logic 104 determines whether the request targets token 155. If the processor bus I/F logic 104 determines that the request targets token 155 e.g., by determining the offset range is within the specified range, at 635 the chipset 120 latches the data in the request.
- the chipset 120 aborts the request.
- the processor 110 may write to the dual ported registers 111 one or more values for token 155 using for example a standard write transaction.
- the processor 110 may then generate a standard I/O write to the token 155, informing the token 155 to fetch the one or more values from the dual ported registers 111 in chipset 120.
- the token 155 may become an I/O bus master (using the bus master engine 157) and read the one or more values, written by the processor 110, from dual ported registers 111.
- the token 155 reads the one or more values from the dual ported registers 111 using a code to help ensure that other devices on the I/O bus 162 ignore the token's read cycle.
- the code comprises a reserved binary number that is ignored by other devices on the I/O bus 162. The read values are then stored by I/O bus I/F logic 158 to registers 156 in token 155. At 655 the request is completed.
- FIG. 7 illustrates a flow diagram for reading from a token using a dual ported register according to one embodiment of the invention.
- a processor 110 may generate a standard I/O write to token 155, informing the token 155 to write one or more values to dual ported registers 111.
- token 155 may become an I/O bus master (using the bus master engine 157) and write one or more values to dual ported registers 111.
- the I/O bus interface logic 158 uses a token cycle that includes a code that ensures that other devices on the I/O bus 162 ignore the write cycle.
- the code comprises a reserved binary number that is ignored by other devices on the I/O bus 162.
- the processor 110 issues a read or write request to chipset 120.
- chipset 120 receives the request from the processor 110 via processor bus 164.
- chipset 120 may decode the address in the request.
- the chipset 120 in addition to decoding the address the chipset 120 decodes the cycle type in the request.
- the processor bus I/F logic 104 determines whether the request is a trusted request.
- the processor bus I/F logic 104 determines this by determining whether the decoded address is within the trusted configuration space, and by determining whether a value in a request identity field in the request is a value that indicates the request is a trusted request. If the request is not a trusted request, at 730, the chipset 120 aborts the request. At 735, the processor bus I/F logic 104 determines whether the request targets token 155. If the processor bus I/F logic 104 determines that the request targets token 155 e.g., by determining the offset range is within the specified range, at 740 the chipset 120 provides the latched data to processor 110. If the request does not target the token 155, at 730, the chipset 120 aborts the request. At 740 the chipset 120 provides the latched data in the dual ported registers 111 to the processor 110.
- a memory hub comprises the memory bus interface logic 106 that couples memory 130 to the chipset 120.
- the MCH may include the graphics bus interface logic 109 that connects graphics controller 115 or an accelerated graphics port (AGP) (not shown).
- AGP accelerated graphics port
- Also coupled to the MCH may be an I/O controller hub (ICH).
- the ICH may include the I/O bus interface logic 105, and a plurality of I/O bus interface logic to connect the ICH to a plurality of I/O devices.
- all processor 110 cycles bound for the ICH are received by the MCH and decoded.
- the MCH forwards configuration space cycles (i.e., trusted cycles) to the ICH for address ranges that do not correspond to registers in the MCH.
- the address ranges that do not correspond to registers in the MCH are address ranges for token 155.
- the processor 110 trusted cycles for token 155 are normal memory read and write cycles with addresses that match the addresses on the processor bus 164 (i.e., with addresses within a trusted configuration space).
- the ICH ignores memory read and write cycles that address the trusted configuration space but originate from other than the MCH.
- FIG. 3 illustrates a token write cycle on I/O bus according to one embodiment of the invention
- a token write cycle 300 on I/O bus 162 is used to write information from processor 110 to token 155.
- the token write cycle 300 is a LPC write cycle.
- the token write cycle comprises a start field 305, cycle type + dir field 310, address (ADDR) field 315, data field 320, turn around (TAR) field 325, synchronous (sync) field 330, and a second turn around (TAR) field 335.
- the reserved bits in the start field 305 may be used, h one embodiment of the invention, the start field 305 may comprise reserved binary bits (binary numbers) in the range 0100-1110 and may be used to write to token 155.
- the reserved binary numbers in the start field of the token write cycle 300 are received only by the token 155 on I/O bus 162, and are ignored by other devices e.g., the super I/O controller 118 connected to the I/O bus 162.
- the other devices on the I/O bus 162 receive the start bits, as s oon a s t he s tart b its a re d ecoded b y t he o ther d evices t o i ndicate a r eserved b inary number, remainder of the token write cycle is ignored. Thus only the token 155 on the I/O bus 162 receives the data from processor 110.
- the embodiment described above uses the reserved bits in the start field of the LPC write cycle, other embodiments may use any other standard that has reserved bits in the start field.
- the I/O bus has one control line LFRAME# (not shown) that is used by the chipset 120 to start or stop the transfer of information to and from the token 155. h particular, the LFRAME# signal is asserted during the start field 305 of the token write cycle 300.
- the chipset 120, and in particular, the I/O bus interface logic 105 may drive data on the token write cycle 300, and then turn the bus around to monitor the token 155 for completion of the cycle. After sending the sync signal 330, the token 155 may then turn the bus around to the chipset 120, ending the cycle.
- the start field 305 indicates the start or stop of a token write cycle 300. All peripherals including token 155 may go to a state that monitors the VO bus 162 when LFRAME# is active. While LFRAME# is active, the start field 305 may take on many values. Generally, the start field 305 indicates a device number for bus masters, or "start/stop" indication for non-bus master cycles. Normally, peripherals ignore the data being transmitted if a reserved field e.g., 0001 or 0100-1100 is observed, and the data transmitted with the token write cycle 300 is ignored.
- a reserved field e.g., 0001 or 0100-1100
- a reserved binary number is used by the chipset 120 in the start field 305.
- token 155 decodes the reserved binary numbers in the start field it responds to the token write cycle 300, and may write the data contained in the token write cycle 300 to one or more of the registers in token 155. Therefore, when the token 155 decodes a start field with e.g., 0101 (a reserved binary number) it responds to the information being transmitted in the token write cycle 300.
- FIG. 4 illustrates a token read cycle on I/O bus according to one embodiment of the invention.
- a token read cycle 400 on I/O bus 162 is used to read information from token 155.
- the token read cycle 400 comprises a start field 405, cycle type + dir field 410, address (ADDR) field 415, turn around (TAR) field 420, synchronous (sync) field 425, a data field 430, and a second turn around (TAR) field 435.
- the reserved bits in the start field 405 may be used.
- the start field 405 may comprise reserved binary bits (binary numbers) in the range 0100-1110 or the binary number 0001, and may be used to read token 155.
- the reserved binary numbers in the start field of the token read cycle 400 are received only by the token 155 on I/O bus 162, and are ignored by other devices e.g., the super I/O controller 118 connected to the I/O bus 162. h one embodiment of the invention, if the other devices on the I/O bus 162 receive the start bits, as soon as the start bits are decoded by the other devices to indicate a reserved binary number, remainder of the token write cycle is ignored. Thus, only the token 155 on the I/O bus 162 receives the read instruction from processor 110.
- the I/O bus 162 has one control line LFRAME# (not shown) that is used by the chipset 120 to start or stop the tr,ansfer of information to and from the token 155.
- LFRAME# is asserted during the start field 505 of the token read cycle 500.
- the chipset 120, and in particul.ar, the I/O bus interface logic 105 may drive address information on the token read cycle 400, and then turn the bus around to monitor the token 155 for the requested data and the completion of the cycle. After sending the sync signal 425, the token 155 may then send the requested data 430, and turn the bus around to the chipset 120, ending the cycle.
- the embodiment described above uses the reserved bits in the start field of the LPC read cycle, other embodiments may use any other standard that has reserved bits in the start field.
- the start field 405 indicates the start or stop of a token read cycle 400. All peripherals including token 155 may go to a state that monitors the I/O bus 162 when LFRAME# is active. While LFRAME# is active, the start field 405 may take on many values. Generally, the start field 405 indicates a device number for bus masters, or "start/stop" indication for non-bus master cycles. Normally, peripherals ignore the data being transmitted if a reserved field e.g., 0001 or 0100-1100 is observed, and the data transmitted with the token read cycle 400 is ignored.
- a reserved field e.g., 0001 or 0100-1100
- a reserved binary number is used by the chipset 120 in the start field 405.
- token 155 decodes the reserved binary numbers in the start field it responds to the token read cycle 400, and obtain data from one or more registers in token 155 and encodes the data in the data field in token read cycle 400. Therefore, when the token 155 decodes a start field with e.g., 0101 (a reserved binary number) it responds to the information requested in the token read cycle 400.
Abstract
Description
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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AU2003223438A AU2003223438A1 (en) | 2002-04-15 | 2003-04-02 | Method and apparatus for communicating securely with a token |
KR1020047016461A KR100643814B1 (en) | 2002-04-15 | 2003-04-02 | Method and apparatus for communicating securely with a token |
CN038136864A CN1659496B (en) | 2002-04-15 | 2003-04-02 | Method and apparatus for communicating securely with a token |
EP03719568A EP1495391A2 (en) | 2002-04-15 | 2003-04-02 | Method and apparatus for communicating securely with a token |
Applications Claiming Priority (2)
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US10/122,544 US7076669B2 (en) | 2002-04-15 | 2002-04-15 | Method and apparatus for communicating securely with a token |
US10/122,544 | 2002-04-15 |
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WO2003090048A2 true WO2003090048A2 (en) | 2003-10-30 |
WO2003090048A3 WO2003090048A3 (en) | 2004-09-23 |
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PCT/US2003/010246 WO2003090048A2 (en) | 2002-04-15 | 2003-04-02 | Method and apparatus for communicating securely with a token |
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US (1) | US7076669B2 (en) |
EP (1) | EP1495391A2 (en) |
KR (1) | KR100643814B1 (en) |
CN (1) | CN1659496B (en) |
AU (1) | AU2003223438A1 (en) |
TW (1) | TWI267750B (en) |
WO (1) | WO2003090048A2 (en) |
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TW200401980A (en) | 2004-02-01 |
US7076669B2 (en) | 2006-07-11 |
US20030196088A1 (en) | 2003-10-16 |
KR100643814B1 (en) | 2006-11-10 |
CN1659496B (en) | 2010-05-26 |
WO2003090048A3 (en) | 2004-09-23 |
TWI267750B (en) | 2006-12-01 |
EP1495391A2 (en) | 2005-01-12 |
CN1659496A (en) | 2005-08-24 |
KR20050000512A (en) | 2005-01-05 |
AU2003223438A1 (en) | 2003-11-03 |
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