WO2003098848B1

WO2003098848B1 - Method and apparatus for optimizing distributed multiplexed bus interconnects

Info

Publication number: WO2003098848B1
Application number: PCT/US2003/015216
Authority: WO
Inventors: Michael J Meyer; Scott C Evans; Kamil Synek
Original assignee: Sonics Inc
Priority date: 2002-05-15
Filing date: 2003-05-14
Publication date: 2004-04-08
Also published as: US6880133B2; WO2003098848A3; AU2003229086A1; WO2003098848A2; AU2003229086A8; EP1506503A4; US7412670B2; US20050172244A1; JP2005526327A; JP4287368B2; US20030217347A1; EP1506503A2

Abstract

A method and apparatus for optimizing distributed multiplexed bus interconnects (Figure 2c).

Claims

AMENDED CLAIMS Received by the International Bureau on 31 December 2003 (31.12.2003) Claim 1-51 have been replaced by claims 1-18.CLAIMSWhat is claimed is:

1. A method of optimizing an interconnect, comprising: optimizing an amount of signaling wiring present within a distributed multiplexed bus interconnect by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the multiplexed bus interconnect transmits or receives signals from the multiplexed bus interconnect, wherein the multiplexed bus interconnect contains one or more multiplexers to route signals through the multiplexed bus interconnect.

2. The method of claim 1 , wherein a first distributed node connecting to the distributed multiplexed bus interconnect contains combining logic that combines input signals from other nodes and has an output port to a next node that has fewer wires than present on its input port, wherein the combining logic and the signaling wiring between the first node and the other nodes supplying the input signals are eliminated when the other nodes supplying the input signals do not transmit signals to the distributed multiplexed bus interconnect.

3. The method of claim 2, wherein the combining logic and the signaling wiring between the first node and the other nodes supplying the input signals are only eliminated when sub-nodes connecting to the other nodes supplying 15 the input signals also do not transmit signals to the distributed multiplexed bus interconnect.

4. The method of claim 2, wherein the nodes that do have combining logic are connected together in a tree structure after optimization occurs.

5. The method of claim 4, wherein the removal of unnecessary signal wiring is performed from the bottom of the tree up.

6. The method of claim 1 , wherein a first distributed node connecting to the distributed multiplexed bus interconnect contains combining logic that combines input signals from other nodes and has an output to a next node, wherein the combining logic and the signaling wiring between the first node and the ether nodes supplying the input signals are eliminated when the input signals being transmitting by the other nodes are a constant signal.

7. The method of claim 1 , wherein a first distributed node connecting to the distributed multiplexed bus interconnect contains repeater logic to retransmit to a second node a received signal, wherein the repeater logic and the signaling wiring between the first distributed node and the second distributed node are eliminated when the second node and sub nodes connected to the second node do not receive signals from the distributed multiplexed bus interconnect. 16

8. The method of claim 1 , wherein optimizing further comprises removal from a node connected to the distributed multiplexed bus interconnect selected from the group consisting of combining logic, repeater logic, signaling wiring to a connected node, and root logic.

9. The method of claim 1 , wherein the optimizing is done at a point in time before fabrication of a device containing the distributed multiplexed bus interconnect.

10. A processing system, comprising: a processor, which when executing a set of instructions performs the method of claim 1.

11. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 1.

12. An apparatus, comprising: means for optimizing an amount of signaling wiring present within a distributed multiplexed bus interconnect by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the multiplexed bus interconnect transmits or receives signals from the multiplexed bus interconnect, wherein the multiplexed bus interconnect contains one or more multiplexers to route signals through the multiplexed bus interconnect. 17

13. The apparatus of claim 12 wherein the optimizing of the amount of signaling wires occurs before the apparatus is fabricated.

14. The apparatus of claim 12 wherein the means for optimizing optimizes at a point in time prior to the fabrication of a device containing the multiplexed bus interconnect.

15. A machine-readable medium having stored thereon information representing the apparatus of claim 12.

16. A system, comprising: a plurality of agents; a plurality of interfaces; and a multiplexed bus interconnect containing one or more multiplexers to route signals through the multiplexed bus interconnect connects to the plurality of agents, wherein an amount of signaling wiring connecting to the plurality of agents is optimized by eliminating individual signaling wires based upon whether an Intellectual Property core associated with a particular agent transmits signals onto the multiplexed bus interconnect or receives signals from the multiplexed bus interconnect.

17. The system of claim 16, wherein the multiplexed bus interconnect connecting the plurality of agents is further optimized by at least one of 18 combiner logic optimization, repeater logic optimization, and root logic optimization.

18. The system of claim 17, wherein the optimization is done at a time of system design.