WO2003103031A3 - Formation of lattice-tuning semiconductor substrates - Google Patents

Formation of lattice-tuning semiconductor substrates Download PDF

Info

Publication number
WO2003103031A3
WO2003103031A3 PCT/EP2003/050207 EP0350207W WO03103031A3 WO 2003103031 A3 WO2003103031 A3 WO 2003103031A3 EP 0350207 W EP0350207 W EP 0350207W WO 03103031 A3 WO03103031 A3 WO 03103031A3
Authority
WO
WIPO (PCT)
Prior art keywords
layers
graded
layer
sige
dislocations
Prior art date
Application number
PCT/EP2003/050207
Other languages
French (fr)
Other versions
WO2003103031A2 (en
Inventor
Adam Daniel Capewell
Timothy John Grasby
Evan Horatio Charles Parker
Terence Whall
Original Assignee
Univ Warwick
Adam Daniel Capewell
Timothy John Grasby
Evan Horatio Charles Parker
Terence Whall
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Warwick, Adam Daniel Capewell, Timothy John Grasby, Evan Horatio Charles Parker, Terence Whall filed Critical Univ Warwick
Priority to AU2003251718A priority Critical patent/AU2003251718A1/en
Priority to KR10-2004-7019420A priority patent/KR20050013563A/en
Priority to EP03755984A priority patent/EP1509949B1/en
Priority to US10/514,941 priority patent/US7214598B2/en
Priority to JP2004510018A priority patent/JP2005528795A/en
Publication of WO2003103031A2 publication Critical patent/WO2003103031A2/en
Publication of WO2003103031A3 publication Critical patent/WO2003103031A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types

Abstract

In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited. Each graded SiGe layer is permitted to relax by pile-ups of dislocations, but the uniform SiGe layers 40 prevent the pile-ups of dislocations from extending out of the graded SiGe layers 38. Furthermore each of the subsequent annealing steps ensures that the previously applied graded and uniform SiGe layers 38 and 40 are fully relaxed in spite of the relative thinness of these layers. As a result the dislocations are produced substantially independently within successive pairs of layers 38 and 40, and are relatively evenly distributed with only small surface undulations 40 being produced. Furthermore the density of threading dislocations is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice which can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.
PCT/EP2003/050207 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates WO2003103031A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2003251718A AU2003251718A1 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates
KR10-2004-7019420A KR20050013563A (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates
EP03755984A EP1509949B1 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates
US10/514,941 US7214598B2 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates
JP2004510018A JP2005528795A (en) 2002-05-31 2003-05-30 Formation of lattice-matched semiconductor substrates

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0212616.7A GB0212616D0 (en) 2002-05-31 2002-05-31 Formation of lattice-tuning semiconductor substrates
GB0212616.7 2002-05-31

Publications (2)

Publication Number Publication Date
WO2003103031A2 WO2003103031A2 (en) 2003-12-11
WO2003103031A3 true WO2003103031A3 (en) 2004-04-08

Family

ID=9937802

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/050207 WO2003103031A2 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates

Country Status (8)

Country Link
US (1) US7214598B2 (en)
EP (1) EP1509949B1 (en)
JP (1) JP2005528795A (en)
KR (1) KR20050013563A (en)
CN (1) CN100437905C (en)
AU (1) AU2003251718A1 (en)
GB (1) GB0212616D0 (en)
WO (1) WO2003103031A2 (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004021578A1 (en) 2003-09-17 2005-04-21 Aixtron Ag Method and apparatus for depositing mono- or multi-component layers and layer sequences using non-continuous injection of liquid and dissolved starting substances via a multi-channel injection unit
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US7247583B2 (en) 2004-01-30 2007-07-24 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
GB2411047B (en) * 2004-02-13 2008-01-02 Iqe Silicon Compounds Ltd Compound semiconductor device and method of producing the same
US7118995B2 (en) 2004-05-19 2006-10-10 International Business Machines Corporation Yield improvement in silicon-germanium epitaxial growth
JP2008506617A (en) * 2004-07-15 2008-03-06 アイクストロン、アーゲー Method for depositing a film containing Si and Ge
US7682952B2 (en) 2004-11-30 2010-03-23 Massachusetts Institute Of Technology Method for forming low defect density alloy graded layers and structure containing such layers
EP1705697A1 (en) * 2005-03-21 2006-09-27 S.O.I. Tec Silicon on Insulator Technologies S.A. Composition graded layer structure and method for forming the same
JP2007036134A (en) * 2005-07-29 2007-02-08 Toshiba Corp Semiconductor wafer and method for manufacturing semiconductor device
US7902046B2 (en) * 2005-09-19 2011-03-08 The Board Of Trustees Of The Leland Stanford Junior University Thin buffer layers for SiGe growth on mismatched substrates
WO2007053686A2 (en) 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated semiconductor materials and devices
US20070154637A1 (en) * 2005-12-19 2007-07-05 Rohm And Haas Electronic Materials Llc Organometallic composition
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US8115195B2 (en) 2008-03-20 2012-02-14 Siltronic Ag Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
US20090242989A1 (en) * 2008-03-25 2009-10-01 Chan Kevin K Complementary metal-oxide-semiconductor device with embedded stressor
US8084788B2 (en) * 2008-10-10 2011-12-27 International Business Machines Corporation Method of forming source and drain of a field-effect-transistor and structure thereof
KR20100064742A (en) * 2008-12-05 2010-06-15 한국전자통신연구원 Growth of pure ge layer with low threadin dislocation density
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices
US20110070746A1 (en) * 2009-09-24 2011-03-24 Te-Yin Kao Method of increasing operation speed and saturated current of semiconductor device and method of reducing site flatness and roughness of surface of semiconductor wafer
GB2519338A (en) * 2013-10-17 2015-04-22 Nanogan Ltd Crack-free gallium nitride materials
KR102259328B1 (en) 2014-10-10 2021-06-02 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9842900B2 (en) 2016-03-30 2017-12-12 International Business Machines Corporation Graded buffer layers with lattice matched epitaxial oxide interlayers
US10801895B2 (en) 2017-09-07 2020-10-13 Teledyne Scientific & Imaging, Llc Spectroscopic focal plane array and method of making same
CN109950153B (en) * 2019-03-08 2022-03-04 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN109920738A (en) * 2019-03-08 2019-06-21 中国科学院微电子研究所 Semiconductor structure and its production method
CN109887847A (en) * 2019-03-08 2019-06-14 中国科学院微电子研究所 Semiconductor structure and its production method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759898A (en) * 1993-10-29 1998-06-02 International Business Machines Corporation Production of substrate for tensilely strained semiconductor
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
WO2001054175A1 (en) * 2000-01-20 2001-07-26 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6313016B1 (en) * 1998-12-22 2001-11-06 Daimlerchrysler Ag Method for producing epitaxial silicon germanium layers
US20020017642A1 (en) * 2000-08-01 2002-02-14 Mitsubishi Materials Corporation Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256550A (en) * 1988-11-29 1993-10-26 Hewlett-Packard Company Fabricating a semiconductor device with strained Si1-x Gex layer
US5221413A (en) 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US6107653A (en) * 1997-06-24 2000-08-22 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
JP2003517726A (en) 1999-09-20 2003-05-27 アンバーウェーブ システムズ コーポレイション Fabrication method of relaxed silicon germanium layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759898A (en) * 1993-10-29 1998-06-02 International Business Machines Corporation Production of substrate for tensilely strained semiconductor
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US6313016B1 (en) * 1998-12-22 2001-11-06 Daimlerchrysler Ag Method for producing epitaxial silicon germanium layers
WO2001054175A1 (en) * 2000-01-20 2001-07-26 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US20020017642A1 (en) * 2000-08-01 2002-02-14 Mitsubishi Materials Corporation Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIU J L ET AL: "A SURFACTANT-MEDIATED RELAXED SI0.5GE0.5 GRADED LAYER WITH A VERY LOW THREADING DISLOCATION DENSITY AND SMOOTH SURFACE", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 75, no. 11, 13 September 1999 (1999-09-13), pages 1586 - 1588, XP001040754, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
US7214598B2 (en) 2007-05-08
AU2003251718A1 (en) 2003-12-19
EP1509949A2 (en) 2005-03-02
EP1509949B1 (en) 2012-08-22
WO2003103031A2 (en) 2003-12-11
JP2005528795A (en) 2005-09-22
CN100437905C (en) 2008-11-26
CN1656603A (en) 2005-08-17
GB0212616D0 (en) 2002-07-10
KR20050013563A (en) 2005-02-04
US20050239255A1 (en) 2005-10-27

Similar Documents

Publication Publication Date Title
WO2003103031A3 (en) Formation of lattice-tuning semiconductor substrates
EP1763069B1 (en) Method for forming a semiconductor heterostructure
US9934964B2 (en) Semiconductor heterostructures having reduced dislocation pile-ups and related methods
KR100934037B1 (en) Method for manufacturing semiconductor heterostructure
JP4386333B2 (en) Manufacturing method of semiconductor substrate
EP2016205B1 (en) SEMICONDUCTOR STRAIN RELAXED SiGe BUFFER STRUCTURES
EP1249036A1 (en) Low threading dislocation density relaxed mismatched epilayers without high temperature growth
KR20090032073A (en) Strained layers within semiconductor buffer structures
JP2005537672A5 (en)
WO2004102635A9 (en) Methods for preserving strained semiconductor layers during oxide layer formation
KR20040100893A (en) A method for manufacturing a silicon substrate having a distorted layer
CN111739788A (en) Method for preparing germanium-silicon semiconductor material layer and germanium-silicon semiconductor material layer
WO2020046890A1 (en) Method and device for making superlattice structures with reduced defect densities
EP1714323B1 (en) Compound semiconductor device and method of producing the same
JP2003133548A (en) Semiconductor substrate and field effect transistor, and their manufacturing methods

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003755984

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10514941

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 20038122847

Country of ref document: CN

Ref document number: 1020047019420

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2004510018

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 1020047019420

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003755984

Country of ref document: EP