WO2003105219A1 - A method of fabricating a substrate comprising a useful layer of a monocrystalline semiconductor material - Google Patents

A method of fabricating a substrate comprising a useful layer of a monocrystalline semiconductor material Download PDF

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WO2003105219A1
WO2003105219A1 PCT/IB2003/003068 IB0303068W WO03105219A1 WO 2003105219 A1 WO2003105219 A1 WO 2003105219A1 IB 0303068 W IB0303068 W IB 0303068W WO 03105219 A1 WO03105219 A1 WO 03105219A1
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layer
intermediate support
nucleation
useful
support
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PCT/IB2003/003068
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French (fr)
Inventor
Fabrice Letertre
Bruno Ghyselen
Olivier Rayssac
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S.O.I.T.E.C. Silicon On Insulator Technologies
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Priority claimed from FR0207132A external-priority patent/FR2840730B1/en
Application filed by S.O.I.T.E.C. Silicon On Insulator Technologies filed Critical S.O.I.T.E.C. Silicon On Insulator Technologies
Publication of WO2003105219A1 publication Critical patent/WO2003105219A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

Definitions

  • the present invention relates to a method of fabricating a support carrying a substrate comprising a useful layer of monocrystalline semiconductor material, especially a wide band gap material, and in particular a gallium nitride (GaN) , aluminium nitride (A1N) , or some other mono or poly-metallic nitride substrate, or a diamond substrate.
  • a gallium nitride GaN
  • AlN aluminium nitride
  • diamond substrate a diamond substrate.
  • the most widely known technique for producing a bulk GaN substrate consists in depositing said material on a substrate by hetero-epitaxy .
  • the material of the substrate In order to produce deposited material with good crystal quality, the material of the substrate must present little lattice mismatch relative to the epitaxial monocrystal . Because of the high temperatures involved in hetero-epitaxy, it is also necessary for the thermal expansion coefficient of the substrate material to be relatively close to that of the epitaxial monocrystal. Finally, said substrate must be mechanically and chemically stable at the temperatures under consideration in order to obtain good crystal quality. Naturally, the surface condition and the good crystal quality of the starting substrate are also important factors.
  • Materials that are currently recognized as good candidates having regard to the above criteria are sapphire and silicon carbide (SiC) , although they are far from being optimal as regards their lattice parameters and their expansion coefficients.
  • those substrates are oxides with high temperature chemical stability that is poorer than that of SiC or of sapphire. Said problem with stability manifests itself in the form of dissociation and diffusion of the metal and/or oxygen component elements of the oxide towards the epitaxial layer.
  • the article "Impurity contamination of GaN epitaxial films from the sapphire, SiC, and ZnO substrates”, Popovici et al., Appl . Phys. Lett., 71(23), 8 December 1997 demonstrates contamination by zinc and by oxygen in the case of a ZnO substrate, and that contamination compromises the quality and purity of the epitaxial layer.
  • Appl. Phys., Vol. 41 (2001), p. 140-143 proposes using a gallium arsenide GaAs substrate on which to grow GaN by hetero-epitaxy.
  • GaAs undergoes surface dissociation, which causes arsenic to evaporate, which is likely to contaminate the GaN monocrystal.
  • An aim of the present invention is to overcome the limitations of the prior art and to propose a method for manufacturing a substrate by hetero-epitaxial growth in which a low cost intermediate support can be eliminated by etching while leaving the useful layer substantially unaffected by elements dissociated from said intermediate support.
  • the present invention provides a method for manufacturing a substrate comprising a useful layer of at least one monocrystalline semiconductor material on a support, said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer, said nucleation layer being provided on an intermediate support in the form of a thin layer of nucleation material taken from a source substrate, the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting the material of the nucleation layer so that it forms a barrier against the diffusion of eleme nts deriving from the thermal dissociation of the material of the intermediate support; applying the nucleation layer to the intermediate support; growing the or each monocrystalline semiconductor material of the useful layer on said nucleation layer; bonding the useful layer to a final support at the
  • the first step is carried out by forming a source substrate comprising a detachment zone at a certain depth, by bonding the source substrate to the intermediate support, and by carrying out a treatment on the zone forming the detachment site to detach a thin layer from the source substrate;
  • said detachment treatment comprises applying stresses included in the group formed by thermal stresses and mechanical stresses;
  • the intermediate support is selected from the group formed by silicon, gallium arsenide, zinc oxide, lithium gallium oxide, and lithium aluminium oxide;
  • the useful layer comprises at least one mono or poly-metallic nitride; • the useful layer is constituted by gallium nitride, and the material of the nucleation layer is selected from the group formed by silicon carbide, gallium nitride and sapphire; and
  • the present invention provides a method for manufacturing a substrate comprising a useful layer of at least one monocrystalline semiconductor material on a support, said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer, said nucleation layer being provided on an intermediate support in the form of a thin layer of nucleation material taken from a source substrate, the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting a barrier material capable of forming a barrier against the diffusion of elements deriving from the thermal dissociation of the material of the intermediate support; providing one face of the intermediate support with a barrier layer made of the barrier material and with the nucleation layer; growing the or each monocrystalline semiconductor material
  • the barrier layer and/or nucleation layer is/are formed by providing a source substrate comprising a zone forming a detachment site at a certain depth, by bonding the source substrate to the intermediate support, and by carrying out a treatment on the zone forming the detachment site to detach the layer in question from the source substrate;
  • the barrier layer is applied to the intermediate support and/or the nucleation layer is applied to the barrier layer by molecular bonding
  • Figure 1A shows a source substrate 10, for example of monocrystalline silicon carbide SiC, in which ions, for example hydrogen ions, have been implanted at a certain depth using an ionic bombardment machine, a plasma implantation machine, etc.
  • Said implantation defines a thin layer 12 from the remainder of the source substrate, the main concentration of hydrogen ions being indicated at 14.
  • implantation is carried out to a depth in the range 200 nanometers (nm) to 1000 n , using ions with energy in the range 50 kilo electron volts (keV) to 200 keV, and an implantation dose in the range 5 x 10 l ⁇ ions per square centimeter (ions/cm 2 ) to 1 x 10 17 ions/cm 2 .
  • substrate 10 carrying layer 12 is then bonded by molecular bonding to a substrate forming a growth support 20 formed here from monocrystalline gallium arsenide GaAs.
  • Said substrate 20 typically has a thickness in the range 400 micrometers ( ⁇ m) to 800 ⁇ m.
  • the faces of substrate 10 and substrate 20 to be assembled together have been provided with bonding layers 13, 23, in particular of silicon oxide Si0 2 or silicon nitride Si 3 N 4 , in a manner that is known per se.
  • Said bonding layers when formed from Si0 2 on Si, are advantageously formed by thermal oxidation, or alternatively, by deposition.
  • the bonding energy of the bonding interface is brought to the required level by heat treatment, typically at a temperature of more than 300 °C for a period that is typically 2 hours.
  • a heat treatment is typically carried out at a temperature in the range 800°C to 900°C for a period in the range 30 minutes to 3 hours. Such heat treatment can be combined with that used to strengthen the bonding interface .
  • a structure comprising a GaAs growth support 20 carrying a thin nucleation layer 12 of monocrystalline SiC is obtained.
  • the free surface of said layer can undergo polishing/cleaning and in particular chemical-mechanical polishing or ion beam smoothing intended to allow good-quality epitaxial growth to be performed thereon.
  • MOCVD metal organic chemical vapor deposition
  • Such an operation is carried out at a temperature of the order of 1050°C to 1100°C, at which temperature partial dissociation of the GaAs forming the support 20 is observed.
  • the presence of the SiC nucleation layer 12, which forms a barrier layer against the diffusion of atoms of arsenic or gallium towards the deposited layer 30, prevents disturbance of the crystal quality and the purity of said layer 30.
  • Said stack is typically a few microns thick, i.e., it is a thin layer, as opposed to the thick layers with a minimum thickness of about 200 ⁇ m to 300 ⁇ m, rendering the stack self-supporting.
  • Figure ID shows the resulting structure.
  • the assembly constituted by layers 20, 23, 13, 12 and 30 is applied to a target substrate 40 of monocrystalline or polycrystalline silicon intended to constitute the final support of the GaN useful layer.
  • said final support 40 advantageously has metallization 41 allowing the final support to constitute a reflector for visible or UV radiation emitted by the electroluminescent components which have been formed in the useful layer 30.
  • This metallization is preferably formed by cathode sputtering or vacuum evaporation of gold, tin, or palladium (or of any suitable alloy) with a thickness of 500 nm, for example .
  • the free surface of the GaN stack 30 undergoes polishing treatment, typically a chemical-mechanical polishing or ion beam smoothing intended to endow it with a flatness that is suitable for molecular bonding with the target substrate 40, which itself must have a satisfactory flatness produced prior to metallization.
  • polishing treatment typically a chemical-mechanical polishing or ion beam smoothing intended to endow it with a flatness that is suitable for molecular bonding with the target substrate 40, which itself must have a satisfactory flatness produced prior to metallization.
  • the thickness of substrate 40 is typically in the range 300 ⁇ m to 500 ⁇ m.
  • Fixing is achieved in this case by molecular bonding or by eutectic bonding (which means that polishing can be dispensed with) , if necessary supplying heat energy at a temperature in the range 200°C to 350 °C for several hours to produce the desired bonding forces.
  • the GaN stack 30 can undergo all or some treatments for producing components such as blue or green LEDs, laser diodes, etc.
  • the assembly is then exposed to chemical etching with a solution composed of a mixture of HF, HN0 3 , CH 3 COOH, and H 2 0 in proportions of 1:3:3:5 to etch the intermediate GaAs support 20 and remove it completely.
  • the final step consists of removing, preferably by ionic etching, the nucleation layer and, if appropriate, the bonding layers 13 and 23 if they have not been removed chemically. During this operation, it is also possible to remove a portion of the epitaxial layers that have been formed, in particular to remove initial epitaxial layers containing defects.
  • the method described above can be endowed with a variety of variants.
  • nucleation layer 12 is principally conditioned by the search for a compromise between the lattice parameter, thermal expansion coefficient, stability at high temperatures, ability to form a barrier layer against the diffusion of elements from possible partial decomposition of the layer forming the intermediate support.
  • SiC as indicated above is selected, or GaN, or even sapphire is selected.
  • the material of the intermediate support 20 is not critical as regards lattice parameter, but it is selected principally as a result of finding a compromise between its thermal expansion coefficient compared with that of the material of the epitaxial layer, the stability of the epitaxial layer to high temperatures, and in particular the facility with which it is removed chemically.
  • GaAs silicon, certain oxides such as ZnO, or LiGa 2 or NdGa0 3 can in particular be used.
  • the material deposited by epitaxial growth to form the useful layer or layers of the substrate is typically a stack of differently doped layers of GaN, in a manner that is known per se. However, it can also be a stack of a variety of other metal nitrides such as A1N or GaAlN, etc.
  • the final support 40 can be constituted by any support are selected as a function of a compromise between its ability to receive the metallization 41 if appropriate, its ability to receive the deposited layer 30 by bonding or any other technique, its properties in terms of mechanical and chemical stability during treatments for producing components in the stack of layers 30, its thermal properties, its fabrication cost, etc.
  • the barrier layer can be formed, deposited or applied either onto the source substrate 10, or onto the intermediate support 20, prior to bonding.
  • EXAMPLE A 500 nm thick layer of Si0 2 is produced on one face of a monocrystalline SiC source substrate by thermal oxidation. Hydrogen ions are then implanted with an energy of 100 keV and using a dose of 8 x 10 16 ions/cm 2 into the source substrate using ion bombardment equipment.
  • a 500 ⁇ m thick monocrystalline GaAs substrate intended to form the intermediate support is also prepared, and one face of the substrate is coated with a 500 nm thick Si0 2 layer by chemical vapor deposition.
  • Surface activation is then carried out, for example by chemical-mechanical polishing, to smooth the surfaces and provide them with a certain hydrophilic nature.
  • the faces of the source substrate and the intermediate support substrate are then brought together and bonded, and a suitable bonding energy is obtained by heat treatment at 350°C for a period of 2 hours.
  • This assembly then undergoes heat treatment at 900 °C for a period of one hour to obtain detachment at the implanted zone.
  • the face of the layer 12 is then polished at the detachment location using ionic smoothing by ion cluster smoothing.
  • GaN stack 30 has the following succession of layers:
  • the free face of the stack 30 is polished by an ion cluster technique
  • a monocrystalline silicon substrate with a normal commercial grade of surface polishing and a thickness of 500 ⁇ m is coated with a metallization based on indium/palladium over a thickness of 400 nm.
  • the intermediate support 20 carrying the stack 30 and the substrate 40 carrying the metallization 41 are then bonded together by molecular bonding, the bonding interface being reinforced by heat treatment at 350 °C for a period of 2 hours .
  • the GaAs intermediate support is then etched by immersion in an etching solution composed of a mixture of HF, HN0 3 , CH 3 COOH, and H 2 0 in proportions of 1:3:3:5, peripheral etching of the metallic layer 41 being minor and without consequence.
  • an etching solution composed of a mixture of HF, HN0 3 , CH 3 COOH, and H 2 0 in proportions of 1:3:3:5, peripheral etching of the metallic layer 41 being minor and without consequence.
  • This latter layer is then removed, for example by SF 6 /0 2 reactive ionic etching.

Abstract

A method for manufacturing a substrate comprising a useful layer (30) of at least one monocrystalline semiconductor material on a support (40) involves an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer (12). The nucleation layer is provided on an intermediate support (20) in the form of a thin layer of nucleation material taken from a source substrate (10). The following steps are performed: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting the material of the nucleation layer so that it forms a barrier against the diffusion of elements deriving from the thermal dissociation of the material of the intermediate support; applying the nucleation layer (12) to the intermediate support (20); growing the or each monocrystalline semiconductor material of the useful layer (30) on said nucleation layer (12); bonding the useful layer (30) to a final support (40) at the face of said useful layer opposite to the intermediate support; and exposing said intermediate support (20) to said etching medium to remove it by chemical etching substantially without affecting the useful layer. Application to producing optoelectronic components such as LEDs based on thin layer metallic nitrides.

Description

A METHOD OP FABRICATING A SUBSTRATE COMPRISING A USEFUL LAYER OF A MONOCRYSTALLINE SEMICONDUCTOR MATERIAL
The present invention relates to a method of fabricating a support carrying a substrate comprising a useful layer of monocrystalline semiconductor material, especially a wide band gap material, and in particular a gallium nitride (GaN) , aluminium nitride (A1N) , or some other mono or poly-metallic nitride substrate, or a diamond substrate.
Technologies based on GaN, A1N, and compounds thereof currently suffer from a dearth of large-sized bulk substrates of such materials.
The most widely known technique for producing a bulk GaN substrate consists in depositing said material on a substrate by hetero-epitaxy .
In order to produce deposited material with good crystal quality, the material of the substrate must present little lattice mismatch relative to the epitaxial monocrystal . Because of the high temperatures involved in hetero-epitaxy, it is also necessary for the thermal expansion coefficient of the substrate material to be relatively close to that of the epitaxial monocrystal. Finally, said substrate must be mechanically and chemically stable at the temperatures under consideration in order to obtain good crystal quality. Naturally, the surface condition and the good crystal quality of the starting substrate are also important factors.
Materials that are currently recognized as good candidates having regard to the above criteria are sapphire and silicon carbide (SiC) , although they are far from being optimal as regards their lattice parameters and their expansion coefficients.
The growth of layers of GaN on substrates of zirconium oxide ZnO, or lithium gallium oxide LiGa02, or lithium aluminium oxide LiA102 (see the article "Growth of Ill- Nitrides on ZnO, LiGa02 and LiA102 substrates", Mackenzie et al., J. Electrochem. Soc, vol. 145, N° 7, July 1998, p. 2581) or of neodymium gallium oxide NdGa03 (see the article "GaN bulk substrates for GaN based LEDs and LDs", Oda et al., Phys. Stat. Sol., (a) 180, 51 (2000)), has also been described, said materials having been selected for their small lattice mismatch relative to GaN and their small coefficient of expansion difference compared with GaN.
However, those substrates are oxides with high temperature chemical stability that is poorer than that of SiC or of sapphire. Said problem with stability manifests itself in the form of dissociation and diffusion of the metal and/or oxygen component elements of the oxide towards the epitaxial layer. In the case of a ZnO substrate, the article "Impurity contamination of GaN epitaxial films from the sapphire, SiC, and ZnO substrates", Popovici et al., Appl . Phys. Lett., 71(23), 8 December 1997, demonstrates contamination by zinc and by oxygen in the case of a ZnO substrate, and that contamination compromises the quality and purity of the epitaxial layer. Further, once the layer or layers intended to form the substrate have been formed, in the majority of cases the support on which growth has been carried out has to be removed, which necessitates either chemical etching of said support and thus its loss even if it is produced from an expensive material, thereby increasing the cost of the process, or by rupture between the layers formed by epitaxial growth and said support.
More generally, it has been proven that, for the purpose of temporary support removal, the chip manufacturers would mostly prefer an etching technique than a rupture technique. This is mainly because in the industry of semiconductors, etching techniques have been well mastered for years and most often do not require any significant investment, while ruptures techniques might be difficult to control and/or require significant additional investment and add complexity to the whole process. In parallel, an etching approach would be economically valuable only if the material of the support is reasonably inexpensive, but such inexpensive materials, such as gallium arsenide GaAs, bring other drawbacks. In this regard, the paper "Preparation of large freestanding GaN substrates by Hydride Vapor Phase Epitaxy using GaAs as a starting substrate", Motoki et al., Jpn . J. Appl. Phys., Vol. 41 (2001), p. 140-143, proposes using a gallium arsenide GaAs substrate on which to grow GaN by hetero-epitaxy. However, when heated to the high temperatures involved in epitaxy, GaAs undergoes surface dissociation, which causes arsenic to evaporate, which is likely to contaminate the GaN monocrystal.
An aim of the present invention is to overcome the limitations of the prior art and to propose a method for manufacturing a substrate by hetero-epitaxial growth in which a low cost intermediate support can be eliminated by etching while leaving the useful layer substantially unaffected by elements dissociated from said intermediate support.
In a first aspect, the present invention provides a method for manufacturing a substrate comprising a useful layer of at least one monocrystalline semiconductor material on a support, said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer, said nucleation layer being provided on an intermediate support in the form of a thin layer of nucleation material taken from a source substrate, the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting the material of the nucleation layer so that it forms a barrier against the diffusion of eleme nts deriving from the thermal dissociation of the material of the intermediate support; applying the nucleation layer to the intermediate support; growing the or each monocrystalline semiconductor material of the useful layer on said nucleation layer; bonding the useful layer to a final support at the face of said useful layer opposite to the intermediate support; and exposing said intermediate support to said etching medium to remove it by chemical etching substantially without affecting the useful layer, substantially without affecting the useful layer. Certain preferred, but non-limiting features of the method are as follows: • the first step is carried out by forming a source substrate comprising a detachment zone at a certain depth, by bonding the source substrate to the intermediate support, and by carrying out a treatment on the zone forming the detachment site to detach a thin layer from the source substrate;
• the detachment zone is produced by implanting atomic species;
• said detachment treatment comprises applying stresses included in the group formed by thermal stresses and mechanical stresses;
• the nucleation layer is applied to the intermediate support by molecular bonding;
• before applying the nucleation layer to said intermediate support, a bonding layer is deposited on at least one of these two parts;
• the intermediate support is selected from the group formed by silicon, gallium arsenide, zinc oxide, lithium gallium oxide, and lithium aluminium oxide;
• the useful layer comprises at least one mono or poly-metallic nitride; • the useful layer is constituted by gallium nitride, and the material of the nucleation layer is selected from the group formed by silicon carbide, gallium nitride and sapphire; and
• the final support comprises a radiation- reflective coating on its surface receiving the useful layer. In a second aspect, the present invention provides a method for manufacturing a substrate comprising a useful layer of at least one monocrystalline semiconductor material on a support, said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer, said nucleation layer being provided on an intermediate support in the form of a thin layer of nucleation material taken from a source substrate, the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting a barrier material capable of forming a barrier against the diffusion of elements deriving from the thermal dissociation of the material of the intermediate support; providing one face of the intermediate support with a barrier layer made of the barrier material and with the nucleation layer; growing the or each monocrystalline semiconductor material of the useful layer on said nucleation layer; bonding the useful layer to a final support at the face of said useful layer opposite to the intermediate support; and exposing said intermediate support to said etching medium to remove it by chemical etching substantially without affecting the useful layer which is protected by the barrier layer.
Preferred but non-limiting features of said second method are as follows :
• the barrier layer and/or nucleation layer is/are formed by providing a source substrate comprising a zone forming a detachment site at a certain depth, by bonding the source substrate to the intermediate support, and by carrying out a treatment on the zone forming the detachment site to detach the layer in question from the source substrate;
• the barrier layer is applied to the intermediate support and/or the nucleation layer is applied to the barrier layer by molecular bonding;
• before applying the barrier layer and/or the nucleation layer by bonding, a layer of adhesive is deposited on at least one of the faces to be bonded. Other aspects, aims and advantages of the present invention become clear from the following description of a preferred implementation, given by way of non-limiting example and made with reference to the accompanying drawings in which Figures 1A to 1G illustrate the successive steps of a method in accordance with the invention. Referring to Figures 1A to 1G, Figure 1A shows a source substrate 10, for example of monocrystalline silicon carbide SiC, in which ions, for example hydrogen ions, have been implanted at a certain depth using an ionic bombardment machine, a plasma implantation machine, etc. Said implantation defines a thin layer 12 from the remainder of the source substrate, the main concentration of hydrogen ions being indicated at 14. Typically, implantation is carried out to a depth in the range 200 nanometers (nm) to 1000 n , using ions with energy in the range 50 kilo electron volts (keV) to 200 keV, and an implantation dose in the range 5 x 10lδ ions per square centimeter (ions/cm2) to 1 x 1017 ions/cm2.
Referring to Figure IB, substrate 10 carrying layer 12 is then bonded by molecular bonding to a substrate forming a growth support 20 formed here from monocrystalline gallium arsenide GaAs. Said substrate 20 typically has a thickness in the range 400 micrometers (μm) to 800 μm.
Optionally, the faces of substrate 10 and substrate 20 to be assembled together have been provided with bonding layers 13, 23, in particular of silicon oxide Si02 or silicon nitride Si3N4, in a manner that is known per se. Said bonding layers, when formed from Si02 on Si, are advantageously formed by thermal oxidation, or alternatively, by deposition. The bonding energy of the bonding interface is brought to the required level by heat treatment, typically at a temperature of more than 300 °C for a period that is typically 2 hours.
Stresses, in particular thermal and/or mechanical stresses, but which could be of some other nature, are exerted so as to detach the assembly constituted by the substrate 20 and the layer 12 from the remainder of the substrate 10 at the implanted zone 14, using the known
Smart-Cut® technique developed by the Applicant. To this end, a heat treatment is typically carried out at a temperature in the range 800°C to 900°C for a period in the range 30 minutes to 3 hours. Such heat treatment can be combined with that used to strengthen the bonding interface . As illustrated in Figure 1C, a structure comprising a GaAs growth support 20 carrying a thin nucleation layer 12 of monocrystalline SiC is obtained. The free surface of said layer can undergo polishing/cleaning and in particular chemical-mechanical polishing or ion beam smoothing intended to allow good-quality epitaxial growth to be performed thereon.
A metal organic chemical vapor deposition (MOCVD) hetero-epitaxy technique is carried out on this surface to produce a stack of deposits of gallium nitride GaN with different types of doping, said technique being known to produce a GaN stack 30 of good crystal quality.
Such an operation is carried out at a temperature of the order of 1050°C to 1100°C, at which temperature partial dissociation of the GaAs forming the support 20 is observed. However, the presence of the SiC nucleation layer 12, which forms a barrier layer against the diffusion of atoms of arsenic or gallium towards the deposited layer 30, prevents disturbance of the crystal quality and the purity of said layer 30.
Said stack is typically a few microns thick, i.e., it is a thin layer, as opposed to the thick layers with a minimum thickness of about 200 μm to 300 μm, rendering the stack self-supporting. Figure ID shows the resulting structure.
After growth of the GaN stack 30, the assembly constituted by layers 20, 23, 13, 12 and 30 is applied to a target substrate 40 of monocrystalline or polycrystalline silicon intended to constitute the final support of the GaN useful layer.
At its surface receiving the useful GaN layer, said final support 40 advantageously has metallization 41 allowing the final support to constitute a reflector for visible or UV radiation emitted by the electroluminescent components which have been formed in the useful layer 30. This metallization is preferably formed by cathode sputtering or vacuum evaporation of gold, tin, or palladium (or of any suitable alloy) with a thickness of 500 nm, for example .
The free surface of the GaN stack 30 undergoes polishing treatment, typically a chemical-mechanical polishing or ion beam smoothing intended to endow it with a flatness that is suitable for molecular bonding with the target substrate 40, which itself must have a satisfactory flatness produced prior to metallization.
The thickness of substrate 40 is typically in the range 300 μm to 500 μm.
Fixing is achieved in this case by molecular bonding or by eutectic bonding (which means that polishing can be dispensed with) , if necessary supplying heat energy at a temperature in the range 200°C to 350 °C for several hours to produce the desired bonding forces.
If necessary, prior to said fixing operation, the GaN stack 30 can undergo all or some treatments for producing components such as blue or green LEDs, laser diodes, etc. The assembly is then exposed to chemical etching with a solution composed of a mixture of HF, HN03, CH3COOH, and H20 in proportions of 1:3:3:5 to etch the intermediate GaAs support 20 and remove it completely.
The final step consists of removing, preferably by ionic etching, the nucleation layer and, if appropriate, the bonding layers 13 and 23 if they have not been removed chemically. During this operation, it is also possible to remove a portion of the epitaxial layers that have been formed, in particular to remove initial epitaxial layers containing defects. The method described above can be endowed with a variety of variants.
Firstly, the choice of nucleation layer 12 is principally conditioned by the search for a compromise between the lattice parameter, thermal expansion coefficient, stability at high temperatures, ability to form a barrier layer against the diffusion of elements from possible partial decomposition of the layer forming the intermediate support. Preferably, either SiC as indicated above is selected, or GaN, or even sapphire is selected.
In contrast, the material of the intermediate support 20 is not critical as regards lattice parameter, but it is selected principally as a result of finding a compromise between its thermal expansion coefficient compared with that of the material of the epitaxial layer, the stability of the epitaxial layer to high temperatures, and in particular the facility with which it is removed chemically.
Apart from GaAs, silicon, certain oxides such as ZnO, or LiGa2 or NdGa03 can in particular be used.
Further, the material deposited by epitaxial growth to form the useful layer or layers of the substrate is typically a stack of differently doped layers of GaN, in a manner that is known per se. However, it can also be a stack of a variety of other metal nitrides such as A1N or GaAlN, etc.
Finally, the final support 40 can be constituted by any support are selected as a function of a compromise between its ability to receive the metallization 41 if appropriate, its ability to receive the deposited layer 30 by bonding or any other technique, its properties in terms of mechanical and chemical stability during treatments for producing components in the stack of layers 30, its thermal properties, its fabrication cost, etc.
In a variant, not shown, it is possible to form two distinct layers, deposited on or applied to the intermediate support, one forming a barrier to the diffusion of elements deriving from dissociation of the material of the intermediate support, and the other, outer layer, forming a nucleation layer. It should be noted in this respect that the barrier layer can be formed, deposited or applied either onto the source substrate 10, or onto the intermediate support 20, prior to bonding. EXAMPLE A 500 nm thick layer of Si02 is produced on one face of a monocrystalline SiC source substrate by thermal oxidation. Hydrogen ions are then implanted with an energy of 100 keV and using a dose of 8 x 1016 ions/cm2 into the source substrate using ion bombardment equipment.
A 500 μm thick monocrystalline GaAs substrate intended to form the intermediate support is also prepared, and one face of the substrate is coated with a 500 nm thick Si02 layer by chemical vapor deposition.
Surface activation is then carried out, for example by chemical-mechanical polishing, to smooth the surfaces and provide them with a certain hydrophilic nature.
The faces of the source substrate and the intermediate support substrate are then brought together and bonded, and a suitable bonding energy is obtained by heat treatment at 350°C for a period of 2 hours.
This assembly then undergoes heat treatment at 900 °C for a period of one hour to obtain detachment at the implanted zone.
The face of the layer 12 is then polished at the detachment location using ionic smoothing by ion cluster smoothing.
Different GaN layers are then deposited by epitaxial growth. Typically, said GaN stack 30 has the following succession of layers:
• an 8 nm A1N buffer layer;
• a 1 μm GaN layer.
After said operation, the free face of the stack 30 is polished by an ion cluster technique
Meanwhile, a monocrystalline silicon substrate with a normal commercial grade of surface polishing and a thickness of 500 μm is coated with a metallization based on indium/palladium over a thickness of 400 nm. The intermediate support 20 carrying the stack 30 and the substrate 40 carrying the metallization 41 are then bonded together by molecular bonding, the bonding interface being reinforced by heat treatment at 350 °C for a period of 2 hours .
The GaAs intermediate support is then etched by immersion in an etching solution composed of a mixture of HF, HN03, CH3COOH, and H20 in proportions of 1:3:3:5, peripheral etching of the metallic layer 41 being minor and without consequence.
Said etching finishes at the SiC layer 12.
This latter layer is then removed, for example by SF6/02 reactive ionic etching.
Clearly, the present invention is not limited to the implementation described and shown in the drawings, and the skilled person is capable of providing variants and modifications .

Claims

1. A method for manufacturing a substrate comprising a useful layer (30) of at least one monocrystalline semiconductor material on a support (40) , said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer (12), said nucleation layer being provided on an intermediate support (20) in the form of a thin layer of nucleation material taken from a source substrate (10) , the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting the material of the nucleation layer so that it forms a barrier against the diffusion of elements deriving from the thermal dissociation of the material of the intermediate support;- applying the nucleation layer (12) to the intermediate support (20) ; growing the or each monocrystalline semiconductor material of the useful layer (30) on said nucleation layer (12); bonding the useful layer (30) to a final support (40) at the face of said useful layer opposite to the intermediate support; and exposing said intermediate support (20) to said etching medium to remove it by chemical etching substantially without affecting the useful layer.
2. A method according to claim 1, characterized in that the first step is carried out by forming a source substrate (10) comprising a detachment zone (14) at a certain depth, by bonding the source substrate to the intermediate support, and by carrying out a treatment on the zone forming the detachment site to detach a thin layer (12) from the source substrate.
3. A method according to claim 2, characterized in that the detachment zone (14) is produced by implanting atomic species .
4. A method according to claim 3, characterized in that said detachment treatment comprises applying stresses included in the group formed by thermal stresses and mechanical stresses.
5. A method according to any one of claims 1 to 4, characterized in that the nucleation layer (12) is applied to the intermediate support (20) by molecular bonding.
6. A method according to claim 5, characterized in that before applying the nucleation layer (12) to said intermediate support (20) , a bonding layer (13; 23) is deposited on at least one of said two parts.
7. A method according to any one of claims 1 to 6, characterized in that the intermediate support (20) is selected from the group formed by silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminium oxide.
8. A method according to any one of claims 1 to 7, characterized in that the useful layer (30) comprises at least one mono or poly-metallic nitride.
9. A method according to any one of claims 1 to 8, characterized in that the useful layer (30) is constituted by gallium nitride, and in that the material of the nucleation layer (12) is selected from the group formed by silicon carbide, gallium nitride and sapphire.
10. A method according to any one of claims 1 to 9, characterized in that the final support (40) comprises a radiation-reflective coating (41) on its surface receiving the useful layer (30) .
11. A method for manufacturing a substrate comprising a useful layer (30) of at least one monocrystalline semiconductor material on a support (40), said method involving an epitaxial growing of the monocrystalline semiconductor material on a nucleation layer (12), said nucleation layer being provided on an intermediate support (20) in the form of a thin layer of nucleation material taken from a source substrate (10) , the method comprising the following steps: selecting the material of intermediate support so that it can be chemically etched by a given etching medium, it is liable to thermal dissociation when exposed to the temperature of epitaxial growing, and it is less expensive than materials which are less liable to thermal dissociation at said temperature of epitaxial growing, selecting a barrier material capable of forming a barrier against the diffusion of elements deriving from the thermal dissociation of the material of the intermediate support; providing one face of the intermediate support
(20) with a barrier layer made of the barrier material and with the nucleation layer (12) , growing the or each monocrystalline semiconductor material of the useful layer (30) on said nucleation layer (12); bonding the useful layer (30) to a final support (40) at the face of said useful layer opposite to the intermediate support; and exposing said intermediate support (20) to said etching medium to remove it by chemical etching substantially without affecting the useful layer which is protected by the barrier layer.
12. A method according to claim 11, characterized in that the barrier layer and/or the nucleation layer is/are formed by providing a source substrate (10) comprising a zone (14) forming a detachment site at a certain depth, by bonding the source substrate to the intermediate support (20) , and by carrying out a treatment on the zone forming the detachment site to detach the layer in question from the source substrate.
13. A method according to claim 12, characterized in that the detachment zone (14) is produced by implanting atomic species.
14. A method according to claim 13, characterized in that said detachment treatment comprises applying stresses included in the group formed by thermal stresses and mechanical stresses.
15. A method according to any one of claims 11 to 14, characterized in that the barrier layer is applied to the intermediate support (20) and/or the nucleation layer (12) is applied to the barrier layer by molecular bonding.
16. A method according to claim 15, characterized in that before applying the barrier layer and/or the nucleation layer (12) by bonding, a layer of adhesive (13; 23) is deposited on at least one of the faces to be bonded.
17. A method according to claim 11, characterized in that the barrier layer and/or the nucleation layer (12) is/are formed by a deposition technique.
18. A method according to any one of claims 11 to 17, characterized in that the intermediate support is selected from the group formed by silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminium oxide.
19. A method according to any one of claims 11 to 18, characterized in that the useful layer comprises at least one mono or poly-metallic nitride.
20. A method according to any one of claims 11 to 19, characterized in that the useful layer is constituted by gallium nitride, and in that the material of the nucleation layer is selected from the group formed by silicon carbide, gallium nitride and sapphire.
21. A method according to any one of claims 11 to 20, characterized in that the final support comprises a radiation-reflective coating 41 on its surface receiving the useful layer (30) .
PCT/IB2003/003068 2002-06-11 2003-06-11 A method of fabricating a substrate comprising a useful layer of a monocrystalline semiconductor material WO2003105219A1 (en)

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FR0207132 2002-06-11
FR0300780 2003-01-24
FR0300780A FR2840731B3 (en) 2002-06-11 2003-01-24 METHOD FOR MANUFACTURING A SUBSTRATE HAVING A USEFUL LAYER OF SINGLE-CRYSTAL SEMICONDUCTOR MATERIAL OF IMPROVED PROPERTIES

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US20030232487A1 (en) 2003-12-18
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US7265029B2 (en) 2007-09-04

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